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OMAP3: zoom1: Configure GPMC for Ethernet
zoom1 uses LAN9211 configured over GPMC Chip Select 1. Signed-off-by: Nishanth Menon <nm@ti.com>
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@ -18,6 +18,7 @@
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#include <netdev.h>
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#include <netdev.h>
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#include <twl4030.h>
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#include <twl4030.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/sys_proto.h>
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@ -26,6 +27,20 @@
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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/* gpmc_cfg is initialized by gpmc_init and we use it here */
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extern struct gpmc *gpmc_cfg;
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/* GPMC definitions for Ethenet Controller LAN9211 */
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static const u32 gpmc_lab_enet[] = {
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ZOOM1_ENET_GPMC_CONF1,
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ZOOM1_ENET_GPMC_CONF2,
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ZOOM1_ENET_GPMC_CONF3,
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ZOOM1_ENET_GPMC_CONF4,
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ZOOM1_ENET_GPMC_CONF5,
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ZOOM1_ENET_GPMC_CONF6,
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/*CONF7- computed as params */
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};
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/*
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/*
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* Routine: board_init
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* Routine: board_init
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* Description: Early hardware init.
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* Description: Early hardware init.
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@ -33,6 +48,9 @@ DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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int board_init(void)
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{
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* CS1 is Ethernet LAN9211 */
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enable_gpmc_cs_config(gpmc_lab_enet, &gpmc_cfg->cs[1],
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DEBUG_BASE, GPMC_SIZE_16M);
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/* board id for Linux */
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/* board id for Linux */
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gd->bd->bi_arch_number = MACH_TYPE_OMAP_LDP;
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gd->bd->bi_arch_number = MACH_TYPE_OMAP_LDP;
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/* boot param addr */
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/* boot param addr */
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@ -17,6 +17,13 @@ const omap3_sysinfo sysinfo = {
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"NAND",
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"NAND",
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};
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};
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#define ZOOM1_ENET_GPMC_CONF1 0x00611000
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#define ZOOM1_ENET_GPMC_CONF2 0x001F1F01
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#define ZOOM1_ENET_GPMC_CONF3 0x00080803
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#define ZOOM1_ENET_GPMC_CONF4 0x1D091D09
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#define ZOOM1_ENET_GPMC_CONF5 0x041D1F1F
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#define ZOOM1_ENET_GPMC_CONF6 0x1D0904C4
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/*
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/*
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* IEN - Input Enable
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* IEN - Input Enable
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* IDIS - Input Disable
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* IDIS - Input Disable
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@ -94,13 +101,13 @@ const omap3_sysinfo sysinfo = {
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MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
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MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
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MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
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MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
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MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
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MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
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MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M7)) /*GPMC_nCS1*/\
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MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
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MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M7)) /*GPMC_nCS2*/\
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MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | DIS | M7)) /*GPMC_nCS2*/\
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MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M7)) /*GPMC_nCS3*/\
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MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | DIS | M4)) /*GPMC_nCS3 -> GPIO54*/\
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MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M7)) /*GPMC_nCS4*/\
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MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | DIS | M4)) /*GPMC_nCS4 -> GPIO 55*/\
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MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M7)) /*GPMC_nCS5*/\
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MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M4)) /*GPMC_nCS5 -> GPIO 56*/\
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MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /*GPMC_nCS6*/\
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MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /*GPMC_nCS6*/\
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MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M7)) /*GPMC_nCS7*/\
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MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*GPMC_nCS7 -> GPMC_IO_DIR*/\
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MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
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MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
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MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
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MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
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MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
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MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
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