mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 20:56:16 +09:00
Merge tag 'ti-v2020.10-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- Added support for J7200 evm - DM_ETH and DM_USB migrations for omap3 - USB DFU and mass storage support for AM65x evm - RTI watchdog support for K3 devices - Fix an issue with L3 cache on K3 devices
This commit is contained in:
Tom Rini
commit
c25344ff9a
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@ -955,7 +955,9 @@ dtb-$(CONFIG_STM32MP15x) += \
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||||||
|
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||||||
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb
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dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb
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||||||
dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
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dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
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k3-j721e-r5-common-proc-board.dtb
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k3-j721e-r5-common-proc-board.dtb \
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k3-j7200-common-proc-board.dtb \
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k3-j7200-r5-common-proc-board.dtb
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||||||
dtb-$(CONFIG_ARCH_MEDIATEK) += \
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dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt7622-rfb.dtb \
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mt7622-rfb.dtb \
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|
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@ -230,4 +230,13 @@
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};
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};
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};
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};
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};
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};
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mcu_rti1: rti@40610000 {
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compatible = "ti,j7-rti-wdt";
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reg = <0x0 0x40610000 0x0 0x100>;
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clocks = <&k3_clks 135 0>;
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power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
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assigned-clocks = <&k3_clks 135 0>;
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assigned-clock-parents = <&k3_clks 135 4>;
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||||||
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};
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};
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};
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|
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|
@ -62,7 +62,7 @@
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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cbass_main: interconnect@100000 {
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cbass_main: bus@100000 {
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compatible = "simple-bus";
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compatible = "simple-bus";
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#address-cells = <2>;
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#address-cells = <2>;
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#size-cells = <2>;
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#size-cells = <2>;
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@ -87,7 +87,7 @@
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<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
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<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
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<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
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<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
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cbass_mcu: interconnect@28380000 {
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cbass_mcu: bus@28380000 {
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compatible = "simple-bus";
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compatible = "simple-bus";
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#address-cells = <2>;
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#address-cells = <2>;
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#size-cells = <2>;
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#size-cells = <2>;
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@ -104,7 +104,7 @@
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<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
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<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
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<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/
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<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/
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cbass_wakeup: interconnect@42040000 {
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cbass_wakeup: bus@42040000 {
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compatible = "simple-bus";
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compatible = "simple-bus";
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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#size-cells = <1>;
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|
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@ -139,6 +139,12 @@
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u-boot,dm-spl;
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u-boot,dm-spl;
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};
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};
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usb0_pins_default: usb0_pins_default {
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pinctrl-single,pins = <
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||||||
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AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
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|
>;
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u-boot,dm-spl;
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|
};
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};
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};
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|
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&main_pmx1 {
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&main_pmx1 {
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|
@ -250,3 +256,24 @@
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&chipid {
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&chipid {
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u-boot,dm-spl;
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u-boot,dm-spl;
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||||||
};
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};
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|
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&dwc3_0 {
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status = "okay";
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u-boot,dm-spl;
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|
};
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|
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|
&usb0_phy {
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status = "okay";
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u-boot,dm-spl;
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};
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|
&usb0 {
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|
pinctrl-names = "default";
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pinctrl-0 = <&usb0_pins_default>;
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|
dr_mode = "peripheral";
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|
u-boot,dm-spl;
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|
};
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|
|
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|
&scm_conf {
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|
u-boot,dm-spl;
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|
};
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|
@ -278,3 +278,38 @@
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#size-cells = <1>;
|
#size-cells = <1>;
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||||||
};
|
};
|
||||||
};
|
};
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||||||
|
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||||||
|
&main_pmx0 {
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|
u-boot,dm-spl;
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usb0_pins_default: usb0_pins_default {
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pinctrl-single,pins = <
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||||||
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AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
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||||||
|
>;
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u-boot,dm-spl;
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};
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};
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&dwc3_0 {
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status = "okay";
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u-boot,dm-spl;
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||||||
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/delete-property/ power-domains;
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-parents;
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||||||
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};
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|
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&usb0_phy {
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status = "okay";
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u-boot,dm-spl;
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/delete-property/ clocks;
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||||||
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};
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||||||
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&usb0 {
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pinctrl-names = "default";
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||||||
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pinctrl-0 = <&usb0_pins_default>;
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||||||
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dr_mode = "peripheral";
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u-boot,dm-spl;
|
||||||
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};
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||||||
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&scm_conf {
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u-boot,dm-spl;
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||||||
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};
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|
||||||
133
arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
Normal file
133
arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
Normal file
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|
@ -0,0 +1,133 @@
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||||||
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
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||||||
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*/
|
||||||
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||||||
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/ {
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chosen {
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||||||
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stdout-path = "serial2:115200n8";
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||||||
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tick-timer = &timer1;
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};
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||||||
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aliases {
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ethernet0 = &cpsw_port1;
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||||||
|
};
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||||||
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};
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||||||
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|
||||||
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&chipid {
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||||||
|
u-boot,dm-spl;
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||||||
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};
|
||||||
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|
||||||
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&cbass_main {
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||||||
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u-boot,dm-spl;
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||||||
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};
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||||||
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||||||
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&main_navss {
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||||||
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u-boot,dm-spl;
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||||||
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};
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||||||
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&cbass_mcu_wakeup {
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||||||
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u-boot,dm-spl;
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|
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timer1: timer@40400000 {
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||||||
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compatible = "ti,omap5430-timer";
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reg = <0x0 0x40400000 0x0 0x80>;
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||||||
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ti,timer-alwon;
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||||||
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clock-frequency = <25000000>;
|
||||||
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u-boot,dm-spl;
|
||||||
|
};
|
||||||
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};
|
||||||
|
|
||||||
|
&secure_proxy_main {
|
||||||
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u-boot,dm-spl;
|
||||||
|
};
|
||||||
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||||||
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&dmsc {
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||||||
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u-boot,dm-spl;
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||||||
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k3_sysreset: sysreset-controller {
|
||||||
|
compatible = "ti,sci-sysreset";
|
||||||
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u-boot,dm-spl;
|
||||||
|
};
|
||||||
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};
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||||||
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|
||||||
|
&k3_pds {
|
||||||
|
u-boot,dm-spl;
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||||||
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};
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||||||
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||||||
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&k3_clks {
|
||||||
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u-boot,dm-spl;
|
||||||
|
};
|
||||||
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|
||||||
|
&k3_reset {
|
||||||
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u-boot,dm-spl;
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||||||
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};
|
||||||
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|
||||||
|
&wkup_pmx0 {
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||||||
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u-boot,dm-spl;
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||||||
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};
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||||||
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||||||
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&main_pmx0 {
|
||||||
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u-boot,dm-spl;
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};
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||||||
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||||||
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&main_uart0 {
|
||||||
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u-boot,dm-spl;
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||||||
|
};
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||||||
|
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||||||
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&mcu_uart0 {
|
||||||
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u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_sdhci0 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_sdhci1 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&wkup_i2c0_pins_default {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&wkup_i2c0 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_i2c0 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_i2c0_pins_default {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&exp2 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&mcu_cpsw {
|
||||||
|
reg = <0x0 0x46000000 0x0 0x200000>,
|
||||||
|
<0x0 0x40f00200 0x0 0x8>;
|
||||||
|
reg-names = "cpsw_nuss", "mac_efuse";
|
||||||
|
|
||||||
|
cpsw-phy-sel@40f04040 {
|
||||||
|
compatible = "ti,am654-cpsw-phy-sel";
|
||||||
|
reg= <0x0 0x40f04040 0x0 0x4>;
|
||||||
|
reg-names = "gmii-sel";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_usbss0_pins_default {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
&usbss0 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
ti,usb2-only;
|
||||||
|
};
|
||||||
|
|
||||||
|
&usb0 {
|
||||||
|
dr_mode = "peripheral";
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
195
arch/arm/dts/k3-j7200-common-proc-board.dts
Normal file
195
arch/arm/dts/k3-j7200-common-proc-board.dts
Normal file
|
|
@ -0,0 +1,195 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include <dt-bindings/net/ti-dp83867.h>
|
||||||
|
#include "k3-j7200-som-p0.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
chosen {
|
||||||
|
stdout-path = "serial2:115200n8";
|
||||||
|
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&wkup_pmx0 {
|
||||||
|
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
|
||||||
|
pinctrl-single,pins = <
|
||||||
|
J721E_WKUP_IOPAD(0x100, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
|
||||||
|
J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
|
||||||
|
wkup_gpio_pins_default: wkup-gpio-pins-default {
|
||||||
|
pinctrl-single,pins = <
|
||||||
|
J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mcu_cpsw_pins_default: mcu_cpsw_pins_default {
|
||||||
|
pinctrl-single,pins = <
|
||||||
|
J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
|
||||||
|
J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
|
||||||
|
J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
|
||||||
|
J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
|
||||||
|
J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
|
||||||
|
J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
|
||||||
|
J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
|
||||||
|
J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
|
||||||
|
J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
|
||||||
|
J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
|
||||||
|
J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
|
||||||
|
J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mcu_mdio_pins_default: mcu_mdio1_pins_default {
|
||||||
|
pinctrl-single,pins = <
|
||||||
|
J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
|
||||||
|
J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_pmx0 {
|
||||||
|
main_i2c0_pins_default: main-i2c0-pins-default {
|
||||||
|
pinctrl-single,pins = <
|
||||||
|
J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
|
||||||
|
J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_usbss0_pins_default: main_usbss0_pins_default {
|
||||||
|
pinctrl-single,pins = <
|
||||||
|
J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&wkup_uart0 {
|
||||||
|
/* Wakeup UART is used by System firmware */
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_uart0 {
|
||||||
|
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_uart2 {
|
||||||
|
/* MAIN UART 2 is used by R5F firmware */
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_uart3 {
|
||||||
|
/* UART not brought out */
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_uart4 {
|
||||||
|
/* UART not brought out */
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_uart5 {
|
||||||
|
/* UART not brought out */
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_uart6 {
|
||||||
|
/* UART not brought out */
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_uart7 {
|
||||||
|
/* UART not brought out */
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_uart8 {
|
||||||
|
/* UART not brought out */
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_uart9 {
|
||||||
|
/* UART not brought out */
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
&wkup_i2c0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&wkup_i2c0_pins_default>;
|
||||||
|
clock-frequency = <400000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_sdhci0 {
|
||||||
|
/* eMMC */
|
||||||
|
non-removable;
|
||||||
|
ti,driver-strength-ohm = <50>;
|
||||||
|
disable-wp;
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_sdhci1 {
|
||||||
|
/* SD card */
|
||||||
|
ti,driver-strength-ohm = <50>;
|
||||||
|
disable-wp;
|
||||||
|
no-1-8-v;
|
||||||
|
sdhci-caps-mask = <0x8000000F 0x0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_i2c0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||||
|
clock-frequency = <400000>;
|
||||||
|
|
||||||
|
exp1: gpio@20 {
|
||||||
|
compatible = "ti,tca6416";
|
||||||
|
reg = <0x20>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
exp2: gpio@22 {
|
||||||
|
compatible = "ti,tca6424";
|
||||||
|
reg = <0x22>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&usbss0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&main_usbss0_pins_default>;
|
||||||
|
ti,vbus-divider;
|
||||||
|
ti,usb2-only;
|
||||||
|
};
|
||||||
|
|
||||||
|
&usb0 {
|
||||||
|
dr_mode = "otg";
|
||||||
|
maximum-speed = "high-speed";
|
||||||
|
};
|
||||||
|
|
||||||
|
&wkup_gpio0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&wkup_gpio_pins_default>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&mcu_cpsw {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&davinci_mdio {
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
reg = <0>;
|
||||||
|
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||||
|
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpsw_port1 {
|
||||||
|
phy-mode = "rgmii-rxid";
|
||||||
|
phy-handle = <&phy0>;
|
||||||
|
};
|
||||||
2195
arch/arm/dts/k3-j7200-ddr-evm-lp4-1600.dtsi
Normal file
2195
arch/arm/dts/k3-j7200-ddr-evm-lp4-1600.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
343
arch/arm/dts/k3-j7200-main.dtsi
Normal file
343
arch/arm/dts/k3-j7200-main.dtsi
Normal file
|
|
@ -0,0 +1,343 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0
|
||||||
|
/*
|
||||||
|
* Device Tree Source for J7200 SoC Family Main Domain peripherals
|
||||||
|
*
|
||||||
|
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
*/
|
||||||
|
|
||||||
|
&cbass_main {
|
||||||
|
msmc_ram: sram@70000000 {
|
||||||
|
compatible = "mmio-sram";
|
||||||
|
reg = <0x0 0x70000000 0x0 0x100000>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0x0 0x0 0x70000000 0x100000>;
|
||||||
|
|
||||||
|
atf-sram@0 {
|
||||||
|
reg = <0x0 0x20000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
gic500: interrupt-controller@1800000 {
|
||||||
|
compatible = "arm,gic-v3";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges;
|
||||||
|
#interrupt-cells = <3>;
|
||||||
|
interrupt-controller;
|
||||||
|
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
|
||||||
|
<0x00 0x01900000 0x00 0x100000>; /* GICR */
|
||||||
|
|
||||||
|
/* vcpumntirq: virtual CPU interface maintenance interrupt */
|
||||||
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
|
||||||
|
gic_its: msi-controller@1820000 {
|
||||||
|
compatible = "arm,gic-v3-its";
|
||||||
|
reg = <0x00 0x01820000 0x00 0x10000>;
|
||||||
|
socionext,synquacer-pre-its = <0x1000000 0x400000>;
|
||||||
|
msi-controller;
|
||||||
|
#msi-cells = <1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
main_navss: navss@30000000 {
|
||||||
|
compatible = "simple-mfd";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
|
||||||
|
|
||||||
|
secure_proxy_main: mailbox@32c00000 {
|
||||||
|
compatible = "ti,am654-secure-proxy";
|
||||||
|
#mbox-cells = <1>;
|
||||||
|
reg-names = "target_data", "rt", "scfg";
|
||||||
|
reg = <0x00 0x32c00000 0x00 0x100000>,
|
||||||
|
<0x00 0x32400000 0x00 0x100000>,
|
||||||
|
<0x00 0x32800000 0x00 0x100000>;
|
||||||
|
interrupt-names = "rx_011";
|
||||||
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
main_pmx0: pinmux@11c000 {
|
||||||
|
compatible = "pinctrl-single";
|
||||||
|
/* Proxy 0 addressing */
|
||||||
|
reg = <0x0 0x11c000 0x0 0x2b4>;
|
||||||
|
#pinctrl-cells = <1>;
|
||||||
|
pinctrl-single,register-width = <32>;
|
||||||
|
pinctrl-single,function-mask = <0xffffffff>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_uart0: serial@2800000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x02800000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 146 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
main_uart1: serial@2810000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x02810000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 278 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
main_uart2: serial@2820000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x02820000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 279 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
main_uart3: serial@2830000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x02830000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 280 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
main_uart4: serial@2840000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x02840000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 281 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
main_uart5: serial@2850000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x02850000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 282 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
main_uart6: serial@2860000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x02860000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 283 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
main_uart7: serial@2870000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x02870000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 284 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
main_uart8: serial@2880000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x02880000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 285 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
main_uart9: serial@2890000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x02890000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 286 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
main_sdhci0: sdhci@4f80000 {
|
||||||
|
compatible = "ti,j721e-sdhci-8bit";
|
||||||
|
reg = <0x0 0x04f80000 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>;
|
||||||
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clock-names = "clk_xin", "clk_ahb";
|
||||||
|
clocks = <&k3_clks 91 3>, <&k3_clks 91 0>;
|
||||||
|
ti,otap-del-sel-legacy = <0x0>;
|
||||||
|
ti,otap-del-sel-mmc-hs = <0x0>;
|
||||||
|
ti,otap-del-sel-ddr52 = <0x6>;
|
||||||
|
ti,otap-del-sel-hs200 = <0x8>;
|
||||||
|
ti,otap-del-sel-hs400 = <0x0>;
|
||||||
|
ti,strobe-sel = <0x77>;
|
||||||
|
ti,trm-icp = <0x8>;
|
||||||
|
bus-width = <8>;
|
||||||
|
mmc-hs200-1_8v;
|
||||||
|
mmc-ddr-1_8v;
|
||||||
|
dma-coherent;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_sdhci1: sdhci@4fb0000 {
|
||||||
|
compatible = "ti,j721e-sdhci-4bit";
|
||||||
|
reg = <0x0 0x04fb0000 0x0 0x260>, <0x0 0x4fb8000 0x0 0x134>;
|
||||||
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clock-names = "clk_xin", "clk_ahb";
|
||||||
|
clocks = <&k3_clks 92 2>, <&k3_clks 92 1>;
|
||||||
|
ti,otap-del-sel-legacy = <0x0>;
|
||||||
|
ti,otap-del-sel-sd-hs = <0x0>;
|
||||||
|
ti,otap-del-sel-sdr12 = <0xf>;
|
||||||
|
ti,otap-del-sel-sdr25 = <0xf>;
|
||||||
|
ti,otap-del-sel-sdr50 = <0xc>;
|
||||||
|
ti,otap-del-sel-sdr104 = <0x5>;
|
||||||
|
ti,otap-del-sel-ddr50 = <0xc>;
|
||||||
|
dma-coherent;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_i2c0: i2c@2000000 {
|
||||||
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||||
|
reg = <0x0 0x2000000 0x0 0x100>;
|
||||||
|
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clock-names = "fck";
|
||||||
|
clocks = <&k3_clks 187 1>;
|
||||||
|
power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_i2c1: i2c@2010000 {
|
||||||
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||||
|
reg = <0x0 0x2010000 0x0 0x100>;
|
||||||
|
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clock-names = "fck";
|
||||||
|
clocks = <&k3_clks 188 1>;
|
||||||
|
power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_i2c2: i2c@2020000 {
|
||||||
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||||
|
reg = <0x0 0x2020000 0x0 0x100>;
|
||||||
|
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clock-names = "fck";
|
||||||
|
clocks = <&k3_clks 189 1>;
|
||||||
|
power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_i2c3: i2c@2030000 {
|
||||||
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||||
|
reg = <0x0 0x2030000 0x0 0x100>;
|
||||||
|
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clock-names = "fck";
|
||||||
|
clocks = <&k3_clks 190 1>;
|
||||||
|
power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_i2c4: i2c@2040000 {
|
||||||
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||||
|
reg = <0x0 0x2040000 0x0 0x100>;
|
||||||
|
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clock-names = "fck";
|
||||||
|
clocks = <&k3_clks 191 1>;
|
||||||
|
power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_i2c5: i2c@2050000 {
|
||||||
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||||
|
reg = <0x0 0x2050000 0x0 0x100>;
|
||||||
|
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clock-names = "fck";
|
||||||
|
clocks = <&k3_clks 192 1>;
|
||||||
|
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_i2c6: i2c@2060000 {
|
||||||
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||||
|
reg = <0x0 0x2060000 0x0 0x100>;
|
||||||
|
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clock-names = "fck";
|
||||||
|
clocks = <&k3_clks 193 1>;
|
||||||
|
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
};
|
||||||
|
|
||||||
|
usbss0: cdns_usb@4104000 {
|
||||||
|
compatible = "ti,j721e-usb";
|
||||||
|
reg = <0x00 0x4104000 0x00 0x100>;
|
||||||
|
dma-coherent;
|
||||||
|
power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
|
||||||
|
clock-names = "usb2_refclk", "lpm_clk";
|
||||||
|
assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
|
||||||
|
assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
usb0: usb@6000000 {
|
||||||
|
compatible = "cdns,usb3";
|
||||||
|
reg = <0x00 0x6000000 0x00 0x10000>,
|
||||||
|
<0x00 0x6010000 0x00 0x10000>,
|
||||||
|
<0x00 0x6020000 0x00 0x10000>;
|
||||||
|
reg-names = "otg", "xhci", "dev";
|
||||||
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
|
||||||
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
|
||||||
|
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
|
||||||
|
interrupt-names = "host",
|
||||||
|
"peripheral",
|
||||||
|
"otg";
|
||||||
|
maximum-speed = "super-speed";
|
||||||
|
dr_mode = "otg";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
272
arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
Normal file
272
arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
Normal file
|
|
@ -0,0 +1,272 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0
|
||||||
|
/*
|
||||||
|
* Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
|
||||||
|
*
|
||||||
|
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
*/
|
||||||
|
|
||||||
|
&cbass_mcu_wakeup {
|
||||||
|
dmsc: dmsc@44083000 {
|
||||||
|
compatible = "ti,k2g-sci";
|
||||||
|
ti,host-id = <12>;
|
||||||
|
|
||||||
|
mbox-names = "rx", "tx";
|
||||||
|
|
||||||
|
mboxes= <&secure_proxy_main 11>,
|
||||||
|
<&secure_proxy_main 13>;
|
||||||
|
|
||||||
|
reg-names = "debug_messages";
|
||||||
|
reg = <0x00 0x44083000 0x0 0x1000>;
|
||||||
|
|
||||||
|
k3_pds: power-controller {
|
||||||
|
compatible = "ti,sci-pm-domain";
|
||||||
|
#power-domain-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
k3_clks: clocks {
|
||||||
|
compatible = "ti,k2g-sci-clk";
|
||||||
|
#clock-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
k3_reset: reset-controller {
|
||||||
|
compatible = "ti,sci-reset";
|
||||||
|
#reset-cells = <2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
chipid: chipid@43000014 {
|
||||||
|
compatible = "ti,am654-chipid";
|
||||||
|
reg = <0x0 0x43000014 0x0 0x4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
wkup_pmx0: pinmux@4301c000 {
|
||||||
|
compatible = "pinctrl-single";
|
||||||
|
/* Proxy 0 addressing */
|
||||||
|
reg = <0x00 0x4301c000 0x00 0x178>;
|
||||||
|
#pinctrl-cells = <1>;
|
||||||
|
pinctrl-single,register-width = <32>;
|
||||||
|
pinctrl-single,function-mask = <0xffffffff>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mcu_ram: sram@41c00000 {
|
||||||
|
compatible = "mmio-sram";
|
||||||
|
reg = <0x00 0x41c00000 0x00 0x100000>;
|
||||||
|
ranges = <0x0 0x00 0x41c00000 0x100000>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
wkup_uart0: serial@42300000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x42300000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <48000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 287 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
wkup_i2c0: i2c@42120000 {
|
||||||
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||||
|
reg = <0x0 0x42120000 0x0 0x100>;
|
||||||
|
interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clock-names = "fck";
|
||||||
|
clocks = <&k3_clks 197 1>;
|
||||||
|
power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mcu_uart0: serial@40a00000 {
|
||||||
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||||
|
reg = <0x00 0x40a00000 0x00 0x100>;
|
||||||
|
reg-shift = <2>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-frequency = <96000000>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 149 2>;
|
||||||
|
clock-names = "fclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
fss: system-controller@47000000 {
|
||||||
|
compatible = "syscon", "simple-mfd";
|
||||||
|
reg = <0x0 0x47000000 0x0 0x100>;
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
hbmc_mux: hbmc-mux {
|
||||||
|
compatible = "mmio-mux";
|
||||||
|
#mux-control-cells = <1>;
|
||||||
|
mux-reg-masks = <0x4 0x2>; /* HBMC select */
|
||||||
|
};
|
||||||
|
|
||||||
|
hbmc: hyperbus@47034000 {
|
||||||
|
compatible = "ti,am654-hbmc";
|
||||||
|
reg = <0x0 0x47034000 0x0 0x100>,
|
||||||
|
<0x5 0x00000000 0x1 0x0000000>;
|
||||||
|
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
mux-controls = <&hbmc_mux 0>;
|
||||||
|
clocks = <&k3_clks 102 5>;
|
||||||
|
assigned-clocks = <&k3_clks 102 5>;
|
||||||
|
assigned-clock-rates = <333333333>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
mcu_i2c0: i2c@40b00000 {
|
||||||
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||||
|
reg = <0x0 0x40b00000 0x0 0x100>;
|
||||||
|
interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clock-names = "fck";
|
||||||
|
clocks = <&k3_clks 194 1>;
|
||||||
|
power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mcu_i2c1: i2c@40b10000 {
|
||||||
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||||
|
reg = <0x0 0x40b10000 0x0 0x100>;
|
||||||
|
interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clock-names = "fck";
|
||||||
|
clocks = <&k3_clks 195 1>;
|
||||||
|
power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cbass_mcu_navss: mcu-navss {
|
||||||
|
compatible = "simple-mfd";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges;
|
||||||
|
dma-coherent;
|
||||||
|
dma-ranges;
|
||||||
|
|
||||||
|
ti,sci-dev-id = <232>;
|
||||||
|
|
||||||
|
mcu_ringacc: ringacc@2b800000 {
|
||||||
|
compatible = "ti,am654-navss-ringacc";
|
||||||
|
reg = <0x0 0x2b800000 0x0 0x400000>,
|
||||||
|
<0x0 0x2b000000 0x0 0x400000>,
|
||||||
|
<0x0 0x28590000 0x0 0x100>,
|
||||||
|
<0x0 0x2a500000 0x0 0x40000>;
|
||||||
|
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
|
||||||
|
ti,num-rings = <286>;
|
||||||
|
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
|
||||||
|
ti,sci = <&dmsc>;
|
||||||
|
ti,sci-dev-id = <235>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mcu_udmap: dma-controller@285c0000 {
|
||||||
|
compatible = "ti,j721e-navss-mcu-udmap";
|
||||||
|
reg = <0x0 0x285c0000 0x0 0x100>,
|
||||||
|
<0x0 0x2a800000 0x0 0x40000>,
|
||||||
|
<0x0 0x2aa00000 0x0 0x40000>;
|
||||||
|
reg-names = "gcfg", "rchanrt", "tchanrt";
|
||||||
|
#dma-cells = <1>;
|
||||||
|
|
||||||
|
ti,sci = <&dmsc>;
|
||||||
|
ti,sci-dev-id = <236>;
|
||||||
|
ti,ringacc = <&mcu_ringacc>;
|
||||||
|
|
||||||
|
ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
|
||||||
|
<0x0f>; /* TX_HCHAN */
|
||||||
|
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
|
||||||
|
<0x0b>; /* RX_HCHAN */
|
||||||
|
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
wkup_gpio0: gpio@42110000 {
|
||||||
|
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||||
|
reg = <0x0 0x42110000 0x0 0x100>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
ti,ngpio = <84>;
|
||||||
|
ti,davinci-gpio-unbanked = <0>;
|
||||||
|
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
clocks = <&k3_clks 113 0>;
|
||||||
|
clock-names = "gpio";
|
||||||
|
};
|
||||||
|
|
||||||
|
mcu_conf: scm_conf@40f00000 {
|
||||||
|
compatible = "syscon", "simple-mfd";
|
||||||
|
reg = <0x0 0x40f00000 0x0 0x20000>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0x0 0x0 0x40f00000 0x20000>;
|
||||||
|
|
||||||
|
phy_gmii_sel: phy@4040 {
|
||||||
|
compatible = "ti,am654-cpsw-phy-sel";
|
||||||
|
reg = <0x4040 0x4>;
|
||||||
|
reg-names = "gmii-sel";
|
||||||
|
#phy-cells = <1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
mcu_cpsw: ethernet@46000000 {
|
||||||
|
compatible = "ti,j721e-cpsw-nuss";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
reg = <0x0 0x46000000 0x0 0x200000>;
|
||||||
|
reg-names = "cpsw_nuss";
|
||||||
|
ranges;
|
||||||
|
dma-coherent;
|
||||||
|
clocks = <&k3_clks 18 21>;
|
||||||
|
clock-names = "fck";
|
||||||
|
power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
|
||||||
|
dmas = <&mcu_udmap 0xf000>,
|
||||||
|
<&mcu_udmap 0xf001>,
|
||||||
|
<&mcu_udmap 0xf002>,
|
||||||
|
<&mcu_udmap 0xf003>,
|
||||||
|
<&mcu_udmap 0xf004>,
|
||||||
|
<&mcu_udmap 0xf005>,
|
||||||
|
<&mcu_udmap 0xf006>,
|
||||||
|
<&mcu_udmap 0xf007>,
|
||||||
|
<&mcu_udmap 0x7000>;
|
||||||
|
dma-names = "tx0", "tx1", "tx2", "tx3",
|
||||||
|
"tx4", "tx5", "tx6", "tx7",
|
||||||
|
"rx";
|
||||||
|
|
||||||
|
ethernet-ports {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
cpsw_port1: port@1 {
|
||||||
|
reg = <1>;
|
||||||
|
ti,mac-only;
|
||||||
|
ti,label = "port1";
|
||||||
|
ti,syscon-efuse = <&mcu_conf 0x200>;
|
||||||
|
phys = <&phy_gmii_sel 1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
davinci_mdio: mdio@f00 {
|
||||||
|
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
|
||||||
|
reg = <0x0 0xf00 0x0 0x100>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
clocks = <&k3_clks 18 21>;
|
||||||
|
clock-names = "fck";
|
||||||
|
bus_freq = <1000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpts {
|
||||||
|
clocks = <&k3_clks 18 2>;
|
||||||
|
clock-names = "cpts";
|
||||||
|
interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-names = "cpts";
|
||||||
|
ti,cpts-ext-ts-inputs = <4>;
|
||||||
|
ti,cpts-periodic-outputs = <2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
217
arch/arm/dts/k3-j7200-r5-common-proc-board.dts
Normal file
217
arch/arm/dts/k3-j7200-r5-common-proc-board.dts
Normal file
|
|
@ -0,0 +1,217 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include "k3-j7200-som-p0.dtsi"
|
||||||
|
#include "k3-j7200-ddr-evm-lp4-1600.dtsi"
|
||||||
|
#include "k3-j721e-ddr.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
aliases {
|
||||||
|
remoteproc0 = &sysctrler;
|
||||||
|
remoteproc1 = &a72_0;
|
||||||
|
};
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
stdout-path = &main_uart0;
|
||||||
|
tick-timer = &timer1;
|
||||||
|
};
|
||||||
|
|
||||||
|
a72_0: a72@0 {
|
||||||
|
compatible = "ti,am654-rproc";
|
||||||
|
reg = <0x0 0x00a90000 0x0 0x10>;
|
||||||
|
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
|
||||||
|
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
resets = <&k3_reset 202 0>;
|
||||||
|
assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
|
||||||
|
assigned-clock-rates = <2000000000>, <200000000>;
|
||||||
|
ti,sci = <&dmsc>;
|
||||||
|
ti,sci-proc-id = <32>;
|
||||||
|
ti,sci-host-id = <10>;
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
clk_200mhz: dummy_clock_200mhz {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
|
clock-frequency = <200000000>;
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
|
||||||
|
clk_19_2mhz: dummy_clock_19_2mhz {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
|
clock-frequency = <19200000>;
|
||||||
|
u-boot,dm-spl;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&memorycontroller {
|
||||||
|
power-domains = <&k3_pds 8 TI_SCI_PD_SHARED>,
|
||||||
|
<&k3_pds 90 TI_SCI_PD_SHARED>;
|
||||||
|
clocks = <&k3_clks 8 5>, <&k3_clks 30 9>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cbass_mcu_wakeup {
|
||||||
|
mcu_secproxy: secproxy@2a380000 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
compatible = "ti,am654-secure-proxy";
|
||||||
|
reg = <0x0 0x2a380000 0x0 0x80000>,
|
||||||
|
<0x0 0x2a400000 0x0 0x80000>,
|
||||||
|
<0x0 0x2a480000 0x0 0x80000>;
|
||||||
|
reg-names = "rt", "scfg", "target_data";
|
||||||
|
#mbox-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
sysctrler: sysctrler {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
compatible = "ti,am654-system-controller";
|
||||||
|
mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
|
||||||
|
mbox-names = "tx", "rx";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&dmsc {
|
||||||
|
mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
|
||||||
|
mbox-names = "tx", "rx", "notify";
|
||||||
|
ti,host-id = <4>;
|
||||||
|
ti,secure-host;
|
||||||
|
};
|
||||||
|
|
||||||
|
&wkup_pmx0 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
wkup_uart0_pins_default: wkup_uart0_pins_default {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
pinctrl-single,pins = <
|
||||||
|
J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */
|
||||||
|
J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
|
||||||
|
mcu_uart0_pins_default: mcu_uart0_pins_default {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
pinctrl-single,pins = <
|
||||||
|
J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) WKUP_GPIO0_13.MCU_UART0_RXD */
|
||||||
|
J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) WKUP_GPIO0_12.MCU_UART0_TXD */
|
||||||
|
J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) WKUP_GPIO0_14.MCU_UART0_CTSn */
|
||||||
|
J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) WKUP_GPIO0_15.MCU_UART0_RTSn */
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
|
||||||
|
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
|
||||||
|
pinctrl-single,pins = <
|
||||||
|
J721E_WKUP_IOPAD(0x100, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
|
||||||
|
J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_pmx0 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
|
||||||
|
main_uart0_pins_default: main_uart0_pins_default {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
pinctrl-single,pins = <
|
||||||
|
J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */
|
||||||
|
J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
|
||||||
|
J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */
|
||||||
|
J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_i2c0_pins_default: main-i2c0-pins-default {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
pinctrl-single,pins = <
|
||||||
|
J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
|
||||||
|
J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
|
||||||
|
main_usbss0_pins_default: main_usbss0_pins_default {
|
||||||
|
pinctrl-single,pins = <
|
||||||
|
J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&wkup_uart0 {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&wkup_uart0_pins_default>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&mcu_uart0 {
|
||||||
|
/delete-property/ power-domains;
|
||||||
|
/delete-property/ clocks;
|
||||||
|
/delete-property/ clock-names;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&mcu_uart0_pins_default>;
|
||||||
|
status = "okay";
|
||||||
|
clock-frequency = <96000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_uart0 {
|
||||||
|
status = "okay";
|
||||||
|
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&main_uart0_pins_default>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_sdhci0 {
|
||||||
|
/delete-property/ power-domains;
|
||||||
|
/delete-property/ assigned-clocks;
|
||||||
|
/delete-property/ assigned-clock-parents;
|
||||||
|
clock-names = "clk_xin";
|
||||||
|
clocks = <&clk_200mhz>;
|
||||||
|
ti,driver-strength-ohm = <50>;
|
||||||
|
non-removable;
|
||||||
|
bus-width = <8>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_sdhci1 {
|
||||||
|
/delete-property/ power-domains;
|
||||||
|
/delete-property/ assigned-clocks;
|
||||||
|
/delete-property/ assigned-clock-parents;
|
||||||
|
clock-names = "clk_xin";
|
||||||
|
clocks = <&clk_200mhz>;
|
||||||
|
ti,driver-strength-ohm = <50>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&main_i2c0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||||
|
clock-frequency = <400000>;
|
||||||
|
|
||||||
|
exp1: gpio@20 {
|
||||||
|
compatible = "ti,tca6416";
|
||||||
|
reg = <0x20>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
exp2: gpio@22 {
|
||||||
|
compatible = "ti,tca6424";
|
||||||
|
reg = <0x22>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&usbss0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&main_usbss0_pins_default>;
|
||||||
|
ti,vbus-divider;
|
||||||
|
ti,usb2-only;
|
||||||
|
};
|
||||||
|
|
||||||
|
&usb0 {
|
||||||
|
dr_mode = "otg";
|
||||||
|
maximum-speed = "high-speed";
|
||||||
|
};
|
||||||
|
|
||||||
|
#include "k3-j7200-common-proc-board-u-boot.dtsi"
|
||||||
62
arch/arm/dts/k3-j7200-som-p0.dtsi
Normal file
62
arch/arm/dts/k3-j7200-som-p0.dtsi
Normal file
|
|
@ -0,0 +1,62 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include "k3-j7200.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
memory@80000000 {
|
||||||
|
device_type = "memory";
|
||||||
|
/* 4G RAM */
|
||||||
|
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
|
||||||
|
<0x00000008 0x80000000 0x00000000 0x80000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
reserved_memory: reserved-memory {
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
secure_ddr: optee@9e800000 {
|
||||||
|
reg = <0x00 0x9e800000 0x00 0x01800000>;
|
||||||
|
alignment = <0x1000>;
|
||||||
|
no-map;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&wkup_pmx0 {
|
||||||
|
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
|
||||||
|
pinctrl-single,pins = <
|
||||||
|
J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
|
||||||
|
J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
|
||||||
|
J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
|
||||||
|
J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
|
||||||
|
J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
|
||||||
|
J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
|
||||||
|
J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
|
||||||
|
J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
|
||||||
|
J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
|
||||||
|
J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
|
||||||
|
J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
|
||||||
|
J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
|
||||||
|
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&hbmc {
|
||||||
|
status = "disabled";
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
|
||||||
|
ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */
|
||||||
|
<0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */
|
||||||
|
|
||||||
|
flash@0,0 {
|
||||||
|
compatible = "cypress,hyperflash", "cfi-flash";
|
||||||
|
reg = <0x0 0x0 0x4000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
177
arch/arm/dts/k3-j7200.dtsi
Normal file
177
arch/arm/dts/k3-j7200.dtsi
Normal file
|
|
@ -0,0 +1,177 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0
|
||||||
|
/*
|
||||||
|
* Device Tree Source for J7200 SoC Family
|
||||||
|
*
|
||||||
|
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <dt-bindings/interrupt-controller/irq.h>
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/pinctrl/k3.h>
|
||||||
|
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Texas Instruments K3 J7200 SoC";
|
||||||
|
compatible = "ti,j7200";
|
||||||
|
interrupt-parent = <&gic500>;
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
serial0 = &wkup_uart0;
|
||||||
|
serial1 = &mcu_uart0;
|
||||||
|
serial2 = &main_uart0;
|
||||||
|
serial3 = &main_uart1;
|
||||||
|
serial4 = &main_uart2;
|
||||||
|
serial5 = &main_uart3;
|
||||||
|
serial6 = &main_uart4;
|
||||||
|
serial7 = &main_uart5;
|
||||||
|
serial8 = &main_uart6;
|
||||||
|
serial9 = &main_uart7;
|
||||||
|
serial10 = &main_uart8;
|
||||||
|
serial11 = &main_uart9;
|
||||||
|
i2c0 = &wkup_i2c0;
|
||||||
|
i2c1 = &mcu_i2c0;
|
||||||
|
i2c2 = &mcu_i2c1;
|
||||||
|
i2c3 = &main_i2c0;
|
||||||
|
i2c4 = &main_i2c1;
|
||||||
|
i2c5 = &main_i2c2;
|
||||||
|
i2c6 = &main_i2c3;
|
||||||
|
i2c7 = &main_i2c4;
|
||||||
|
i2c8 = &main_i2c5;
|
||||||
|
i2c9 = &main_i2c6;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
cpu-map {
|
||||||
|
cluster0: cluster0 {
|
||||||
|
core0 {
|
||||||
|
cpu = <&cpu0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
core1 {
|
||||||
|
cpu = <&cpu1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu0: cpu@0 {
|
||||||
|
compatible = "arm,cortex-a72";
|
||||||
|
reg = <0x000>;
|
||||||
|
device_type = "cpu";
|
||||||
|
enable-method = "psci";
|
||||||
|
i-cache-size = <0xC000>;
|
||||||
|
i-cache-line-size = <64>;
|
||||||
|
i-cache-sets = <256>;
|
||||||
|
d-cache-size = <0x8000>;
|
||||||
|
d-cache-line-size = <64>;
|
||||||
|
d-cache-sets = <128>;
|
||||||
|
next-level-cache = <&L2_0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu1: cpu@1 {
|
||||||
|
compatible = "arm,cortex-a72";
|
||||||
|
reg = <0x001>;
|
||||||
|
device_type = "cpu";
|
||||||
|
enable-method = "psci";
|
||||||
|
i-cache-size = <0xC000>;
|
||||||
|
i-cache-line-size = <64>;
|
||||||
|
i-cache-sets = <256>;
|
||||||
|
d-cache-size = <0x8000>;
|
||||||
|
d-cache-line-size = <64>;
|
||||||
|
d-cache-sets = <128>;
|
||||||
|
next-level-cache = <&L2_0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
L2_0: l2-cache0 {
|
||||||
|
compatible = "cache";
|
||||||
|
cache-level = <2>;
|
||||||
|
cache-size = <0x100000>;
|
||||||
|
cache-line-size = <64>;
|
||||||
|
cache-sets = <2048>;
|
||||||
|
next-level-cache = <&msmc_l3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
msmc_l3: l3-cache0 {
|
||||||
|
compatible = "cache";
|
||||||
|
cache-level = <3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
firmware {
|
||||||
|
optee {
|
||||||
|
compatible = "linaro,optee-tz";
|
||||||
|
method = "smc";
|
||||||
|
};
|
||||||
|
|
||||||
|
psci: psci {
|
||||||
|
compatible = "arm,psci-1.0";
|
||||||
|
method = "smc";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
a72_timer0: timer-cl0-cpu0 {
|
||||||
|
compatible = "arm,armv8-timer";
|
||||||
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
|
||||||
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
|
||||||
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
|
||||||
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
|
||||||
|
};
|
||||||
|
|
||||||
|
pmu: pmu {
|
||||||
|
compatible = "arm,armv8-pmuv3";
|
||||||
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cbass_main: bus@100000 {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
|
||||||
|
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
|
||||||
|
<0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */
|
||||||
|
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
|
||||||
|
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
|
||||||
|
<0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
|
||||||
|
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT */
|
||||||
|
|
||||||
|
/* MCUSS_WKUP Range */
|
||||||
|
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
|
||||||
|
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
|
||||||
|
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
|
||||||
|
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
|
||||||
|
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
|
||||||
|
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
|
||||||
|
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
|
||||||
|
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
|
||||||
|
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
|
||||||
|
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
|
||||||
|
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
|
||||||
|
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>;
|
||||||
|
|
||||||
|
cbass_mcu_wakeup: bus@28380000 {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
|
||||||
|
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
|
||||||
|
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
|
||||||
|
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
|
||||||
|
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
|
||||||
|
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
|
||||||
|
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
|
||||||
|
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
|
||||||
|
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
|
||||||
|
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
|
||||||
|
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
|
||||||
|
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>; /* FSS OSPI0 data region 3 */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Now include the peripherals for each bus segments */
|
||||||
|
#include "k3-j7200-main.dtsi"
|
||||||
|
#include "k3-j7200-mcu-wakeup.dtsi"
|
||||||
|
|
@ -543,4 +543,22 @@
|
||||||
clocks = <&k3_clks 193 0>;
|
clocks = <&k3_clks 193 0>;
|
||||||
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
|
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
watchdog0: watchdog@2200000 {
|
||||||
|
compatible = "ti,j7-rti-wdt";
|
||||||
|
reg = <0x0 0x2200000 0x0 0x100>;
|
||||||
|
clocks = <&k3_clks 252 1>;
|
||||||
|
power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
assigned-clocks = <&k3_clks 252 1>;
|
||||||
|
assigned-clock-parents = <&k3_clks 252 5>;
|
||||||
|
};
|
||||||
|
|
||||||
|
watchdog1: watchdog@2210000 {
|
||||||
|
compatible = "ti,j7-rti-wdt";
|
||||||
|
reg = <0x0 0x2210000 0x0 0x100>;
|
||||||
|
clocks = <&k3_clks 253 1>;
|
||||||
|
power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
|
||||||
|
assigned-clocks = <&k3_clks 253 1>;
|
||||||
|
assigned-clock-parents = <&k3_clks 253 5>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -131,7 +131,7 @@
|
||||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
};
|
};
|
||||||
|
|
||||||
cbass_main: interconnect@100000 {
|
cbass_main: bus@100000 {
|
||||||
compatible = "simple-bus";
|
compatible = "simple-bus";
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
#size-cells = <2>;
|
#size-cells = <2>;
|
||||||
|
|
@ -164,7 +164,7 @@
|
||||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
|
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
|
||||||
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
|
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
|
||||||
|
|
||||||
cbass_mcu_wakeup: interconnect@28380000 {
|
cbass_mcu_wakeup: bus@28380000 {
|
||||||
compatible = "simple-bus";
|
compatible = "simple-bus";
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
#size-cells = <2>;
|
#size-cells = <2>;
|
||||||
|
|
|
||||||
|
|
@ -11,4 +11,14 @@
|
||||||
chosen {
|
chosen {
|
||||||
stdout-path = &uart1;
|
stdout-path = &uart1;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
ethernet@2c000000 {
|
||||||
|
compatible = "smsc,lan9221","smsc,lan9115";
|
||||||
|
reg = <0x2c000000 0xff>;
|
||||||
|
bank-width = <2>;
|
||||||
|
vddvario-supply = <&vddvario>;
|
||||||
|
vdd33a-supply = <&vdd33a>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
smsc,save-mac-address;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -11,4 +11,14 @@
|
||||||
chosen {
|
chosen {
|
||||||
stdout-path = &uart1;
|
stdout-path = &uart1;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
ethernet@2c000000 {
|
||||||
|
compatible = "smsc,lan9221","smsc,lan9115";
|
||||||
|
reg = <0x2c000000 0xff>;
|
||||||
|
bank-width = <2>;
|
||||||
|
vddvario-supply = <&vddvario>;
|
||||||
|
vdd33a-supply = <&vdd33a>;
|
||||||
|
reg-io-width = <4>;
|
||||||
|
smsc,save-mac-address;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -8,6 +8,7 @@ obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
|
||||||
obj-$(CONFIG_ARM64) += arm64-mmu.o
|
obj-$(CONFIG_ARM64) += arm64-mmu.o
|
||||||
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
|
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
|
||||||
obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
|
obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
|
||||||
|
obj-$(CONFIG_ARM64) += cache.o
|
||||||
ifeq ($(CONFIG_SPL_BUILD),y)
|
ifeq ($(CONFIG_SPL_BUILD),y)
|
||||||
obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
|
obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
|
||||||
endif
|
endif
|
||||||
|
|
|
||||||
|
|
@ -7,6 +7,7 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
|
#include <fdt_support.h>
|
||||||
#include <init.h>
|
#include <init.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <spl.h>
|
#include <spl.h>
|
||||||
|
|
@ -18,7 +19,11 @@
|
||||||
#include <dm/uclass-internal.h>
|
#include <dm/uclass-internal.h>
|
||||||
#include <dm/pinctrl.h>
|
#include <dm/pinctrl.h>
|
||||||
#include <linux/soc/ti/ti_sci_protocol.h>
|
#include <linux/soc/ti/ti_sci_protocol.h>
|
||||||
|
#include <log.h>
|
||||||
#include <mmc.h>
|
#include <mmc.h>
|
||||||
|
#include <stdlib.h>
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
#ifdef CONFIG_SPL_BUILD
|
#ifdef CONFIG_SPL_BUILD
|
||||||
#ifdef CONFIG_K3_LOAD_SYSFW
|
#ifdef CONFIG_K3_LOAD_SYSFW
|
||||||
|
|
@ -41,16 +46,6 @@ struct fwl_data main_cbass_fwls[] = {
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
static void mmr_unlock(u32 base, u32 partition)
|
|
||||||
{
|
|
||||||
/* Translate the base address */
|
|
||||||
phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
|
|
||||||
|
|
||||||
/* Unlock the requested partition if locked using two-step sequence */
|
|
||||||
writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
|
|
||||||
writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void ctrl_mmr_unlock(void)
|
static void ctrl_mmr_unlock(void)
|
||||||
{
|
{
|
||||||
/* Unlock all WKUP_CTRL_MMR0 module registers */
|
/* Unlock all WKUP_CTRL_MMR0 module registers */
|
||||||
|
|
@ -88,7 +83,7 @@ static void store_boot_index_from_rom(void)
|
||||||
bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
|
bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined(CONFIG_K3_LOAD_SYSFW)
|
#if defined(CONFIG_K3_LOAD_SYSFW) && CONFIG_IS_ENABLED(DM_MMC)
|
||||||
void k3_mmc_stop_clock(void)
|
void k3_mmc_stop_clock(void)
|
||||||
{
|
{
|
||||||
if (spl_boot_device() == BOOT_DEVICE_MMC1) {
|
if (spl_boot_device() == BOOT_DEVICE_MMC1) {
|
||||||
|
|
@ -113,12 +108,54 @@ void k3_mmc_restart_clock(void)
|
||||||
mmc_set_clock(mmc, mmc->saved_clock, false);
|
mmc_set_clock(mmc, mmc->saved_clock, false);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
#else
|
||||||
|
void k3_mmc_stop_clock(void) {}
|
||||||
|
void k3_mmc_restart_clock(void) {}
|
||||||
#endif
|
#endif
|
||||||
|
#if CONFIG_IS_ENABLED(DFU) || CONFIG_IS_ENABLED(USB_STORAGE)
|
||||||
|
#define CTRLMMR_SERDES0_CTRL 0x00104080
|
||||||
|
#define PCIE_LANE0 0x1
|
||||||
|
static int fixup_usb_boot(void)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
switch (spl_boot_device()) {
|
||||||
|
case BOOT_DEVICE_USB:
|
||||||
|
/*
|
||||||
|
* If bootmode is Host bootmode, fixup the dr_mode to host
|
||||||
|
* before the dwc3 bind takes place
|
||||||
|
*/
|
||||||
|
ret = fdt_find_and_setprop((void *)gd->fdt_blob,
|
||||||
|
"/interconnect@100000/dwc3@4000000/usb@10000",
|
||||||
|
"dr_mode", "host", 11, 0);
|
||||||
|
if (ret)
|
||||||
|
printf("%s: fdt_find_and_setprop() failed:%d\n", __func__,
|
||||||
|
ret);
|
||||||
|
fallthrough;
|
||||||
|
case BOOT_DEVICE_DFU:
|
||||||
|
/*
|
||||||
|
* The serdes mux between PCIe and USB3 needs to be set to PCIe for
|
||||||
|
* accessing the interface at USB 2.0
|
||||||
|
*/
|
||||||
|
writel(PCIE_LANE0, CTRLMMR_SERDES0_CTRL);
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int fdtdec_board_setup(const void *fdt_blob)
|
||||||
|
{
|
||||||
|
return fixup_usb_boot();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
void board_init_f(ulong dummy)
|
void board_init_f(ulong dummy)
|
||||||
{
|
{
|
||||||
#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
|
#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
|
||||||
struct udevice *dev;
|
struct udevice *dev;
|
||||||
|
size_t pool_size;
|
||||||
|
void *pool_addr;
|
||||||
int ret;
|
int ret;
|
||||||
#endif
|
#endif
|
||||||
/*
|
/*
|
||||||
|
|
@ -149,6 +186,20 @@ void board_init_f(ulong dummy)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_K3_LOAD_SYSFW
|
#ifdef CONFIG_K3_LOAD_SYSFW
|
||||||
|
/*
|
||||||
|
* Initialize an early full malloc environment. Do so by allocating a
|
||||||
|
* new malloc area inside the currently active pre-relocation "first"
|
||||||
|
* malloc pool of which we use all that's left.
|
||||||
|
*/
|
||||||
|
pool_size = CONFIG_VAL(SYS_MALLOC_F_LEN) - gd->malloc_ptr;
|
||||||
|
pool_addr = malloc(pool_size);
|
||||||
|
if (!pool_addr)
|
||||||
|
panic("ERROR: Can't allocate full malloc pool!\n");
|
||||||
|
|
||||||
|
mem_malloc_init((ulong)pool_addr, (ulong)pool_size);
|
||||||
|
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
|
||||||
|
debug("%s: initialized an early full malloc pool at 0x%08lx of 0x%lx bytes\n",
|
||||||
|
__func__, (unsigned long)pool_addr, (unsigned long)pool_size);
|
||||||
/*
|
/*
|
||||||
* Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
|
* Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
|
||||||
* regardless of the result of pinctrl. Do this without probing the
|
* regardless of the result of pinctrl. Do this without probing the
|
||||||
|
|
@ -165,7 +216,7 @@ void board_init_f(ulong dummy)
|
||||||
* Load, start up, and configure system controller firmware while
|
* Load, start up, and configure system controller firmware while
|
||||||
* also populating the SYSFW post-PM configuration callback hook.
|
* also populating the SYSFW post-PM configuration callback hook.
|
||||||
*/
|
*/
|
||||||
k3_sysfw_loader(k3_mmc_stop_clock, k3_mmc_restart_clock);
|
k3_sysfw_loader(false, k3_mmc_stop_clock, k3_mmc_restart_clock);
|
||||||
|
|
||||||
/* Prepare console output */
|
/* Prepare console output */
|
||||||
preloader_console_init();
|
preloader_console_init();
|
||||||
|
|
@ -272,6 +323,11 @@ static u32 __get_primary_bootmedia(u32 devstat)
|
||||||
CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
|
CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
|
||||||
if (port == 0x1)
|
if (port == 0x1)
|
||||||
bootmode = BOOT_DEVICE_MMC2;
|
bootmode = BOOT_DEVICE_MMC2;
|
||||||
|
} else if (bootmode == BOOT_DEVICE_DFU) {
|
||||||
|
u32 mode = (devstat & CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK) >>
|
||||||
|
CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT;
|
||||||
|
if (mode == 0x2)
|
||||||
|
bootmode = BOOT_DEVICE_USB;
|
||||||
}
|
}
|
||||||
|
|
||||||
return bootmode;
|
return bootmode;
|
||||||
|
|
|
||||||
24
arch/arm/mach-k3/cache.S
Normal file
24
arch/arm/mach-k3/cache.S
Normal file
|
|
@ -0,0 +1,24 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
|
||||||
|
* Andrew F. Davis <afd@ti.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <config.h>
|
||||||
|
#include <linux/linkage.h>
|
||||||
|
|
||||||
|
#if defined(CONFIG_SPL_BUILD)
|
||||||
|
ENTRY(__asm_invalidate_l3_dcache)
|
||||||
|
/* Invalidate SPL address range */
|
||||||
|
mov x0, #CONFIG_SPL_TEXT_BASE
|
||||||
|
add x1, x0, #CONFIG_SPL_MAX_SIZE
|
||||||
|
b __asm_flush_dcache_range
|
||||||
|
ENDPROC(__asm_invalidate_l3_dcache)
|
||||||
|
|
||||||
|
ENTRY(__asm_flush_l3_dcache)
|
||||||
|
/* Flush SPL address range */
|
||||||
|
mov x0, #CONFIG_SPL_TEXT_BASE
|
||||||
|
add x1, x0, #CONFIG_SPL_MAX_SIZE
|
||||||
|
b __asm_flush_dcache_range
|
||||||
|
ENDPROC(__asm_flush_l3_dcache)
|
||||||
|
#endif
|
||||||
|
|
@ -62,6 +62,24 @@ void k3_sysfw_print_ver(void)
|
||||||
ti_sci->version.firmware_revision, fw_desc);
|
ti_sci->version.firmware_revision, fw_desc);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void mmr_unlock(phys_addr_t base, u32 partition)
|
||||||
|
{
|
||||||
|
/* Translate the base address */
|
||||||
|
phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
|
||||||
|
|
||||||
|
/* Unlock the requested partition if locked using two-step sequence */
|
||||||
|
writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
|
||||||
|
writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data)
|
||||||
|
{
|
||||||
|
if (strncmp(data->header, K3_ROM_BOOT_HEADER_MAGIC, 7))
|
||||||
|
return false;
|
||||||
|
|
||||||
|
return data->num_components > 1;
|
||||||
|
}
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
#ifdef CONFIG_K3_EARLY_CONS
|
#ifdef CONFIG_K3_EARLY_CONS
|
||||||
|
|
@ -335,6 +353,26 @@ int print_cpuinfo(void)
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
bool soc_is_j721e(void)
|
||||||
|
{
|
||||||
|
u32 soc;
|
||||||
|
|
||||||
|
soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
|
||||||
|
JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
|
||||||
|
|
||||||
|
return soc == J721E;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool soc_is_j7200(void)
|
||||||
|
{
|
||||||
|
u32 soc;
|
||||||
|
|
||||||
|
soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
|
||||||
|
JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
|
||||||
|
|
||||||
|
return soc == J7200;
|
||||||
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_ARM64
|
#ifdef CONFIG_ARM64
|
||||||
void board_prep_linux(bootm_headers_t *images)
|
void board_prep_linux(bootm_headers_t *images)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -7,6 +7,10 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <asm/armv7_mpu.h>
|
#include <asm/armv7_mpu.h>
|
||||||
|
#include <asm/hardware.h>
|
||||||
|
|
||||||
|
#define J721E 0xbb64
|
||||||
|
#define J7200 0xbb6d
|
||||||
|
|
||||||
struct fwl_data {
|
struct fwl_data {
|
||||||
const char *name;
|
const char *name;
|
||||||
|
|
@ -22,3 +26,5 @@ void start_non_linux_remote_cores(void);
|
||||||
int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr);
|
int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr);
|
||||||
void k3_sysfw_print_ver(void);
|
void k3_sysfw_print_ver(void);
|
||||||
void spl_enable_dcache(void);
|
void spl_enable_dcache(void);
|
||||||
|
void mmr_unlock(phys_addr_t base, u32 partition);
|
||||||
|
bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data);
|
||||||
|
|
|
||||||
|
|
@ -58,10 +58,16 @@ SPL_ITS := u-boot-spl-k3.its
|
||||||
INPUTS-y += tispl.bin
|
INPUTS-y += tispl.bin
|
||||||
endif
|
endif
|
||||||
|
|
||||||
|
ifeq ($(CONFIG_SPL_OF_LIST),)
|
||||||
|
LIST_OF_DTB := $(CONFIG_DEFAULT_DEVICE_TREE)
|
||||||
|
else
|
||||||
|
LIST_OF_DTB := $(CONFIG_SPL_OF_LIST)
|
||||||
|
endif
|
||||||
|
|
||||||
quiet_cmd_k3_mkits = MKITS $@
|
quiet_cmd_k3_mkits = MKITS $@
|
||||||
cmd_k3_mkits = \
|
cmd_k3_mkits = \
|
||||||
$(srctree)/tools/k3_fit_atf.sh \
|
$(srctree)/tools/k3_fit_atf.sh \
|
||||||
$(patsubst %,$(obj)/dts/%.dtb,$(subst ",,$(CONFIG_SPL_OF_LIST))) > $@
|
$(patsubst %,$(obj)/dts/%.dtb,$(subst ",,$(LIST_OF_DTB))) > $@
|
||||||
|
|
||||||
$(SPL_ITS): FORCE
|
$(SPL_ITS): FORCE
|
||||||
$(call cmd,k3_mkits)
|
$(call cmd,k3_mkits)
|
||||||
|
|
|
||||||
|
|
@ -25,6 +25,8 @@
|
||||||
#define CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT 14
|
#define CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT 14
|
||||||
#define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK GENMASK(17, 17)
|
#define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK GENMASK(17, 17)
|
||||||
#define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 12
|
#define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 12
|
||||||
|
#define CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT 9
|
||||||
|
#define CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK GENMASK(10, 9)
|
||||||
|
|
||||||
#define WKUP_CTRL_MMR0_BASE 0x43000000
|
#define WKUP_CTRL_MMR0_BASE 0x43000000
|
||||||
#define MCU_CTRL_MMR0_BASE 0x40f00000
|
#define MCU_CTRL_MMR0_BASE 0x40f00000
|
||||||
|
|
|
||||||
|
|
@ -14,7 +14,8 @@
|
||||||
#define BOOT_DEVICE_I2C 0x05
|
#define BOOT_DEVICE_I2C 0x05
|
||||||
#define BOOT_DEVICE_MMC2 0x06
|
#define BOOT_DEVICE_MMC2 0x06
|
||||||
#define BOOT_DEVICE_ETHERNET 0x07
|
#define BOOT_DEVICE_ETHERNET 0x07
|
||||||
#define BOOT_DEVICE_USB 0x08
|
#define BOOT_DEVICE_DFU 0x08
|
||||||
|
#define BOOT_DEVICE_USB 0x408
|
||||||
#define BOOT_DEVICE_PCIE 0x09
|
#define BOOT_DEVICE_PCIE 0x09
|
||||||
#define BOOT_DEVICE_UART 0x0a
|
#define BOOT_DEVICE_UART 0x0a
|
||||||
#define BOOT_DEVICE_NAND 0x0c
|
#define BOOT_DEVICE_NAND 0x0c
|
||||||
|
|
|
||||||
|
|
@ -15,9 +15,17 @@
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Assuming these addresses and definitions stay common across K3 devices */
|
/* Assuming these addresses and definitions stay common across K3 devices */
|
||||||
|
#define CTRLMMR_WKUP_JTAG_ID 0x43000014
|
||||||
#define JTAG_ID_VARIANT_SHIFT 28
|
#define JTAG_ID_VARIANT_SHIFT 28
|
||||||
#define JTAG_ID_VARIANT_MASK (0xf << 28)
|
#define JTAG_ID_VARIANT_MASK (0xf << 28)
|
||||||
#define JTAG_ID_PARTNO_SHIFT 12
|
#define JTAG_ID_PARTNO_SHIFT 12
|
||||||
#define JTAG_ID_PARTNO_MASK (0xffff << 12)
|
#define JTAG_ID_PARTNO_MASK (0xffff << 12)
|
||||||
|
|
||||||
|
#define K3_ROM_BOOT_HEADER_MAGIC "EXTBOOT"
|
||||||
|
|
||||||
|
struct rom_extended_boot_data {
|
||||||
|
char header[8];
|
||||||
|
u32 num_components;
|
||||||
|
};
|
||||||
|
|
||||||
#endif /* _ASM_ARCH_HARDWARE_H_ */
|
#endif /* _ASM_ARCH_HARDWARE_H_ */
|
||||||
|
|
|
||||||
|
|
@ -51,6 +51,9 @@
|
||||||
#define CTRLMMR_LOCK_KICK1 0x0100c
|
#define CTRLMMR_LOCK_KICK1 0x0100c
|
||||||
#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
|
#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
|
||||||
|
|
||||||
|
/* ROM HANDOFF Structure location */
|
||||||
|
#define ROM_ENTENDED_BOOT_DATA_INFO 0x41cffb00
|
||||||
|
|
||||||
/* MCU SCRATCHPAD usage */
|
/* MCU SCRATCHPAD usage */
|
||||||
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
|
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -16,4 +16,7 @@ int do_board_detect(void);
|
||||||
void release_resources_for_core_shutdown(void);
|
void release_resources_for_core_shutdown(void);
|
||||||
int fdt_disable_node(void *blob, char *node_path);
|
int fdt_disable_node(void *blob, char *node_path);
|
||||||
|
|
||||||
|
bool soc_is_j721e(void);
|
||||||
|
bool soc_is_j7200(void);
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -7,6 +7,8 @@
|
||||||
#ifndef _SYSFW_LOADER_H_
|
#ifndef _SYSFW_LOADER_H_
|
||||||
#define _SYSFW_LOADER_H_
|
#define _SYSFW_LOADER_H_
|
||||||
|
|
||||||
void k3_sysfw_loader(void (*config_pm_pre_callback)(void), void (*config_pm_done_callback)(void));
|
void k3_sysfw_loader(bool rom_loaded_sysfw,
|
||||||
|
void (*config_pm_pre_callback)(void),
|
||||||
|
void (*config_pm_done_callback)(void));
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -64,16 +64,6 @@ struct fwl_data cbass_hc_cfg0_fwls[] = {
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
static void mmr_unlock(u32 base, u32 partition)
|
|
||||||
{
|
|
||||||
/* Translate the base address */
|
|
||||||
phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
|
|
||||||
|
|
||||||
/* Unlock the requested partition if locked using two-step sequence */
|
|
||||||
writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
|
|
||||||
writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void ctrl_mmr_unlock(void)
|
static void ctrl_mmr_unlock(void)
|
||||||
{
|
{
|
||||||
/* Unlock all WKUP_CTRL_MMR0 module registers */
|
/* Unlock all WKUP_CTRL_MMR0 module registers */
|
||||||
|
|
@ -97,9 +87,9 @@ static void ctrl_mmr_unlock(void)
|
||||||
mmr_unlock(CTRL_MMR0_BASE, 1);
|
mmr_unlock(CTRL_MMR0_BASE, 1);
|
||||||
mmr_unlock(CTRL_MMR0_BASE, 2);
|
mmr_unlock(CTRL_MMR0_BASE, 2);
|
||||||
mmr_unlock(CTRL_MMR0_BASE, 3);
|
mmr_unlock(CTRL_MMR0_BASE, 3);
|
||||||
mmr_unlock(CTRL_MMR0_BASE, 4);
|
|
||||||
mmr_unlock(CTRL_MMR0_BASE, 5);
|
mmr_unlock(CTRL_MMR0_BASE, 5);
|
||||||
mmr_unlock(CTRL_MMR0_BASE, 6);
|
if (soc_is_j721e())
|
||||||
|
mmr_unlock(CTRL_MMR0_BASE, 6);
|
||||||
mmr_unlock(CTRL_MMR0_BASE, 7);
|
mmr_unlock(CTRL_MMR0_BASE, 7);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -136,10 +126,13 @@ void k3_mmc_restart_clock(void)
|
||||||
* it to the .data section.
|
* it to the .data section.
|
||||||
*/
|
*/
|
||||||
u32 bootindex __attribute__((section(".data")));
|
u32 bootindex __attribute__((section(".data")));
|
||||||
|
static struct rom_extended_boot_data bootdata __section(.data);
|
||||||
|
|
||||||
static void store_boot_index_from_rom(void)
|
static void store_boot_info_from_rom(void)
|
||||||
{
|
{
|
||||||
bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
|
bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
|
||||||
|
memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
|
||||||
|
sizeof(struct rom_extended_boot_data));
|
||||||
}
|
}
|
||||||
|
|
||||||
void board_init_f(ulong dummy)
|
void board_init_f(ulong dummy)
|
||||||
|
|
@ -152,7 +145,7 @@ void board_init_f(ulong dummy)
|
||||||
* Cannot delay this further as there is a chance that
|
* Cannot delay this further as there is a chance that
|
||||||
* K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
|
* K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
|
||||||
*/
|
*/
|
||||||
store_boot_index_from_rom();
|
store_boot_info_from_rom();
|
||||||
|
|
||||||
/* Make all control module registers accessible */
|
/* Make all control module registers accessible */
|
||||||
ctrl_mmr_unlock();
|
ctrl_mmr_unlock();
|
||||||
|
|
@ -184,7 +177,8 @@ void board_init_f(ulong dummy)
|
||||||
* callback hook, effectively switching on (or over) the console
|
* callback hook, effectively switching on (or over) the console
|
||||||
* output.
|
* output.
|
||||||
*/
|
*/
|
||||||
k3_sysfw_loader(k3_mmc_stop_clock, k3_mmc_restart_clock);
|
k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
|
||||||
|
k3_mmc_stop_clock, k3_mmc_restart_clock);
|
||||||
|
|
||||||
/* Prepare console output */
|
/* Prepare console output */
|
||||||
preloader_console_init();
|
preloader_console_init();
|
||||||
|
|
@ -208,7 +202,8 @@ void board_init_f(ulong dummy)
|
||||||
k3_sysfw_print_ver();
|
k3_sysfw_print_ver();
|
||||||
|
|
||||||
/* Perform EEPROM-based board detection */
|
/* Perform EEPROM-based board detection */
|
||||||
do_board_detect();
|
if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT))
|
||||||
|
do_board_detect();
|
||||||
|
|
||||||
#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
|
#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
|
||||||
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
|
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
|
||||||
|
|
@ -370,6 +365,9 @@ void start_non_linux_remote_cores(void)
|
||||||
int size = 0, ret;
|
int size = 0, ret;
|
||||||
u32 loadaddr = 0;
|
u32 loadaddr = 0;
|
||||||
|
|
||||||
|
if (!soc_is_j721e())
|
||||||
|
return;
|
||||||
|
|
||||||
size = load_firmware("name_mainr5f0_0fw", "addr_mainr5f0_0load",
|
size = load_firmware("name_mainr5f0_0fw", "addr_mainr5f0_0load",
|
||||||
&loadaddr);
|
&loadaddr);
|
||||||
if (size <= 0)
|
if (size <= 0)
|
||||||
|
|
|
||||||
|
|
@ -33,6 +33,12 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||||
#define SYSFW_CFG_RM "rm-cfg.bin"
|
#define SYSFW_CFG_RM "rm-cfg.bin"
|
||||||
#define SYSFW_CFG_SEC "sec-cfg.bin"
|
#define SYSFW_CFG_SEC "sec-cfg.bin"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* It is assumed that remoteproc device 0 is the corresponding
|
||||||
|
* system-controller that runs SYSFW. Make sure DT reflects the same.
|
||||||
|
*/
|
||||||
|
#define K3_SYSTEM_CONTROLLER_RPROC_ID 0
|
||||||
|
|
||||||
static bool sysfw_loaded;
|
static bool sysfw_loaded;
|
||||||
static void *sysfw_load_address;
|
static void *sysfw_load_address;
|
||||||
|
|
||||||
|
|
@ -72,6 +78,26 @@ static int fit_get_data_by_name(const void *fit, int images, const char *name,
|
||||||
return fit_image_get_data(fit, node_offset, addr, size);
|
return fit_image_get_data(fit, node_offset, addr, size);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void k3_start_system_controller(int rproc_id, bool rproc_loaded,
|
||||||
|
ulong addr, ulong size)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = rproc_dev_init(rproc_id);
|
||||||
|
if (ret)
|
||||||
|
panic("rproc failed to be initialized (%d)\n", ret);
|
||||||
|
|
||||||
|
if (!rproc_loaded) {
|
||||||
|
ret = rproc_load(rproc_id, addr, size);
|
||||||
|
if (ret)
|
||||||
|
panic("Firmware failed to start on rproc (%d)\n", ret);
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = rproc_start(0);
|
||||||
|
if (ret)
|
||||||
|
panic("Firmware init failed on rproc (%d)\n", ret);
|
||||||
|
}
|
||||||
|
|
||||||
static void k3_sysfw_load_using_fit(void *fit)
|
static void k3_sysfw_load_using_fit(void *fit)
|
||||||
{
|
{
|
||||||
int images;
|
int images;
|
||||||
|
|
@ -91,23 +117,9 @@ static void k3_sysfw_load_using_fit(void *fit)
|
||||||
panic("Error accessing %s node in FIT (%d)\n", SYSFW_FIRMWARE,
|
panic("Error accessing %s node in FIT (%d)\n", SYSFW_FIRMWARE,
|
||||||
ret);
|
ret);
|
||||||
|
|
||||||
/*
|
/* Start up system controller firmware */
|
||||||
* Start up system controller firmware
|
k3_start_system_controller(K3_SYSTEM_CONTROLLER_RPROC_ID, false,
|
||||||
*
|
(ulong)sysfw_addr, (ulong)sysfw_size);
|
||||||
* It is assumed that remoteproc device 0 is the corresponding
|
|
||||||
* system-controller that runs SYSFW. Make sure DT reflects the same.
|
|
||||||
*/
|
|
||||||
ret = rproc_dev_init(0);
|
|
||||||
if (ret)
|
|
||||||
panic("rproc failed to be initialized (%d)\n", ret);
|
|
||||||
|
|
||||||
ret = rproc_load(0, (ulong)sysfw_addr, (ulong)sysfw_size);
|
|
||||||
if (ret)
|
|
||||||
panic("Firmware failed to start on rproc (%d)\n", ret);
|
|
||||||
|
|
||||||
ret = rproc_start(0);
|
|
||||||
if (ret)
|
|
||||||
panic("Firmware init failed on rproc (%d)\n", ret);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static void k3_sysfw_configure_using_fit(void *fit,
|
static void k3_sysfw_configure_using_fit(void *fit,
|
||||||
|
|
@ -223,7 +235,8 @@ static void *k3_sysfw_get_spi_addr(void)
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
void k3_sysfw_loader(void (*config_pm_pre_callback) (void),
|
void k3_sysfw_loader(bool rom_loaded_sysfw,
|
||||||
|
void (*config_pm_pre_callback)(void),
|
||||||
void (*config_pm_done_callback)(void))
|
void (*config_pm_done_callback)(void))
|
||||||
{
|
{
|
||||||
struct spl_image_info spl_image = { 0 };
|
struct spl_image_info spl_image = { 0 };
|
||||||
|
|
@ -231,6 +244,13 @@ void k3_sysfw_loader(void (*config_pm_pre_callback) (void),
|
||||||
struct ti_sci_handle *ti_sci;
|
struct ti_sci_handle *ti_sci;
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
|
|
||||||
|
if (rom_loaded_sysfw) {
|
||||||
|
k3_start_system_controller(K3_SYSTEM_CONTROLLER_RPROC_ID,
|
||||||
|
rom_loaded_sysfw, 0, 0);
|
||||||
|
sysfw_loaded = true;
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
/* Reserve a block of aligned memory for loading the SYSFW image */
|
/* Reserve a block of aligned memory for loading the SYSFW image */
|
||||||
sysfw_load_address = memalign(ARCH_DMA_MINALIGN,
|
sysfw_load_address = memalign(ARCH_DMA_MINALIGN,
|
||||||
CONFIG_K3_SYSFW_IMAGE_SIZE_MAX);
|
CONFIG_K3_SYSFW_IMAGE_SIZE_MAX);
|
||||||
|
|
@ -300,6 +320,17 @@ void k3_sysfw_loader(void (*config_pm_pre_callback) (void),
|
||||||
ret = k3_sysfw_dfu_download(sysfw_load_address);
|
ret = k3_sysfw_dfu_download(sysfw_load_address);
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
|
#if CONFIG_IS_ENABLED(USB_STORAGE)
|
||||||
|
case BOOT_DEVICE_USB:
|
||||||
|
ret = spl_usb_load(&spl_image, &bootdev,
|
||||||
|
CONFIG_SYS_USB_FAT_BOOT_PARTITION,
|
||||||
|
#ifdef CONFIG_K3_SYSFW_IMAGE_NAME
|
||||||
|
CONFIG_K3_SYSFW_IMAGE_NAME);
|
||||||
|
#else
|
||||||
|
NULL);
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
panic("Loading SYSFW image from device %u not supported!\n",
|
panic("Loading SYSFW image from device %u not supported!\n",
|
||||||
bootdev.boot_device);
|
bootdev.boot_device);
|
||||||
|
|
|
||||||
|
|
@ -61,7 +61,10 @@ config TARGET_OMAP3_EVM
|
||||||
select DM
|
select DM
|
||||||
select DM_GPIO
|
select DM_GPIO
|
||||||
select DM_SERIAL
|
select DM_SERIAL
|
||||||
|
select OMAP3_GPIO_2
|
||||||
select OMAP3_GPIO_3
|
select OMAP3_GPIO_3
|
||||||
|
select OMAP3_GPIO_5
|
||||||
|
select OMAP3_GPIO_6
|
||||||
imply CMD_DM
|
imply CMD_DM
|
||||||
|
|
||||||
config TARGET_OMAP3_IGEP00X0
|
config TARGET_OMAP3_IGEP00X0
|
||||||
|
|
|
||||||
|
|
@ -5,3 +5,5 @@ F: board/ti/am65x/
|
||||||
F: include/configs/am65x_evm.h
|
F: include/configs/am65x_evm.h
|
||||||
F: configs/am65x_evm_a53_defconfig
|
F: configs/am65x_evm_a53_defconfig
|
||||||
F: configs/am65x_evm_r5_defconfig
|
F: configs/am65x_evm_r5_defconfig
|
||||||
|
F: configs/am65x_evm_r5_usbdfu_defconfig
|
||||||
|
F: configs/am65x_evm_r5_usbmsc_defconfig
|
||||||
|
|
|
||||||
|
|
@ -101,7 +101,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)
|
||||||
{
|
{
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000", "sram@70000000");
|
ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
|
||||||
|
if (ret < 0)
|
||||||
|
ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
|
||||||
|
"sram@70000000");
|
||||||
if (ret) {
|
if (ret) {
|
||||||
printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
|
printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
|
||||||
return ret;
|
return ret;
|
||||||
|
|
@ -109,7 +112,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)
|
||||||
|
|
||||||
#if defined(CONFIG_TI_SECURE_DEVICE)
|
#if defined(CONFIG_TI_SECURE_DEVICE)
|
||||||
/* Make Crypto HW reserved for secure world use */
|
/* Make Crypto HW reserved for secure world use */
|
||||||
ret = fdt_disable_node(blob, "/interconnect@100000/crypto@4E00000");
|
ret = fdt_disable_node(blob, "/bus@100000/crypto@4e00000");
|
||||||
|
if (ret < 0)
|
||||||
|
ret = fdt_disable_node(blob,
|
||||||
|
"/interconnect@100000/crypto@4E00000");
|
||||||
if (ret)
|
if (ret)
|
||||||
printf("%s: disabling SA2UL failed %d\n", __func__, ret);
|
printf("%s: disabling SA2UL failed %d\n", __func__, ret);
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -311,6 +311,7 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr,
|
||||||
*/
|
*/
|
||||||
int __maybe_unused ti_i2c_eeprom_am6_get_base(int bus_addr, int dev_addr);
|
int __maybe_unused ti_i2c_eeprom_am6_get_base(int bus_addr, int dev_addr);
|
||||||
|
|
||||||
|
#ifdef CONFIG_TI_I2C_BOARD_DETECT
|
||||||
/**
|
/**
|
||||||
* board_ti_is() - Board detection logic for TI EVMs
|
* board_ti_is() - Board detection logic for TI EVMs
|
||||||
* @name_tag: Tag used in eeprom for the board
|
* @name_tag: Tag used in eeprom for the board
|
||||||
|
|
@ -454,5 +455,17 @@ bool board_ti_was_eeprom_read(void);
|
||||||
* Return: 0 if all went fine, else return error.
|
* Return: 0 if all went fine, else return error.
|
||||||
*/
|
*/
|
||||||
int ti_i2c_eeprom_am_set(const char *name, const char *rev);
|
int ti_i2c_eeprom_am_set(const char *name, const char *rev);
|
||||||
|
#else
|
||||||
|
static inline bool board_ti_is(char *name_tag) { return false; };
|
||||||
|
static inline bool board_ti_k3_is(char *name_tag) { return false; };
|
||||||
|
static inline bool board_ti_rev_is(char *rev_tag, int cmp_len)
|
||||||
|
{ return false; };
|
||||||
|
static inline char *board_ti_get_rev(void) { return NULL; };
|
||||||
|
static inline char *board_ti_get_config(void) { return NULL; };
|
||||||
|
static inline char *board_ti_get_name(void) { return NULL; };
|
||||||
|
static inline bool board_ti_was_eeprom_read(void) { return false; };
|
||||||
|
static inline int ti_i2c_eeprom_am_set(const char *name, const char *rev)
|
||||||
|
{ return -EINVAL; };
|
||||||
|
#endif
|
||||||
|
|
||||||
#endif /* __BOARD_DETECT_H */
|
#endif /* __BOARD_DETECT_H */
|
||||||
|
|
|
||||||
|
|
@ -16,7 +16,6 @@
|
||||||
#include <init.h>
|
#include <init.h>
|
||||||
#include <net.h>
|
#include <net.h>
|
||||||
#include <ns16550.h>
|
#include <ns16550.h>
|
||||||
#include <netdev.h>
|
|
||||||
#include <serial.h>
|
#include <serial.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/arch/mem.h>
|
#include <asm/arch/mem.h>
|
||||||
|
|
@ -24,20 +23,17 @@
|
||||||
#include <asm/arch/sys_proto.h>
|
#include <asm/arch/sys_proto.h>
|
||||||
#include <asm/arch/mmc_host_def.h>
|
#include <asm/arch/mmc_host_def.h>
|
||||||
#include <asm/gpio.h>
|
#include <asm/gpio.h>
|
||||||
#include <i2c.h>
|
|
||||||
#include <twl4030.h>
|
#include <twl4030.h>
|
||||||
#include <asm/mach-types.h>
|
#include <asm/mach-types.h>
|
||||||
#include <asm/omap_musb.h>
|
|
||||||
#include <linux/delay.h>
|
#include <linux/delay.h>
|
||||||
#include <linux/mtd/rawnand.h>
|
#include <linux/mtd/rawnand.h>
|
||||||
#include <linux/usb/ch9.h>
|
|
||||||
#include <linux/usb/gadget.h>
|
|
||||||
#include <linux/usb/musb.h>
|
|
||||||
#include "evm.h"
|
#include "evm.h"
|
||||||
|
|
||||||
#define OMAP3EVM_GPIO_ETH_RST_GEN1 64
|
#define OMAP3EVM_GPIO_ETH_RST_GEN1 64
|
||||||
#define OMAP3EVM_GPIO_ETH_RST_GEN2 7
|
#define OMAP3EVM_GPIO_ETH_RST_GEN2 7
|
||||||
|
|
||||||
|
#define CONFIG_SMC911X_BASE 0x2C000000
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
static u32 omap3_evm_version;
|
static u32 omap3_evm_version;
|
||||||
|
|
@ -49,7 +45,7 @@ u32 get_omap3_evm_rev(void)
|
||||||
|
|
||||||
static void omap3_evm_get_revision(void)
|
static void omap3_evm_get_revision(void)
|
||||||
{
|
{
|
||||||
#if defined(CONFIG_CMD_NET)
|
#if defined(CONFIG_SMC911X)
|
||||||
/*
|
/*
|
||||||
* Board revision can be ascertained only by identifying
|
* Board revision can be ascertained only by identifying
|
||||||
* the Ethernet chipset.
|
* the Ethernet chipset.
|
||||||
|
|
@ -70,7 +66,7 @@ static void omap3_evm_get_revision(void)
|
||||||
default:
|
default:
|
||||||
omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
|
omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
|
||||||
}
|
}
|
||||||
#else /* !CONFIG_CMD_NET */
|
#else /* !CONFIG_SMC911X */
|
||||||
#if defined(CONFIG_STATIC_BOARD_REV)
|
#if defined(CONFIG_STATIC_BOARD_REV)
|
||||||
/* Look for static defintion of the board revision */
|
/* Look for static defintion of the board revision */
|
||||||
omap3_evm_version = CONFIG_STATIC_BOARD_REV;
|
omap3_evm_version = CONFIG_STATIC_BOARD_REV;
|
||||||
|
|
@ -78,7 +74,7 @@ static void omap3_evm_get_revision(void)
|
||||||
/* Fallback to the default above */
|
/* Fallback to the default above */
|
||||||
omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
|
omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
|
||||||
#endif /* CONFIG_STATIC_BOARD_REV */
|
#endif /* CONFIG_STATIC_BOARD_REV */
|
||||||
#endif /* CONFIG_CMD_NET */
|
#endif /* CONFIG_SMC911X */
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)
|
#if defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)
|
||||||
|
|
@ -155,33 +151,6 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_SPL_BUILD */
|
#endif /* CONFIG_SPL_BUILD */
|
||||||
|
|
||||||
#if defined(CONFIG_USB_MUSB_OMAP2PLUS)
|
|
||||||
static struct musb_hdrc_config musb_config = {
|
|
||||||
.multipoint = 1,
|
|
||||||
.dyn_fifo = 1,
|
|
||||||
.num_eps = 16,
|
|
||||||
.ram_bits = 12,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct omap_musb_board_data musb_board_data = {
|
|
||||||
.interface_type = MUSB_INTERFACE_ULPI,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct musb_hdrc_platform_data musb_plat = {
|
|
||||||
#if defined(CONFIG_USB_MUSB_HOST)
|
|
||||||
.mode = MUSB_HOST,
|
|
||||||
#elif defined(CONFIG_USB_MUSB_GADGET)
|
|
||||||
.mode = MUSB_PERIPHERAL,
|
|
||||||
#else
|
|
||||||
#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
|
|
||||||
#endif /* CONFIG_USB_MUSB_{GADGET,HOST} */
|
|
||||||
.config = &musb_config,
|
|
||||||
.power = 100,
|
|
||||||
.platform_ops = &omap2430_ops,
|
|
||||||
.board_data = &musb_board_data,
|
|
||||||
};
|
|
||||||
#endif /* CONFIG_USB_MUSB_OMAP2PLUS */
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Routine: misc_init_r
|
* Routine: misc_init_r
|
||||||
* Description: Init ethernet (done here so udelay works)
|
* Description: Init ethernet (done here so udelay works)
|
||||||
|
|
@ -190,25 +159,18 @@ int misc_init_r(void)
|
||||||
{
|
{
|
||||||
twl4030_power_init();
|
twl4030_power_init();
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_I2C_OMAP24XX
|
#if defined(CONFIG_SMC911X)
|
||||||
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_NET)
|
|
||||||
setup_net_chip();
|
setup_net_chip();
|
||||||
#endif
|
#endif
|
||||||
omap3_evm_get_revision();
|
omap3_evm_get_revision();
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_NET)
|
#if defined(CONFIG_SMC911X)
|
||||||
reset_net_chip();
|
reset_net_chip();
|
||||||
#endif
|
#endif
|
||||||
omap_die_id_display();
|
omap_die_id_display();
|
||||||
|
|
||||||
#if defined(CONFIG_USB_MUSB_OMAP2PLUS)
|
#if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET) && \
|
||||||
musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
|
!defined(CONFIG_SMC911X)
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)
|
|
||||||
omap_die_id_usbethaddr();
|
omap_die_id_usbethaddr();
|
||||||
#endif
|
#endif
|
||||||
return 0;
|
return 0;
|
||||||
|
|
@ -225,7 +187,7 @@ void set_muxconf_regs(void)
|
||||||
MUX_EVM();
|
MUX_EVM();
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_NET)
|
#if defined(CONFIG_SMC911X)
|
||||||
/*
|
/*
|
||||||
* Routine: setup_net_chip
|
* Routine: setup_net_chip
|
||||||
* Description: Setting up the configuration GPMC registers specific to the
|
* Description: Setting up the configuration GPMC registers specific to the
|
||||||
|
|
@ -283,33 +245,11 @@ static void reset_net_chip(void)
|
||||||
udelay(1);
|
udelay(1);
|
||||||
gpio_set_value(rst_gpio, 1);
|
gpio_set_value(rst_gpio, 1);
|
||||||
}
|
}
|
||||||
|
#endif /* CONFIG_SMC911X */
|
||||||
int board_eth_init(struct bd_info *bis)
|
|
||||||
{
|
|
||||||
#if defined(CONFIG_SMC911X)
|
|
||||||
env_set("ethaddr", NULL);
|
|
||||||
return smc911x_initialize(0, CONFIG_SMC911X_BASE);
|
|
||||||
#else
|
|
||||||
return 0;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif /* CONFIG_CMD_NET */
|
|
||||||
|
|
||||||
#if defined(CONFIG_MMC)
|
#if defined(CONFIG_MMC)
|
||||||
int board_mmc_init(struct bd_info *bis)
|
|
||||||
{
|
|
||||||
return omap_mmc_init(0, 0, 0, -1, -1);
|
|
||||||
}
|
|
||||||
|
|
||||||
void board_mmc_power_init(void)
|
void board_mmc_power_init(void)
|
||||||
{
|
{
|
||||||
twl4030_power_mmc_init(0);
|
twl4030_power_mmc_init(0);
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_MMC */
|
#endif /* CONFIG_MMC */
|
||||||
|
|
||||||
#if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET) && !defined(CONFIG_CMD_NET)
|
|
||||||
int board_eth_init(struct bd_info *bis)
|
|
||||||
{
|
|
||||||
return usb_eth_initialize(bis);
|
|
||||||
}
|
|
||||||
#endif /* CONFIG_USB_ETHER */
|
|
||||||
|
|
|
||||||
|
|
@ -27,6 +27,26 @@ config TARGET_J721E_R5_EVM
|
||||||
imply SYS_K3_SPL_ATF
|
imply SYS_K3_SPL_ATF
|
||||||
imply TI_I2C_BOARD_DETECT
|
imply TI_I2C_BOARD_DETECT
|
||||||
|
|
||||||
|
config TARGET_J7200_A72_EVM
|
||||||
|
bool "TI K3 based J7200 EVM running on A72"
|
||||||
|
select ARM64
|
||||||
|
select SOC_K3_J721E
|
||||||
|
select BOARD_LATE_INIT
|
||||||
|
imply TI_I2C_BOARD_DETECT
|
||||||
|
select SYS_DISABLE_DCACHE_OPS
|
||||||
|
|
||||||
|
config TARGET_J7200_R5_EVM
|
||||||
|
bool "TI K3 based J7200 EVM running on R5"
|
||||||
|
select CPU_V7R
|
||||||
|
select SYS_THUMB_BUILD
|
||||||
|
select SOC_K3_J721E
|
||||||
|
select K3_LOAD_SYSFW
|
||||||
|
select RAM
|
||||||
|
select SPL_RAM
|
||||||
|
select K3_J721E_DDRSS
|
||||||
|
imply SYS_K3_SPL_ATF
|
||||||
|
imply TI_I2C_BOARD_DETECT
|
||||||
|
|
||||||
endchoice
|
endchoice
|
||||||
|
|
||||||
if TARGET_J721E_A72_EVM
|
if TARGET_J721E_A72_EVM
|
||||||
|
|
@ -61,3 +81,36 @@ config SPL_LDSCRIPT
|
||||||
source "board/ti/common/Kconfig"
|
source "board/ti/common/Kconfig"
|
||||||
|
|
||||||
endif
|
endif
|
||||||
|
|
||||||
|
if TARGET_J7200_A72_EVM
|
||||||
|
|
||||||
|
config SYS_BOARD
|
||||||
|
default "j721e"
|
||||||
|
|
||||||
|
config SYS_VENDOR
|
||||||
|
default "ti"
|
||||||
|
|
||||||
|
config SYS_CONFIG_NAME
|
||||||
|
default "j721e_evm"
|
||||||
|
|
||||||
|
source "board/ti/common/Kconfig"
|
||||||
|
|
||||||
|
endif
|
||||||
|
|
||||||
|
if TARGET_J7200_R5_EVM
|
||||||
|
|
||||||
|
config SYS_BOARD
|
||||||
|
default "j721e"
|
||||||
|
|
||||||
|
config SYS_VENDOR
|
||||||
|
default "ti"
|
||||||
|
|
||||||
|
config SYS_CONFIG_NAME
|
||||||
|
default "j721e_evm"
|
||||||
|
|
||||||
|
config SPL_LDSCRIPT
|
||||||
|
default "arch/arm/mach-omap2/u-boot-spl.lds"
|
||||||
|
|
||||||
|
source "board/ti/common/Kconfig"
|
||||||
|
|
||||||
|
endif
|
||||||
|
|
|
||||||
|
|
@ -5,3 +5,5 @@ F: board/ti/j721e
|
||||||
F: include/configs/j721e_evm.h
|
F: include/configs/j721e_evm.h
|
||||||
F: configs/j721e_evm_r5_defconfig
|
F: configs/j721e_evm_r5_defconfig
|
||||||
F: configs/j721e_evm_a72_defconfig
|
F: configs/j721e_evm_a72_defconfig
|
||||||
|
F: configs/j7200_evm_r5_defconfig
|
||||||
|
F: configs/j7200_evm_a72_defconfig
|
||||||
|
|
|
||||||
|
|
@ -28,6 +28,8 @@
|
||||||
#define board_is_j721e_som() (board_ti_k3_is("J721EX-PM1-SOM") || \
|
#define board_is_j721e_som() (board_ti_k3_is("J721EX-PM1-SOM") || \
|
||||||
board_ti_k3_is("J721EX-PM2-SOM"))
|
board_ti_k3_is("J721EX-PM2-SOM"))
|
||||||
|
|
||||||
|
#define board_is_j7200_som() board_ti_k3_is("J7200X-PM1-SOM")
|
||||||
|
|
||||||
/* Max number of MAC addresses that are parsed/processed per daughter card */
|
/* Max number of MAC addresses that are parsed/processed per daughter card */
|
||||||
#define DAUGHTER_CARD_NO_OF_MAC_ADDR 8
|
#define DAUGHTER_CARD_NO_OF_MAC_ADDR 8
|
||||||
|
|
||||||
|
|
@ -87,19 +89,53 @@ int board_fit_config_name_match(const char *name)
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if CONFIG_IS_ENABLED(DM_GPIO) && CONFIG_IS_ENABLED(OF_LIBFDT)
|
||||||
|
/* Returns 1, if onboard mux is set to hyperflash */
|
||||||
|
static void __maybe_unused detect_enable_hyperflash(void *blob)
|
||||||
|
{
|
||||||
|
struct gpio_desc desc = {0};
|
||||||
|
|
||||||
|
if (dm_gpio_lookup_name("6", &desc))
|
||||||
|
return;
|
||||||
|
|
||||||
|
if (dm_gpio_request(&desc, "6"))
|
||||||
|
return;
|
||||||
|
|
||||||
|
if (dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN))
|
||||||
|
return;
|
||||||
|
|
||||||
|
if (dm_gpio_get_value(&desc)) {
|
||||||
|
int offset;
|
||||||
|
|
||||||
|
do_fixup_by_compat(blob, "ti,am654-hbmc", "status",
|
||||||
|
"okay", sizeof("okay"), 0);
|
||||||
|
offset = fdt_node_offset_by_compatible(blob, -1,
|
||||||
|
"ti,j721e-ospi");
|
||||||
|
fdt_setprop(blob, offset, "status", "disabled",
|
||||||
|
sizeof("disabled"));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
int ft_board_setup(void *blob, struct bd_info *bd)
|
||||||
{
|
{
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000", "sram@70000000");
|
ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
|
||||||
|
if (ret < 0)
|
||||||
|
ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
|
||||||
|
"sram@70000000");
|
||||||
if (ret)
|
if (ret)
|
||||||
printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
|
printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
|
||||||
|
|
||||||
|
detect_enable_hyperflash(blob);
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_TI_I2C_BOARD_DETECT
|
||||||
int do_board_detect(void)
|
int do_board_detect(void)
|
||||||
{
|
{
|
||||||
int ret;
|
int ret;
|
||||||
|
|
@ -135,6 +171,8 @@ static void setup_board_eeprom_env(void)
|
||||||
|
|
||||||
if (board_is_j721e_som())
|
if (board_is_j721e_som())
|
||||||
name = "j721e";
|
name = "j721e";
|
||||||
|
else if (board_is_j7200_som())
|
||||||
|
name = "j7200";
|
||||||
else
|
else
|
||||||
printf("Unidentified board claims %s in eeprom header\n",
|
printf("Unidentified board claims %s in eeprom header\n",
|
||||||
board_ti_get_name());
|
board_ti_get_name());
|
||||||
|
|
@ -336,14 +374,17 @@ static int probe_daughtercards(void)
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
int board_late_init(void)
|
int board_late_init(void)
|
||||||
{
|
{
|
||||||
setup_board_eeprom_env();
|
if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
|
||||||
setup_serial();
|
setup_board_eeprom_env();
|
||||||
|
setup_serial();
|
||||||
|
|
||||||
/* Check for and probe any plugged-in daughtercards */
|
/* Check for and probe any plugged-in daughtercards */
|
||||||
probe_daughtercards();
|
probe_daughtercards();
|
||||||
|
}
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
@ -355,7 +396,10 @@ void spl_board_init(void)
|
||||||
int ret;
|
int ret;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
probe_daughtercards();
|
if ((IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM) ||
|
||||||
|
IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM)) &&
|
||||||
|
IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT))
|
||||||
|
probe_daughtercards();
|
||||||
|
|
||||||
#ifdef CONFIG_ESM_K3
|
#ifdef CONFIG_ESM_K3
|
||||||
if (board_ti_k3_is("J721EX-PM2-SOM")) {
|
if (board_ti_k3_is("J721EX-PM2-SOM")) {
|
||||||
|
|
|
||||||
|
|
@ -18,14 +18,20 @@
|
||||||
|
|
||||||
static int usb_stor_curr_dev = -1; /* current device */
|
static int usb_stor_curr_dev = -1; /* current device */
|
||||||
|
|
||||||
static int spl_usb_load_image(struct spl_image_info *spl_image,
|
int spl_usb_load(struct spl_image_info *spl_image,
|
||||||
struct spl_boot_device *bootdev)
|
struct spl_boot_device *bootdev, int partition,
|
||||||
|
const char *filename)
|
||||||
{
|
{
|
||||||
int err;
|
int err = 0;
|
||||||
struct blk_desc *stor_dev;
|
struct blk_desc *stor_dev;
|
||||||
|
static bool usb_init_pending = true;
|
||||||
|
|
||||||
|
if (usb_init_pending) {
|
||||||
|
usb_stop();
|
||||||
|
err = usb_init();
|
||||||
|
usb_init_pending = false;
|
||||||
|
}
|
||||||
|
|
||||||
usb_stop();
|
|
||||||
err = usb_init();
|
|
||||||
if (err) {
|
if (err) {
|
||||||
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
|
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||||
printf("%s: usb init failed: err - %d\n", __func__, err);
|
printf("%s: usb init failed: err - %d\n", __func__, err);
|
||||||
|
|
@ -43,13 +49,10 @@ static int spl_usb_load_image(struct spl_image_info *spl_image,
|
||||||
|
|
||||||
#ifdef CONFIG_SPL_OS_BOOT
|
#ifdef CONFIG_SPL_OS_BOOT
|
||||||
if (spl_start_uboot() ||
|
if (spl_start_uboot() ||
|
||||||
spl_load_image_fat_os(spl_image, stor_dev,
|
spl_load_image_fat_os(spl_image, stor_dev, partition))
|
||||||
CONFIG_SYS_USB_FAT_BOOT_PARTITION))
|
|
||||||
#endif
|
#endif
|
||||||
{
|
{
|
||||||
err = spl_load_image_fat(spl_image, stor_dev,
|
err = spl_load_image_fat(spl_image, stor_dev, partition, filename);
|
||||||
CONFIG_SYS_USB_FAT_BOOT_PARTITION,
|
|
||||||
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
if (err) {
|
if (err) {
|
||||||
|
|
@ -59,4 +62,12 @@ static int spl_usb_load_image(struct spl_image_info *spl_image,
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int spl_usb_load_image(struct spl_image_info *spl_image,
|
||||||
|
struct spl_boot_device *bootdev)
|
||||||
|
{
|
||||||
|
return spl_usb_load(spl_image, bootdev,
|
||||||
|
CONFIG_SYS_USB_FAT_BOOT_PARTITION,
|
||||||
|
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
|
||||||
|
}
|
||||||
SPL_LOAD_IMAGE_METHOD("USB", 0, BOOT_DEVICE_USB, spl_usb_load_image);
|
SPL_LOAD_IMAGE_METHOD("USB", 0, BOOT_DEVICE_USB, spl_usb_load_image);
|
||||||
|
|
|
||||||
|
|
@ -26,6 +26,7 @@ CONFIG_DEFAULT_DEVICE_TREE="k3-am654-base-board"
|
||||||
CONFIG_DISTRO_DEFAULTS=y
|
CONFIG_DISTRO_DEFAULTS=y
|
||||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
CONFIG_SPL_LOAD_FIT=y
|
CONFIG_SPL_LOAD_FIT=y
|
||||||
|
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
|
||||||
# CONFIG_USE_SPL_FIT_GENERATOR is not set
|
# CONFIG_USE_SPL_FIT_GENERATOR is not set
|
||||||
CONFIG_OF_BOARD_SETUP=y
|
CONFIG_OF_BOARD_SETUP=y
|
||||||
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
|
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
|
||||||
|
|
@ -36,15 +37,21 @@ CONFIG_SPL_SEPARATE_BSS=y
|
||||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
|
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
|
||||||
CONFIG_SPL_DMA=y
|
CONFIG_SPL_DMA=y
|
||||||
|
CONFIG_SPL_ENV_SUPPORT=y
|
||||||
CONFIG_SPL_I2C_SUPPORT=y
|
CONFIG_SPL_I2C_SUPPORT=y
|
||||||
CONFIG_SPL_DM_MAILBOX=y
|
CONFIG_SPL_DM_MAILBOX=y
|
||||||
CONFIG_SPL_MTD_SUPPORT=y
|
CONFIG_SPL_MTD_SUPPORT=y
|
||||||
CONFIG_SPL_DM_SPI_FLASH=y
|
CONFIG_SPL_DM_SPI_FLASH=y
|
||||||
CONFIG_SPL_DM_RESET=y
|
CONFIG_SPL_DM_RESET=y
|
||||||
CONFIG_SPL_POWER_DOMAIN=y
|
CONFIG_SPL_POWER_DOMAIN=y
|
||||||
|
CONFIG_SPL_RAM_SUPPORT=y
|
||||||
# CONFIG_SPL_SPI_FLASH_TINY is not set
|
# CONFIG_SPL_SPI_FLASH_TINY is not set
|
||||||
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
|
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
|
||||||
CONFIG_SPL_SPI_LOAD=y
|
CONFIG_SPL_SPI_LOAD=y
|
||||||
|
CONFIG_SPL_USB_HOST_SUPPORT=y
|
||||||
|
CONFIG_SPL_USB_STORAGE=y
|
||||||
|
CONFIG_SPL_USB_GADGET=y
|
||||||
|
CONFIG_SPL_DFU=y
|
||||||
CONFIG_SPL_YMODEM_SUPPORT=y
|
CONFIG_SPL_YMODEM_SUPPORT=y
|
||||||
CONFIG_CMD_ASKENV=y
|
CONFIG_CMD_ASKENV=y
|
||||||
CONFIG_CMD_DFU=y
|
CONFIG_CMD_DFU=y
|
||||||
|
|
@ -74,6 +81,7 @@ CONFIG_DM=y
|
||||||
CONFIG_SPL_DM=y
|
CONFIG_SPL_DM=y
|
||||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||||
CONFIG_SPL_REGMAP=y
|
CONFIG_SPL_REGMAP=y
|
||||||
|
CONFIG_SPL_SYSCON=y
|
||||||
CONFIG_SPL_OF_TRANSLATE=y
|
CONFIG_SPL_OF_TRANSLATE=y
|
||||||
CONFIG_CLK=y
|
CONFIG_CLK=y
|
||||||
CONFIG_SPL_CLK=y
|
CONFIG_SPL_CLK=y
|
||||||
|
|
@ -114,6 +122,7 @@ CONFIG_PCI=y
|
||||||
CONFIG_DM_PCI=y
|
CONFIG_DM_PCI=y
|
||||||
CONFIG_PCI_KEYSTONE=y
|
CONFIG_PCI_KEYSTONE=y
|
||||||
CONFIG_PHY=y
|
CONFIG_PHY=y
|
||||||
|
CONFIG_SPL_PHY=y
|
||||||
CONFIG_AM654_PHY=y
|
CONFIG_AM654_PHY=y
|
||||||
CONFIG_OMAP_USB2_PHY=y
|
CONFIG_OMAP_USB2_PHY=y
|
||||||
CONFIG_PINCTRL=y
|
CONFIG_PINCTRL=y
|
||||||
|
|
@ -139,6 +148,7 @@ CONFIG_SYSRESET_TI_SCI=y
|
||||||
CONFIG_USB=y
|
CONFIG_USB=y
|
||||||
CONFIG_DM_USB=y
|
CONFIG_DM_USB=y
|
||||||
CONFIG_DM_USB_GADGET=y
|
CONFIG_DM_USB_GADGET=y
|
||||||
|
CONFIG_SPL_DM_USB_GADGET=y
|
||||||
CONFIG_USB_XHCI_HCD=y
|
CONFIG_USB_XHCI_HCD=y
|
||||||
CONFIG_USB_XHCI_DWC3=y
|
CONFIG_USB_XHCI_DWC3=y
|
||||||
CONFIG_USB_DWC3=y
|
CONFIG_USB_DWC3=y
|
||||||
|
|
|
||||||
120
configs/am65x_evm_r5_usbdfu_defconfig
Normal file
120
configs/am65x_evm_r5_usbdfu_defconfig
Normal file
|
|
@ -0,0 +1,120 @@
|
||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_ARCH_K3=y
|
||||||
|
CONFIG_SPL_GPIO_SUPPORT=y
|
||||||
|
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||||
|
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||||
|
CONFIG_SYS_MALLOC_F_LEN=0x55000
|
||||||
|
CONFIG_SOC_K3_AM6=y
|
||||||
|
CONFIG_K3_EARLY_CONS=y
|
||||||
|
CONFIG_TARGET_AM654_R5_EVM=y
|
||||||
|
CONFIG_ENV_SIZE=0x20000
|
||||||
|
CONFIG_DM_GPIO=y
|
||||||
|
CONFIG_SPL_TEXT_BASE=0x41c00000
|
||||||
|
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||||
|
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||||
|
CONFIG_SPL_STACK_R_ADDR=0x82000000
|
||||||
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
|
CONFIG_SPL_FS_FAT=y
|
||||||
|
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||||
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
|
CONFIG_SPL_LOAD_FIT=y
|
||||||
|
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
|
||||||
|
CONFIG_USE_BOOTCOMMAND=y
|
||||||
|
# CONFIG_DISPLAY_CPUINFO is not set
|
||||||
|
CONFIG_SPL_STACK_R=y
|
||||||
|
CONFIG_SPL_SEPARATE_BSS=y
|
||||||
|
CONFIG_SPL_EARLY_BSS=y
|
||||||
|
CONFIG_SPL_DMA=y
|
||||||
|
CONFIG_SPL_ENV_SUPPORT=y
|
||||||
|
CONFIG_SPL_I2C_SUPPORT=y
|
||||||
|
CONFIG_SPL_DM_MAILBOX=y
|
||||||
|
CONFIG_SPL_DM_RESET=y
|
||||||
|
CONFIG_SPL_POWER_SUPPORT=y
|
||||||
|
CONFIG_SPL_POWER_DOMAIN=y
|
||||||
|
CONFIG_SPL_RAM_SUPPORT=y
|
||||||
|
CONFIG_SPL_RAM_DEVICE=y
|
||||||
|
CONFIG_SPL_REMOTEPROC=y
|
||||||
|
CONFIG_SPL_USB_GADGET=y
|
||||||
|
CONFIG_SPL_DFU=y
|
||||||
|
CONFIG_SPL_YMODEM_SUPPORT=y
|
||||||
|
CONFIG_HUSH_PARSER=y
|
||||||
|
CONFIG_CMD_BOOTZ=y
|
||||||
|
CONFIG_CMD_ASKENV=y
|
||||||
|
CONFIG_CMD_DFU=y
|
||||||
|
CONFIG_CMD_GPT=y
|
||||||
|
CONFIG_CMD_I2C=y
|
||||||
|
CONFIG_CMD_REMOTEPROC=y
|
||||||
|
# CONFIG_CMD_SETEXPR is not set
|
||||||
|
CONFIG_CMD_TIME=y
|
||||||
|
CONFIG_CMD_FAT=y
|
||||||
|
CONFIG_OF_CONTROL=y
|
||||||
|
CONFIG_SPL_OF_CONTROL=y
|
||||||
|
CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
|
||||||
|
CONFIG_SPL_MULTI_DTB_FIT=y
|
||||||
|
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
|
||||||
|
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||||
|
CONFIG_DM=y
|
||||||
|
CONFIG_SPL_DM=y
|
||||||
|
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||||
|
CONFIG_REGMAP=y
|
||||||
|
CONFIG_SPL_REGMAP=y
|
||||||
|
CONFIG_SYSCON=y
|
||||||
|
CONFIG_SPL_SYSCON=y
|
||||||
|
CONFIG_SPL_OF_TRANSLATE=y
|
||||||
|
CONFIG_BLK=y
|
||||||
|
CONFIG_CLK=y
|
||||||
|
CONFIG_SPL_CLK=y
|
||||||
|
CONFIG_CLK_TI_SCI=y
|
||||||
|
CONFIG_TI_SCI_PROTOCOL=y
|
||||||
|
CONFIG_DA8XX_GPIO=y
|
||||||
|
CONFIG_DM_I2C=y
|
||||||
|
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
|
||||||
|
CONFIG_SYS_I2C_OMAP24XX=y
|
||||||
|
CONFIG_DM_MAILBOX=y
|
||||||
|
CONFIG_K3_SEC_PROXY=y
|
||||||
|
CONFIG_MISC=y
|
||||||
|
CONFIG_K3_AVS0=y
|
||||||
|
# CONFIG_MMC is not set
|
||||||
|
CONFIG_PHY=y
|
||||||
|
CONFIG_SPL_PHY=y
|
||||||
|
CONFIG_OMAP_USB2_PHY=y
|
||||||
|
CONFIG_PINCTRL=y
|
||||||
|
# CONFIG_PINCTRL_GENERIC is not set
|
||||||
|
CONFIG_SPL_PINCTRL=y
|
||||||
|
# CONFIG_SPL_PINCTRL_GENERIC is not set
|
||||||
|
CONFIG_PINCTRL_SINGLE=y
|
||||||
|
CONFIG_POWER_DOMAIN=y
|
||||||
|
CONFIG_TI_SCI_POWER_DOMAIN=y
|
||||||
|
CONFIG_DM_REGULATOR=y
|
||||||
|
CONFIG_SPL_DM_REGULATOR=y
|
||||||
|
CONFIG_DM_REGULATOR_GPIO=y
|
||||||
|
CONFIG_SPL_DM_REGULATOR_GPIO=y
|
||||||
|
CONFIG_DM_REGULATOR_TPS62360=y
|
||||||
|
CONFIG_RAM=y
|
||||||
|
CONFIG_SPL_RAM=y
|
||||||
|
CONFIG_K3_SYSTEM_CONTROLLER=y
|
||||||
|
CONFIG_REMOTEPROC_TI_K3_ARM64=y
|
||||||
|
CONFIG_DM_RESET=y
|
||||||
|
CONFIG_RESET_TI_SCI=y
|
||||||
|
CONFIG_DM_SERIAL=y
|
||||||
|
CONFIG_SYSRESET=y
|
||||||
|
CONFIG_SPL_SYSRESET=y
|
||||||
|
CONFIG_SYSRESET_TI_SCI=y
|
||||||
|
CONFIG_TIMER=y
|
||||||
|
CONFIG_SPL_TIMER=y
|
||||||
|
CONFIG_OMAP_TIMER=y
|
||||||
|
CONFIG_USB=y
|
||||||
|
CONFIG_DM_USB=y
|
||||||
|
CONFIG_DM_USB_GADGET=y
|
||||||
|
CONFIG_SPL_DM_USB_GADGET=y
|
||||||
|
CONFIG_USB_XHCI_HCD=y
|
||||||
|
CONFIG_USB_XHCI_DWC3=y
|
||||||
|
CONFIG_USB_DWC3=y
|
||||||
|
CONFIG_USB_DWC3_GENERIC=y
|
||||||
|
CONFIG_USB_STORAGE=y
|
||||||
|
CONFIG_USB_GADGET=y
|
||||||
|
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
|
||||||
|
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
|
||||||
|
CONFIG_USB_GADGET_PRODUCT_NUM=0x6162
|
||||||
|
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||||
|
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
|
||||||
119
configs/am65x_evm_r5_usbmsc_defconfig
Normal file
119
configs/am65x_evm_r5_usbmsc_defconfig
Normal file
|
|
@ -0,0 +1,119 @@
|
||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_ARCH_K3=y
|
||||||
|
CONFIG_SPL_GPIO_SUPPORT=y
|
||||||
|
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||||
|
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||||
|
CONFIG_SYS_MALLOC_F_LEN=0x55000
|
||||||
|
CONFIG_SOC_K3_AM6=y
|
||||||
|
CONFIG_K3_EARLY_CONS=y
|
||||||
|
CONFIG_TARGET_AM654_R5_EVM=y
|
||||||
|
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||||
|
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||||
|
CONFIG_ENV_SIZE=0x20000
|
||||||
|
CONFIG_SPL_STACK_R_ADDR=0x82000000
|
||||||
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
|
CONFIG_SPL_FS_FAT=y
|
||||||
|
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||||
|
CONFIG_SPL_TEXT_BASE=0x41c00000
|
||||||
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
|
CONFIG_SPL_LOAD_FIT=y
|
||||||
|
CONFIG_USE_BOOTCOMMAND=y
|
||||||
|
# CONFIG_DISPLAY_CPUINFO is not set
|
||||||
|
CONFIG_SPL_STACK_R=y
|
||||||
|
CONFIG_SPL_SEPARATE_BSS=y
|
||||||
|
CONFIG_SPL_EARLY_BSS=y
|
||||||
|
CONFIG_SPL_DMA=y
|
||||||
|
CONFIG_SPL_ENV_SUPPORT=y
|
||||||
|
CONFIG_SPL_I2C_SUPPORT=y
|
||||||
|
CONFIG_SPL_DM_MAILBOX=y
|
||||||
|
CONFIG_SPL_DM_RESET=y
|
||||||
|
CONFIG_SPL_POWER_SUPPORT=y
|
||||||
|
CONFIG_SPL_POWER_DOMAIN=y
|
||||||
|
CONFIG_SPL_RAM_SUPPORT=y
|
||||||
|
CONFIG_SPL_RAM_DEVICE=y
|
||||||
|
CONFIG_SPL_REMOTEPROC=y
|
||||||
|
CONFIG_SPL_USB_HOST_SUPPORT=y
|
||||||
|
CONFIG_SPL_USB_STORAGE=y
|
||||||
|
CONFIG_SPL_USB_GADGET=y
|
||||||
|
CONFIG_SPL_YMODEM_SUPPORT=y
|
||||||
|
CONFIG_HUSH_PARSER=y
|
||||||
|
CONFIG_CMD_BOOTZ=y
|
||||||
|
CONFIG_CMD_ASKENV=y
|
||||||
|
CONFIG_CMD_GPT=y
|
||||||
|
CONFIG_CMD_I2C=y
|
||||||
|
CONFIG_CMD_REMOTEPROC=y
|
||||||
|
# CONFIG_CMD_SETEXPR is not set
|
||||||
|
CONFIG_CMD_TIME=y
|
||||||
|
CONFIG_CMD_FAT=y
|
||||||
|
CONFIG_OF_CONTROL=y
|
||||||
|
CONFIG_SPL_OF_CONTROL=y
|
||||||
|
CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
|
||||||
|
CONFIG_SPL_MULTI_DTB_FIT=y
|
||||||
|
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
|
||||||
|
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||||
|
CONFIG_DM=y
|
||||||
|
CONFIG_SPL_DM=y
|
||||||
|
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||||
|
CONFIG_REGMAP=y
|
||||||
|
CONFIG_SPL_REGMAP=y
|
||||||
|
CONFIG_SYSCON=y
|
||||||
|
CONFIG_SPL_SYSCON=y
|
||||||
|
CONFIG_SPL_OF_TRANSLATE=y
|
||||||
|
CONFIG_BLK=y
|
||||||
|
CONFIG_CLK=y
|
||||||
|
CONFIG_SPL_CLK=y
|
||||||
|
CONFIG_CLK_TI_SCI=y
|
||||||
|
CONFIG_TI_SCI_PROTOCOL=y
|
||||||
|
CONFIG_DM_GPIO=y
|
||||||
|
CONFIG_DA8XX_GPIO=y
|
||||||
|
CONFIG_DM_I2C=y
|
||||||
|
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
|
||||||
|
CONFIG_SYS_I2C_OMAP24XX=y
|
||||||
|
CONFIG_DM_MAILBOX=y
|
||||||
|
CONFIG_K3_SEC_PROXY=y
|
||||||
|
CONFIG_MISC=y
|
||||||
|
CONFIG_K3_AVS0=y
|
||||||
|
# CONFIG_MMC is not set
|
||||||
|
CONFIG_PHY=y
|
||||||
|
CONFIG_SPL_PHY=y
|
||||||
|
CONFIG_OMAP_USB2_PHY=y
|
||||||
|
CONFIG_PINCTRL=y
|
||||||
|
# CONFIG_PINCTRL_GENERIC is not set
|
||||||
|
CONFIG_SPL_PINCTRL=y
|
||||||
|
# CONFIG_SPL_PINCTRL_GENERIC is not set
|
||||||
|
CONFIG_PINCTRL_SINGLE=y
|
||||||
|
CONFIG_POWER_DOMAIN=y
|
||||||
|
CONFIG_TI_SCI_POWER_DOMAIN=y
|
||||||
|
CONFIG_DM_REGULATOR=y
|
||||||
|
CONFIG_SPL_DM_REGULATOR=y
|
||||||
|
CONFIG_DM_REGULATOR_GPIO=y
|
||||||
|
CONFIG_SPL_DM_REGULATOR_GPIO=y
|
||||||
|
CONFIG_DM_REGULATOR_TPS62360=y
|
||||||
|
CONFIG_RAM=y
|
||||||
|
CONFIG_SPL_RAM=y
|
||||||
|
CONFIG_K3_SYSTEM_CONTROLLER=y
|
||||||
|
CONFIG_REMOTEPROC_TI_K3_ARM64=y
|
||||||
|
CONFIG_DM_RESET=y
|
||||||
|
CONFIG_RESET_TI_SCI=y
|
||||||
|
CONFIG_DM_SERIAL=y
|
||||||
|
CONFIG_SYSRESET=y
|
||||||
|
CONFIG_SPL_SYSRESET=y
|
||||||
|
CONFIG_SYSRESET_TI_SCI=y
|
||||||
|
CONFIG_TIMER=y
|
||||||
|
CONFIG_SPL_TIMER=y
|
||||||
|
CONFIG_OMAP_TIMER=y
|
||||||
|
CONFIG_USB=y
|
||||||
|
CONFIG_DM_USB=y
|
||||||
|
CONFIG_DM_USB_GADGET=y
|
||||||
|
CONFIG_SPL_DM_USB_GADGET=y
|
||||||
|
CONFIG_USB_XHCI_HCD=y
|
||||||
|
CONFIG_USB_XHCI_DWC3=y
|
||||||
|
CONFIG_USB_DWC3=y
|
||||||
|
CONFIG_USB_DWC3_GENERIC=y
|
||||||
|
CONFIG_USB_STORAGE=y
|
||||||
|
CONFIG_USB_GADGET=y
|
||||||
|
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
|
||||||
|
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
|
||||||
|
CONFIG_USB_GADGET_PRODUCT_NUM=0x6162
|
||||||
|
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||||
|
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
|
||||||
173
configs/j7200_evm_a72_defconfig
Normal file
173
configs/j7200_evm_a72_defconfig
Normal file
|
|
@ -0,0 +1,173 @@
|
||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_ARCH_K3=y
|
||||||
|
CONFIG_SPL_GPIO_SUPPORT=y
|
||||||
|
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||||
|
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||||
|
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||||
|
CONFIG_SOC_K3_J721E=y
|
||||||
|
CONFIG_TARGET_J7200_A72_EVM=y
|
||||||
|
CONFIG_ENV_SIZE=0x20000
|
||||||
|
CONFIG_ENV_OFFSET=0x680000
|
||||||
|
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
|
||||||
|
CONFIG_DM_GPIO=y
|
||||||
|
CONFIG_SPL_DM_SPI=y
|
||||||
|
CONFIG_SPL_TEXT_BASE=0x80080000
|
||||||
|
CONFIG_SPL_MMC_SUPPORT=y
|
||||||
|
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||||
|
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||||
|
CONFIG_SPL_STACK_R_ADDR=0x82000000
|
||||||
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
|
CONFIG_ENV_OFFSET_REDUND=0x6A0000
|
||||||
|
CONFIG_SPL_FS_FAT=y
|
||||||
|
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||||
|
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||||
|
CONFIG_SPL_SPI_SUPPORT=y
|
||||||
|
# CONFIG_PSCI_RESET is not set
|
||||||
|
CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-common-proc-board"
|
||||||
|
CONFIG_DISTRO_DEFAULTS=y
|
||||||
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
|
CONFIG_SPL_LOAD_FIT=y
|
||||||
|
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
|
||||||
|
# CONFIG_USE_SPL_FIT_GENERATOR is not set
|
||||||
|
CONFIG_OF_BOARD_SETUP=y
|
||||||
|
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
|
||||||
|
CONFIG_SPL_BOARD_INIT=y
|
||||||
|
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||||
|
CONFIG_SPL_STACK_R=y
|
||||||
|
CONFIG_SPL_SEPARATE_BSS=y
|
||||||
|
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||||
|
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
|
||||||
|
CONFIG_SPL_DMA=y
|
||||||
|
CONFIG_SPL_ENV_SUPPORT=y
|
||||||
|
CONFIG_SPL_I2C_SUPPORT=y
|
||||||
|
CONFIG_SPL_DM_MAILBOX=y
|
||||||
|
CONFIG_SPL_DM_SPI_FLASH=y
|
||||||
|
CONFIG_SPL_DM_RESET=y
|
||||||
|
CONFIG_SPL_POWER_SUPPORT=y
|
||||||
|
CONFIG_SPL_POWER_DOMAIN=y
|
||||||
|
CONFIG_SPL_RAM_SUPPORT=y
|
||||||
|
CONFIG_SPL_RAM_DEVICE=y
|
||||||
|
# CONFIG_SPL_SPI_FLASH_TINY is not set
|
||||||
|
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
|
||||||
|
CONFIG_SPL_SPI_LOAD=y
|
||||||
|
CONFIG_SPL_USB_GADGET=y
|
||||||
|
CONFIG_SPL_DFU=y
|
||||||
|
CONFIG_SPL_YMODEM_SUPPORT=y
|
||||||
|
CONFIG_CMD_ASKENV=y
|
||||||
|
CONFIG_CMD_DFU=y
|
||||||
|
# CONFIG_CMD_FLASH is not set
|
||||||
|
CONFIG_CMD_GPIO=y
|
||||||
|
CONFIG_CMD_GPT=y
|
||||||
|
CONFIG_CMD_I2C=y
|
||||||
|
CONFIG_CMD_MMC=y
|
||||||
|
CONFIG_CMD_MTD=y
|
||||||
|
CONFIG_CMD_UFS=y
|
||||||
|
CONFIG_CMD_USB=y
|
||||||
|
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||||
|
# CONFIG_CMD_SETEXPR is not set
|
||||||
|
CONFIG_CMD_TIME=y
|
||||||
|
CONFIG_CMD_EXT4_WRITE=y
|
||||||
|
CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
|
||||||
|
CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)"
|
||||||
|
CONFIG_CMD_UBI=y
|
||||||
|
# CONFIG_ISO_PARTITION is not set
|
||||||
|
# CONFIG_SPL_EFI_PARTITION is not set
|
||||||
|
CONFIG_OF_CONTROL=y
|
||||||
|
CONFIG_SPL_OF_CONTROL=y
|
||||||
|
CONFIG_SPL_MULTI_DTB_FIT=y
|
||||||
|
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
|
||||||
|
CONFIG_ENV_OVERWRITE=y
|
||||||
|
CONFIG_ENV_IS_IN_MMC=y
|
||||||
|
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||||
|
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||||
|
CONFIG_NET_RANDOM_ETHADDR=y
|
||||||
|
CONFIG_DM=y
|
||||||
|
CONFIG_SPL_DM=y
|
||||||
|
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||||
|
CONFIG_REGMAP=y
|
||||||
|
CONFIG_SPL_REGMAP=y
|
||||||
|
CONFIG_SYSCON=y
|
||||||
|
CONFIG_SPL_OF_TRANSLATE=y
|
||||||
|
CONFIG_CLK=y
|
||||||
|
CONFIG_SPL_CLK=y
|
||||||
|
CONFIG_CLK_TI_SCI=y
|
||||||
|
CONFIG_DFU_MMC=y
|
||||||
|
CONFIG_DFU_RAM=y
|
||||||
|
CONFIG_DFU_SF=y
|
||||||
|
CONFIG_DMA_CHANNELS=y
|
||||||
|
CONFIG_TI_K3_NAVSS_UDMA=y
|
||||||
|
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||||
|
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
|
||||||
|
CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
|
||||||
|
CONFIG_FASTBOOT_FLASH=y
|
||||||
|
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||||
|
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||||
|
CONFIG_TI_SCI_PROTOCOL=y
|
||||||
|
CONFIG_DA8XX_GPIO=y
|
||||||
|
CONFIG_DM_PCA953X=y
|
||||||
|
CONFIG_DM_I2C=y
|
||||||
|
CONFIG_SYS_I2C_OMAP24XX=y
|
||||||
|
CONFIG_DM_MAILBOX=y
|
||||||
|
CONFIG_K3_SEC_PROXY=y
|
||||||
|
CONFIG_DM_MMC=y
|
||||||
|
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||||
|
CONFIG_MMC_SDHCI=y
|
||||||
|
CONFIG_MMC_SDHCI_ADMA=y
|
||||||
|
CONFIG_SPL_MMC_SDHCI_ADMA=y
|
||||||
|
CONFIG_MMC_SDHCI_AM654=y
|
||||||
|
CONFIG_MTD=y
|
||||||
|
CONFIG_DM_MTD=y
|
||||||
|
CONFIG_MTD_NOR_FLASH=y
|
||||||
|
CONFIG_FLASH_CFI_DRIVER=y
|
||||||
|
CONFIG_CFI_FLASH=y
|
||||||
|
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||||
|
CONFIG_FLASH_CFI_MTD=y
|
||||||
|
CONFIG_SYS_FLASH_CFI=y
|
||||||
|
CONFIG_HBMC_AM654=y
|
||||||
|
CONFIG_DM_SPI_FLASH=y
|
||||||
|
CONFIG_SPI_FLASH_STMICRO=y
|
||||||
|
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||||
|
CONFIG_SPI_FLASH_MTD=y
|
||||||
|
CONFIG_PHY_FIXED=y
|
||||||
|
CONFIG_DM_ETH=y
|
||||||
|
CONFIG_TI_AM65_CPSW_NUSS=y
|
||||||
|
CONFIG_PINCTRL=y
|
||||||
|
# CONFIG_PINCTRL_GENERIC is not set
|
||||||
|
CONFIG_SPL_PINCTRL=y
|
||||||
|
# CONFIG_SPL_PINCTRL_GENERIC is not set
|
||||||
|
CONFIG_PINCTRL_SINGLE=y
|
||||||
|
CONFIG_POWER_DOMAIN=y
|
||||||
|
CONFIG_TI_SCI_POWER_DOMAIN=y
|
||||||
|
CONFIG_RAM=y
|
||||||
|
CONFIG_SPL_RAM=y
|
||||||
|
CONFIG_DM_RESET=y
|
||||||
|
CONFIG_RESET_TI_SCI=y
|
||||||
|
CONFIG_SCSI=y
|
||||||
|
CONFIG_DM_SCSI=y
|
||||||
|
CONFIG_DM_SERIAL=y
|
||||||
|
CONFIG_SOC_DEVICE=y
|
||||||
|
CONFIG_SOC_DEVICE_TI_K3=y
|
||||||
|
CONFIG_SOC_TI=y
|
||||||
|
CONFIG_SPI=y
|
||||||
|
CONFIG_DM_SPI=y
|
||||||
|
CONFIG_CADENCE_QSPI=y
|
||||||
|
CONFIG_SYSRESET=y
|
||||||
|
CONFIG_SPL_SYSRESET=y
|
||||||
|
CONFIG_SYSRESET_TI_SCI=y
|
||||||
|
CONFIG_USB=y
|
||||||
|
CONFIG_DM_USB=y
|
||||||
|
CONFIG_DM_USB_GADGET=y
|
||||||
|
CONFIG_SPL_DM_USB_GADGET=y
|
||||||
|
CONFIG_USB_XHCI_HCD=y
|
||||||
|
CONFIG_USB_CDNS3=y
|
||||||
|
CONFIG_USB_CDNS3_GADGET=y
|
||||||
|
CONFIG_USB_CDNS3_HOST=y
|
||||||
|
CONFIG_SPL_USB_CDNS3_GADGET=y
|
||||||
|
CONFIG_USB_GADGET=y
|
||||||
|
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
|
||||||
|
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
|
||||||
|
CONFIG_USB_GADGET_PRODUCT_NUM=0x6164
|
||||||
|
CONFIG_UFS=y
|
||||||
|
CONFIG_CADENCE_UFS=y
|
||||||
|
CONFIG_TI_J721E_UFS=y
|
||||||
|
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||||
130
configs/j7200_evm_r5_defconfig
Normal file
130
configs/j7200_evm_r5_defconfig
Normal file
|
|
@ -0,0 +1,130 @@
|
||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_ARCH_K3=y
|
||||||
|
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||||
|
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||||
|
CONFIG_SYS_MALLOC_F_LEN=0x70000
|
||||||
|
CONFIG_SOC_K3_J721E=y
|
||||||
|
CONFIG_K3_EARLY_CONS=y
|
||||||
|
CONFIG_TARGET_J7200_R5_EVM=y
|
||||||
|
CONFIG_ENV_SIZE=0x20000
|
||||||
|
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
|
||||||
|
CONFIG_DM_GPIO=y
|
||||||
|
CONFIG_SPL_DM_SPI=y
|
||||||
|
CONFIG_SPL_TEXT_BASE=0x41c00000
|
||||||
|
CONFIG_SPL_MMC_SUPPORT=y
|
||||||
|
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||||
|
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||||
|
CONFIG_SPL_STACK_R_ADDR=0x82000000
|
||||||
|
CONFIG_SPL_FS_FAT=y
|
||||||
|
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||||
|
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||||
|
CONFIG_SPL_SPI_SUPPORT=y
|
||||||
|
CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-r5-common-proc-board"
|
||||||
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
|
CONFIG_SPL_LOAD_FIT=y
|
||||||
|
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
|
||||||
|
# CONFIG_USE_SPL_FIT_GENERATOR is not set
|
||||||
|
CONFIG_USE_BOOTCOMMAND=y
|
||||||
|
# CONFIG_DISPLAY_CPUINFO is not set
|
||||||
|
CONFIG_SPL_BOARD_INIT=y
|
||||||
|
CONFIG_SPL_STACK_R=y
|
||||||
|
CONFIG_SPL_SEPARATE_BSS=y
|
||||||
|
CONFIG_SPL_EARLY_BSS=y
|
||||||
|
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||||
|
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
|
||||||
|
CONFIG_SPL_DMA=y
|
||||||
|
CONFIG_SPL_ENV_SUPPORT=y
|
||||||
|
CONFIG_SPL_FS_EXT4=y
|
||||||
|
CONFIG_SPL_I2C_SUPPORT=y
|
||||||
|
CONFIG_SPL_DM_MAILBOX=y
|
||||||
|
CONFIG_SPL_DM_SPI_FLASH=y
|
||||||
|
CONFIG_SPL_DM_RESET=y
|
||||||
|
CONFIG_SPL_POWER_SUPPORT=y
|
||||||
|
CONFIG_SPL_POWER_DOMAIN=y
|
||||||
|
CONFIG_SPL_RAM_SUPPORT=y
|
||||||
|
CONFIG_SPL_RAM_DEVICE=y
|
||||||
|
CONFIG_SPL_REMOTEPROC=y
|
||||||
|
# CONFIG_SPL_SPI_FLASH_TINY is not set
|
||||||
|
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
|
||||||
|
CONFIG_SPL_SPI_LOAD=y
|
||||||
|
CONFIG_SPL_USB_GADGET=y
|
||||||
|
CONFIG_SPL_DFU=y
|
||||||
|
CONFIG_SPL_YMODEM_SUPPORT=y
|
||||||
|
CONFIG_HUSH_PARSER=y
|
||||||
|
CONFIG_CMD_DFU=y
|
||||||
|
# CONFIG_CMD_FLASH is not set
|
||||||
|
CONFIG_CMD_GPT=y
|
||||||
|
CONFIG_CMD_MMC=y
|
||||||
|
CONFIG_CMD_REMOTEPROC=y
|
||||||
|
# CONFIG_CMD_SETEXPR is not set
|
||||||
|
CONFIG_CMD_TIME=y
|
||||||
|
CONFIG_CMD_FAT=y
|
||||||
|
CONFIG_OF_CONTROL=y
|
||||||
|
CONFIG_SPL_OF_CONTROL=y
|
||||||
|
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||||
|
CONFIG_DM=y
|
||||||
|
CONFIG_SPL_DM=y
|
||||||
|
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||||
|
CONFIG_REGMAP=y
|
||||||
|
CONFIG_SPL_REGMAP=y
|
||||||
|
CONFIG_SPL_OF_TRANSLATE=y
|
||||||
|
CONFIG_CLK=y
|
||||||
|
CONFIG_SPL_CLK=y
|
||||||
|
CONFIG_CLK_TI_SCI=y
|
||||||
|
CONFIG_DMA_CHANNELS=y
|
||||||
|
CONFIG_TI_K3_NAVSS_UDMA=y
|
||||||
|
CONFIG_TI_SCI_PROTOCOL=y
|
||||||
|
CONFIG_DA8XX_GPIO=y
|
||||||
|
CONFIG_DM_PCA953X=y
|
||||||
|
CONFIG_DM_I2C=y
|
||||||
|
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
|
||||||
|
CONFIG_SYS_I2C_OMAP24XX=y
|
||||||
|
CONFIG_DM_MAILBOX=y
|
||||||
|
CONFIG_K3_SEC_PROXY=y
|
||||||
|
CONFIG_DM_MMC=y
|
||||||
|
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||||
|
CONFIG_MMC_SDHCI=y
|
||||||
|
CONFIG_SPL_MMC_SDHCI_ADMA=y
|
||||||
|
CONFIG_MMC_SDHCI_AM654=y
|
||||||
|
CONFIG_MTD=y
|
||||||
|
CONFIG_DM_SPI_FLASH=y
|
||||||
|
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
||||||
|
CONFIG_SPI_FLASH_STMICRO=y
|
||||||
|
CONFIG_PINCTRL=y
|
||||||
|
# CONFIG_PINCTRL_GENERIC is not set
|
||||||
|
CONFIG_SPL_PINCTRL=y
|
||||||
|
# CONFIG_SPL_PINCTRL_GENERIC is not set
|
||||||
|
CONFIG_PINCTRL_SINGLE=y
|
||||||
|
CONFIG_POWER_DOMAIN=y
|
||||||
|
CONFIG_TI_SCI_POWER_DOMAIN=y
|
||||||
|
CONFIG_K3_SYSTEM_CONTROLLER=y
|
||||||
|
CONFIG_REMOTEPROC_TI_K3_ARM64=y
|
||||||
|
CONFIG_DM_RESET=y
|
||||||
|
CONFIG_RESET_TI_SCI=y
|
||||||
|
CONFIG_DM_SERIAL=y
|
||||||
|
CONFIG_SOC_DEVICE=y
|
||||||
|
CONFIG_SOC_DEVICE_TI_K3=y
|
||||||
|
CONFIG_SOC_TI=y
|
||||||
|
CONFIG_SPI=y
|
||||||
|
CONFIG_DM_SPI=y
|
||||||
|
CONFIG_CADENCE_QSPI=y
|
||||||
|
CONFIG_SYSRESET=y
|
||||||
|
CONFIG_SPL_SYSRESET=y
|
||||||
|
CONFIG_SYSRESET_TI_SCI=y
|
||||||
|
CONFIG_TIMER=y
|
||||||
|
CONFIG_SPL_TIMER=y
|
||||||
|
CONFIG_OMAP_TIMER=y
|
||||||
|
CONFIG_USB=y
|
||||||
|
CONFIG_DM_USB=y
|
||||||
|
CONFIG_DM_USB_GADGET=y
|
||||||
|
CONFIG_SPL_DM_USB_GADGET=y
|
||||||
|
CONFIG_USB_CDNS3=y
|
||||||
|
CONFIG_USB_CDNS3_GADGET=y
|
||||||
|
CONFIG_SPL_USB_CDNS3_GADGET=y
|
||||||
|
CONFIG_USB_GADGET=y
|
||||||
|
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
|
||||||
|
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
|
||||||
|
CONFIG_USB_GADGET_PRODUCT_NUM=0x6164
|
||||||
|
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||||
|
CONFIG_FS_EXT4=y
|
||||||
|
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
|
||||||
|
|
@ -11,6 +11,7 @@ CONFIG_SPL=y
|
||||||
CONFIG_DEFAULT_DEVICE_TREE="omap3-evm"
|
CONFIG_DEFAULT_DEVICE_TREE="omap3-evm"
|
||||||
CONFIG_DISTRO_DEFAULTS=y
|
CONFIG_DISTRO_DEFAULTS=y
|
||||||
CONFIG_USE_PREBOOT=y
|
CONFIG_USE_PREBOOT=y
|
||||||
|
CONFIG_PREBOOT="usb start"
|
||||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||||
CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb"
|
CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb"
|
||||||
CONFIG_VERSION_VARIABLE=y
|
CONFIG_VERSION_VARIABLE=y
|
||||||
|
|
@ -43,7 +44,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
|
||||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(spl),1920k(u-boot),128k(u-boot-env),128k(dtb),6m(kernel),-(rootfs)"
|
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(spl),1920k(u-boot),128k(u-boot-env),128k(dtb),6m(kernel),-(rootfs)"
|
||||||
CONFIG_CMD_UBI=y
|
CONFIG_CMD_UBI=y
|
||||||
# CONFIG_ISO_PARTITION is not set
|
# CONFIG_ISO_PARTITION is not set
|
||||||
# CONFIG_EFI_PARTITION is not set
|
# CONFIG_SPL_EFI_PARTITION is not set
|
||||||
CONFIG_SPL_PARTITION_UUIDS=y
|
CONFIG_SPL_PARTITION_UUIDS=y
|
||||||
CONFIG_OF_CONTROL=y
|
CONFIG_OF_CONTROL=y
|
||||||
CONFIG_SPL_OF_CONTROL=y
|
CONFIG_SPL_OF_CONTROL=y
|
||||||
|
|
@ -53,19 +54,18 @@ CONFIG_ENV_IS_IN_NAND=y
|
||||||
CONFIG_SPL_DM=y
|
CONFIG_SPL_DM=y
|
||||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||||
CONFIG_SPL_OF_TRANSLATE=y
|
CONFIG_SPL_OF_TRANSLATE=y
|
||||||
# CONFIG_SPL_BLK is not set
|
|
||||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||||
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
|
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
|
||||||
|
CONFIG_GPIO_HOG=y
|
||||||
CONFIG_DM_MMC=y
|
CONFIG_DM_MMC=y
|
||||||
# CONFIG_SPL_DM_MMC is not set
|
|
||||||
CONFIG_MMC_OMAP_HS=y
|
CONFIG_MMC_OMAP_HS=y
|
||||||
CONFIG_MTD=y
|
CONFIG_MTD=y
|
||||||
CONFIG_MTD_RAW_NAND=y
|
CONFIG_MTD_RAW_NAND=y
|
||||||
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
|
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
|
||||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
|
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
|
||||||
|
CONFIG_DM_ETH=y
|
||||||
CONFIG_SMC911X=y
|
CONFIG_SMC911X=y
|
||||||
CONFIG_SMC911X_BASE=0x2C000000
|
|
||||||
CONFIG_SMC911X_32_BIT=y
|
CONFIG_SMC911X_32_BIT=y
|
||||||
CONFIG_SPI=y
|
CONFIG_SPI=y
|
||||||
CONFIG_DM_SPI=y
|
CONFIG_DM_SPI=y
|
||||||
|
|
@ -82,6 +82,10 @@ CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
|
||||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
|
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
|
||||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x5678
|
CONFIG_USB_GADGET_PRODUCT_NUM=0x5678
|
||||||
CONFIG_USB_ETHER=y
|
CONFIG_USB_ETHER=y
|
||||||
|
CONFIG_USB_HOST_ETHER=y
|
||||||
|
CONFIG_USB_ETHER_ASIX=y
|
||||||
|
CONFIG_USB_ETHER_MCS7830=y
|
||||||
|
CONFIG_USB_ETHER_SMSC95XX=y
|
||||||
|
CONFIG_VIDEO_OMAP3=y
|
||||||
CONFIG_FAT_WRITE=y
|
CONFIG_FAT_WRITE=y
|
||||||
CONFIG_BCH=y
|
CONFIG_BCH=y
|
||||||
# CONFIG_EFI_LOADER is not set
|
|
||||||
|
|
|
||||||
|
|
@ -75,7 +75,7 @@ struct am654_sdhci_plat {
|
||||||
struct mmc mmc;
|
struct mmc mmc;
|
||||||
struct regmap *base;
|
struct regmap *base;
|
||||||
bool non_removable;
|
bool non_removable;
|
||||||
u32 otap_del_sel[11];
|
u32 otap_del_sel[MMC_MODES_END];
|
||||||
u32 trm_icp;
|
u32 trm_icp;
|
||||||
u32 drv_strength;
|
u32 drv_strength;
|
||||||
u32 strb_sel;
|
u32 strb_sel;
|
||||||
|
|
|
||||||
|
|
@ -199,7 +199,6 @@ uint32_t lpddr4_init(lpddr4_privatedata * pd, const lpddr4_config * cfg)
|
||||||
{
|
{
|
||||||
uint32_t result = 0U;
|
uint32_t result = 0U;
|
||||||
uint16_t productid = 0U;
|
uint16_t productid = 0U;
|
||||||
uint32_t version[2] = { 0, 0 };
|
|
||||||
|
|
||||||
result = lpddr4_initsf(pd, cfg);
|
result = lpddr4_initsf(pd, cfg);
|
||||||
if (result == (uint32_t) CDN_EOK) {
|
if (result == (uint32_t) CDN_EOK) {
|
||||||
|
|
@ -209,20 +208,7 @@ uint32_t lpddr4_init(lpddr4_privatedata * pd, const lpddr4_config * cfg)
|
||||||
CPS_REG_READ(&
|
CPS_REG_READ(&
|
||||||
(ctlregbase->
|
(ctlregbase->
|
||||||
LPDDR4__CONTROLLER_ID__REG))));
|
LPDDR4__CONTROLLER_ID__REG))));
|
||||||
version[0] =
|
if (productid == PRODUCT_ID) {
|
||||||
(uint32_t) (CPS_FLD_READ
|
|
||||||
(LPDDR4__CONTROLLER_VERSION_0__FLD,
|
|
||||||
CPS_REG_READ(&
|
|
||||||
(ctlregbase->
|
|
||||||
LPDDR4__CONTROLLER_VERSION_0__REG))));
|
|
||||||
version[1] =
|
|
||||||
(uint32_t) (CPS_FLD_READ
|
|
||||||
(LPDDR4__CONTROLLER_VERSION_1__FLD,
|
|
||||||
CPS_REG_READ(&
|
|
||||||
(ctlregbase->
|
|
||||||
LPDDR4__CONTROLLER_VERSION_1__REG))));
|
|
||||||
if ((productid == PRODUCT_ID) && (version[0] == VERSION_0)
|
|
||||||
&& (version[1] == VERSION_1)) {
|
|
||||||
/* Populating configuration data to pD */
|
/* Populating configuration data to pD */
|
||||||
pd->ctlbase = ctlregbase;
|
pd->ctlbase = ctlregbase;
|
||||||
pd->infohandler =
|
pd->infohandler =
|
||||||
|
|
|
||||||
|
|
@ -12,6 +12,7 @@
|
||||||
|
|
||||||
#define AM65X 0xbb5a
|
#define AM65X 0xbb5a
|
||||||
#define J721E 0xbb64
|
#define J721E 0xbb64
|
||||||
|
#define J7200 0xbb6d
|
||||||
|
|
||||||
#define REV_SR1_0 0
|
#define REV_SR1_0 0
|
||||||
#define REV_SR2_0 1
|
#define REV_SR2_0 1
|
||||||
|
|
@ -40,6 +41,9 @@ static const char *get_family_string(u32 idreg)
|
||||||
case J721E:
|
case J721E:
|
||||||
family = "J721E";
|
family = "J721E";
|
||||||
break;
|
break;
|
||||||
|
case J7200:
|
||||||
|
family = "J7200";
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
family = "Unknown Silicon";
|
family = "Unknown Silicon";
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -155,6 +155,13 @@ config WDT_ORION
|
||||||
Select this to enable Orion watchdog timer, which can be found on some
|
Select this to enable Orion watchdog timer, which can be found on some
|
||||||
Marvell Armada chips.
|
Marvell Armada chips.
|
||||||
|
|
||||||
|
config WDT_K3_RTI
|
||||||
|
bool "Texas Instruments K3 RTI watchdog"
|
||||||
|
depends on WDT && ARCH_K3
|
||||||
|
help
|
||||||
|
Say Y here if you want to include support for the K3 watchdog
|
||||||
|
timer (RTI module) available in the K3 generation of processors.
|
||||||
|
|
||||||
config WDT_SANDBOX
|
config WDT_SANDBOX
|
||||||
bool "Enable Watchdog Timer support for Sandbox"
|
bool "Enable Watchdog Timer support for Sandbox"
|
||||||
depends on SANDBOX && WDT
|
depends on SANDBOX && WDT
|
||||||
|
|
|
||||||
|
|
@ -28,6 +28,7 @@ obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
|
||||||
obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
|
obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
|
||||||
obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o
|
obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o
|
||||||
obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o
|
obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o
|
||||||
|
obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o
|
||||||
obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
|
obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
|
||||||
obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o
|
obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o
|
||||||
obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o
|
obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o
|
||||||
|
|
|
||||||
123
drivers/watchdog/rti_wdt.c
Normal file
123
drivers/watchdog/rti_wdt.c
Normal file
|
|
@ -0,0 +1,123 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* Copyright (c) Siemens AG, 2020
|
||||||
|
*
|
||||||
|
* Authors:
|
||||||
|
* Jan Kiszka <jan.kiszka@siemens.com>
|
||||||
|
*
|
||||||
|
* Derived from linux/drivers/watchdog/rti_wdt.c
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <clk.h>
|
||||||
|
#include <dm.h>
|
||||||
|
#include <power-domain.h>
|
||||||
|
#include <wdt.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
|
||||||
|
/* Timer register set definition */
|
||||||
|
#define RTIDWDCTRL 0x90
|
||||||
|
#define RTIDWDPRLD 0x94
|
||||||
|
#define RTIWDSTATUS 0x98
|
||||||
|
#define RTIWDKEY 0x9c
|
||||||
|
#define RTIDWDCNTR 0xa0
|
||||||
|
#define RTIWWDRXCTRL 0xa4
|
||||||
|
#define RTIWWDSIZECTRL 0xa8
|
||||||
|
|
||||||
|
#define RTIWWDRX_NMI 0xa
|
||||||
|
|
||||||
|
#define RTIWWDSIZE_50P 0x50
|
||||||
|
|
||||||
|
#define WDENABLE_KEY 0xa98559da
|
||||||
|
|
||||||
|
#define WDKEY_SEQ0 0xe51a
|
||||||
|
#define WDKEY_SEQ1 0xa35c
|
||||||
|
|
||||||
|
#define WDT_PRELOAD_SHIFT 13
|
||||||
|
|
||||||
|
#define WDT_PRELOAD_MAX 0xfff
|
||||||
|
|
||||||
|
struct rti_wdt_priv {
|
||||||
|
phys_addr_t regs;
|
||||||
|
unsigned int clk_khz;
|
||||||
|
};
|
||||||
|
|
||||||
|
static int rti_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
|
||||||
|
{
|
||||||
|
struct rti_wdt_priv *priv = dev_get_priv(dev);
|
||||||
|
u32 timer_margin;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
if (readl(priv->regs + RTIDWDCTRL) == WDENABLE_KEY)
|
||||||
|
return -EBUSY;
|
||||||
|
|
||||||
|
timer_margin = timeout_ms * priv->clk_khz / 1000;
|
||||||
|
timer_margin >>= WDT_PRELOAD_SHIFT;
|
||||||
|
if (timer_margin > WDT_PRELOAD_MAX)
|
||||||
|
timer_margin = WDT_PRELOAD_MAX;
|
||||||
|
|
||||||
|
writel(timer_margin, priv->regs + RTIDWDPRLD);
|
||||||
|
writel(RTIWWDRX_NMI, priv->regs + RTIWWDRXCTRL);
|
||||||
|
writel(RTIWWDSIZE_50P, priv->regs + RTIWWDSIZECTRL);
|
||||||
|
|
||||||
|
readl(priv->regs + RTIWWDSIZECTRL);
|
||||||
|
|
||||||
|
writel(WDENABLE_KEY, priv->regs + RTIDWDCTRL);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int rti_wdt_reset(struct udevice *dev)
|
||||||
|
{
|
||||||
|
struct rti_wdt_priv *priv = dev_get_priv(dev);
|
||||||
|
u32 prld;
|
||||||
|
|
||||||
|
/* Make sure we do not reset too early */
|
||||||
|
prld = readl(priv->regs + RTIDWDPRLD) << WDT_PRELOAD_SHIFT;
|
||||||
|
if (readl(priv->regs + RTIDWDCNTR) >= prld / 2)
|
||||||
|
return -EPERM;
|
||||||
|
|
||||||
|
writel(WDKEY_SEQ0, priv->regs + RTIWDKEY);
|
||||||
|
writel(WDKEY_SEQ1, priv->regs + RTIWDKEY);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int rti_wdt_probe(struct udevice *dev)
|
||||||
|
{
|
||||||
|
struct rti_wdt_priv *priv = dev_get_priv(dev);
|
||||||
|
struct clk clk;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
priv->regs = devfdt_get_addr(dev);
|
||||||
|
if (!priv->regs)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
ret = clk_get_by_index(dev, 0, &clk);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
priv->clk_khz = clk_get_rate(&clk);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct wdt_ops rti_wdt_ops = {
|
||||||
|
.start = rti_wdt_start,
|
||||||
|
.reset = rti_wdt_reset,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct udevice_id rti_wdt_ids[] = {
|
||||||
|
{ .compatible = "ti,j7-rti-wdt" },
|
||||||
|
{ }
|
||||||
|
};
|
||||||
|
|
||||||
|
U_BOOT_DRIVER(rti_wdt) = {
|
||||||
|
.name = "rti_wdt",
|
||||||
|
.id = UCLASS_WDT,
|
||||||
|
.of_match = rti_wdt_ids,
|
||||||
|
.ops = &rti_wdt_ops,
|
||||||
|
.probe = rti_wdt_probe,
|
||||||
|
.priv_auto_alloc_size = sizeof(struct rti_wdt_priv),
|
||||||
|
.flags = DM_FLAG_REMOVE_WITH_PD_ON,
|
||||||
|
};
|
||||||
|
|
@ -22,6 +22,7 @@
|
||||||
#ifdef CONFIG_TARGET_AM654_A53_EVM
|
#ifdef CONFIG_TARGET_AM654_A53_EVM
|
||||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
|
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
|
||||||
CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
|
CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
|
||||||
|
#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x20000
|
||||||
#else
|
#else
|
||||||
/*
|
/*
|
||||||
* Maximum size in memory allocated to the SPL BSS. Keep it as tight as
|
* Maximum size in memory allocated to the SPL BSS. Keep it as tight as
|
||||||
|
|
@ -44,6 +45,7 @@
|
||||||
/* Configure R5 SPL post-relocation malloc pool in DDR */
|
/* Configure R5 SPL post-relocation malloc pool in DDR */
|
||||||
#define CONFIG_SYS_SPL_MALLOC_START 0x84000000
|
#define CONFIG_SYS_SPL_MALLOC_START 0x84000000
|
||||||
#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M
|
#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M
|
||||||
|
#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x5000
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_K3_SPL_ATF
|
#ifdef CONFIG_SYS_K3_SPL_ATF
|
||||||
|
|
@ -124,8 +126,8 @@
|
||||||
"rootfstype=ubifs root=ubi0:rootfs rw ubi.mtd=ospi.rootfs\0"
|
"rootfstype=ubifs root=ubi0:rootfs rw ubi.mtd=ospi.rootfs\0"
|
||||||
|
|
||||||
#define EXTRA_ENV_DFUARGS \
|
#define EXTRA_ENV_DFUARGS \
|
||||||
"dfu_bufsiz=0x20000\0" \
|
|
||||||
DFU_ALT_INFO_MMC \
|
DFU_ALT_INFO_MMC \
|
||||||
|
DFU_ALT_INFO_RAM \
|
||||||
DFU_ALT_INFO_EMMC \
|
DFU_ALT_INFO_EMMC \
|
||||||
DFU_ALT_INFO_OSPI
|
DFU_ALT_INFO_OSPI
|
||||||
|
|
||||||
|
|
@ -140,6 +142,8 @@
|
||||||
EXTRA_ENV_RPROC_SETTINGS \
|
EXTRA_ENV_RPROC_SETTINGS \
|
||||||
EXTRA_ENV_DFUARGS
|
EXTRA_ENV_DFUARGS
|
||||||
|
|
||||||
|
#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
|
||||||
|
|
||||||
/* Now for the remaining common defines */
|
/* Now for the remaining common defines */
|
||||||
#include <configs/ti_armv7_common.h>
|
#include <configs/ti_armv7_common.h>
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -20,7 +20,7 @@
|
||||||
#define CONFIG_SYS_SDRAM_BASE1 0x880000000
|
#define CONFIG_SYS_SDRAM_BASE1 0x880000000
|
||||||
|
|
||||||
/* SPL Loader Configuration */
|
/* SPL Loader Configuration */
|
||||||
#ifdef CONFIG_TARGET_J721E_A72_EVM
|
#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
|
||||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
|
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
|
||||||
CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
|
CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
|
||||||
/* Image load address in RAM for DFU boot*/
|
/* Image load address in RAM for DFU boot*/
|
||||||
|
|
@ -127,7 +127,7 @@
|
||||||
DFU_ALT_INFO_RAM \
|
DFU_ALT_INFO_RAM \
|
||||||
DFU_ALT_INFO_OSPI
|
DFU_ALT_INFO_OSPI
|
||||||
|
|
||||||
#ifdef CONFIG_TARGET_J721E_A72_EVM
|
#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
|
||||||
#define EXTRA_ENV_J721E_BOARD_SETTINGS_MTD \
|
#define EXTRA_ENV_J721E_BOARD_SETTINGS_MTD \
|
||||||
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
|
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
|
||||||
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
|
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
|
||||||
|
|
|
||||||
|
|
@ -503,6 +503,20 @@ int spl_mmc_load(struct spl_image_info *spl_image,
|
||||||
int raw_part,
|
int raw_part,
|
||||||
unsigned long raw_sect);
|
unsigned long raw_sect);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* spl_usb_load() - Load an image file from USB mass storage
|
||||||
|
*
|
||||||
|
* @param spl_image Image data filled in by loading process
|
||||||
|
* @param bootdev Describes which device to load from
|
||||||
|
* @param raw_part Fat partition to load from
|
||||||
|
* @param filename Name of file to load
|
||||||
|
*
|
||||||
|
* @return 0 on success, otherwise error code
|
||||||
|
*/
|
||||||
|
int spl_usb_load(struct spl_image_info *spl_image,
|
||||||
|
struct spl_boot_device *bootdev,
|
||||||
|
int partition, const char *filename);
|
||||||
|
|
||||||
int spl_ymodem_load_image(struct spl_image_info *spl_image,
|
int spl_ymodem_load_image(struct spl_image_info *spl_image,
|
||||||
struct spl_boot_device *bootdev);
|
struct spl_boot_device *bootdev);
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue
Block a user