brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-07-05 02:36:39 +09:00
Code Issues Projects Releases Wiki Activity

arm: ls102xa: Remove bit reversing for SCFG registers

Browse Source 
SCFG_SCFGREVCR is SCFG bit reverse register. This register
must be written with 0xFFFFFFFF before writing to any other
SCFG register. Then other SCFG register could be written in
big-endian mode.

Address: 157_0000h base + 200h offset = 157_0200h
Bit   0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
W/R                                   SCFGREV
Reset 0 0 0 0 0 0 0 0 0 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
0-31
SCFGREV SCFG Bit Reverse Control Filed
32'h 0000_0000 - No bit reverse is applied
32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be stored/read as
0:31

This patch removes the bit reversing for SCFG registers in
u-boot. It will be implemented through PBI commands in RCW
.pbi
write 0x570200, 0xffffffff
.end
So other SCFG register could be written in big-endian mode
in u-boot or kernel directly.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Alison Wang 2014-10-17 15:26:33 +08:00 committed by York Sun
parent 644bc7ec5c
commit c207ff6129
3 changed files with 0 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
View File

@ -95,8 +95,6 @@ struct ccsr_gur {
u32 sdhcpcr;
};
#define SCFG_SCFGREVCR_REV 0xffffffff
#define SCFG_SCFGREVCR_NOREV 0
#define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f
#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
#define SCFG_PIXCLKCR_PXCKEN 0x80000000

2
board/freescale/ls1021aqds/ls1021aqds.c
View File

@ -140,9 +140,7 @@ int board_early_init_f(void)
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
#ifdef CONFIG_TSEC_ENET
out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
#endif
#ifdef CONFIG_FSL_IFC

5
board/freescale/ls1021atwr/ls1021atwr.c
View File

@ -255,11 +255,8 @@ int board_early_init_f(void)
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET
out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
udelay(10);
out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
#endif
#ifdef CONFIG_FSL_IFC
@ -267,9 +264,7 @@ int board_early_init_f(void)
#endif
#ifdef CONFIG_FSL_DCU_FB
out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
#endif
return 0;