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fix: phy: marvell: cp110: sata: update analog parameters according to latest ETP
Add SATA analog parameters initialization values according to latest ETP. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Igal Liberman
Stefan Roese
parent
d37f020e6f
commit
c01f9fe858
@ -360,15 +360,15 @@ static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src,
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reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
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/* Configure initial and final coefficient value for receiver */
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mask = HPIPE_G3_RX_SELMUPI_MASK;
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data = 0x1 << HPIPE_G3_RX_SELMUPI_OFFSET;
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mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK;
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data = 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET;
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mask |= HPIPE_G3_RX_SELMUPF_MASK;
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data |= 0x1 << HPIPE_G3_RX_SELMUPF_OFFSET;
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mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK;
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data |= 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET;
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mask |= HPIPE_G3_SETTING_BIT_MASK;
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data |= 0x0 << HPIPE_G3_SETTING_BIT_OFFSET;
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reg_set(hpipe_addr + HPIPE_G3_SETTINGS_1_REG, data, mask);
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mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK;
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data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET;
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reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask);
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/* Trigger sampler enable pulse */
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mask = HPIPE_SMAPLER_MASK;
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@ -693,10 +693,176 @@ static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
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0x2 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
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debug("stage: Analog paramters from ETP(HW)\n");
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/*
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* TODO: Set analog paramters from ETP(HW) - for now use the
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* default datas
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*/
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/* Set analog parameters from ETP(HW) */
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/* G1 settings */
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mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
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data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
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mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
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data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
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mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
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data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET;
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mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
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data |= 0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET;
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mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK;
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data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET;
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reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
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mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK;
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data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET;
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mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK;
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data |= 0x2 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
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mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
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data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
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mask |= HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK;
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data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET;
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mask |= HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK;
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data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET;
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reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
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/* G2 settings */
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mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
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data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
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mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK;
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data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET;
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mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
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data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
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mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK;
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data |= 0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET;
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mask |= HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK;
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data |= 0x1 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET;
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reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
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/* G3 settings */
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mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK;
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data = 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET;
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mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK;
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data |= 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET;
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mask |= HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK;
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data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET;
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mask |= HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK;
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data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET;
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mask |= HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK;
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data |= 0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET;
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mask |= HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK;
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data |= 0x2 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET;
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mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK;
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data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET;
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reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask);
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/* DTL Control */
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mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK;
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data = 0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET;
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mask |= HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK;
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data |= 0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET;
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mask |= HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
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data |= 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
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mask |= HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK;
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data |= 0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET;
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mask |= HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK;
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data |= 0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET;
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mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_MASK;
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data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET;
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mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK;
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data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET;
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reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
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/* Trigger sampler enable pulse (by toggleing the bit) */
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mask = HPIPE_SMAPLER_MASK;
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data = 0x1 << HPIPE_SMAPLER_OFFSET;
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reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
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mask = HPIPE_SMAPLER_MASK;
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data = 0x0 << HPIPE_SMAPLER_OFFSET;
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reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
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/* VDD Calibration Control 3 */
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mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
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data = 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
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reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
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/* DFE Resolution Control */
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mask = HPIPE_DFE_RES_FORCE_MASK;
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data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
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reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
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/* DFE F3-F5 Coefficient Control */
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mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
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data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
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mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
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data = 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
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reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
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/* G3 Setting 3 */
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mask = HPIPE_G3_FFE_CAP_SEL_MASK;
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data = 0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET;
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mask |= HPIPE_G3_FFE_RES_SEL_MASK;
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data |= 0x4 << HPIPE_G3_FFE_RES_SEL_OFFSET;
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mask |= HPIPE_G3_FFE_SETTING_FORCE_MASK;
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data |= 0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET;
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mask |= HPIPE_G3_FFE_DEG_RES_LEVEL_MASK;
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data |= 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET;
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mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK;
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data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
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reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
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/* G3 Setting 4 */
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mask = HPIPE_G3_DFE_RES_MASK;
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data = 0x2 << HPIPE_G3_DFE_RES_OFFSET;
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reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
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/* Offset Phase Control */
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mask = HPIPE_OS_PH_OFFSET_MASK;
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data = 0x5c << HPIPE_OS_PH_OFFSET_OFFSET;
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mask |= HPIPE_OS_PH_OFFSET_FORCE_MASK;
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data |= 0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET;
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reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
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mask = HPIPE_OS_PH_VALID_MASK;
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data = 0x1 << HPIPE_OS_PH_VALID_OFFSET;
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reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
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mask = HPIPE_OS_PH_VALID_MASK;
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data = 0x0 << HPIPE_OS_PH_VALID_OFFSET;
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reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
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/* Set G1 TX amplitude and TX post emphasis value */
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mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK;
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data = 0x8 << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET;
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mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK;
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data |= 0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET;
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mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK;
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data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET;
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mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK;
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data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET;
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reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask);
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/* Set G2 TX amplitude and TX post emphasis value */
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mask = HPIPE_G2_SET_0_G2_TX_AMP_MASK;
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data = 0xa << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET;
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mask |= HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK;
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data |= 0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET;
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mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_MASK;
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data |= 0x2 << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET;
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mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK;
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data |= 0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET;
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reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask);
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/* Set G3 TX amplitude and TX post emphasis value */
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mask = HPIPE_G3_SET_0_G3_TX_AMP_MASK;
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data = 0xe << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET;
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mask |= HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK;
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data |= 0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET;
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mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_MASK;
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data |= 0x6 << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET;
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mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK;
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data |= 0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET;
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mask |= HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK;
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data |= 0x4 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET;
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mask |= HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK;
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data |= 0x0 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET;
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reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask);
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/* SERDES External Configuration 2 register */
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mask = SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK;
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data = 0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET;
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reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask);
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/* DFE reset sequence */
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reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
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@ -49,6 +49,9 @@
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#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4
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#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \
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(0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET)
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#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7
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#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \
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(0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET)
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#define SD_EXTERNAL_STATUS0_REG 0x18
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#define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2
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@ -105,9 +108,15 @@
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#define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1
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#define HPIPE_G1_SET_0_G1_TX_AMP_MASK \
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(0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET)
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#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET 6
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#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK \
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(0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET)
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#define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7
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#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \
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(0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)
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#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET 11
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#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK \
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(0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET)
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#define HPIPE_G1_SET_1_REG 0x038
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#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0
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@ -116,22 +125,96 @@
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#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3
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#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \
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(0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET)
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#define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6
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#define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \
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(0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET)
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#define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8
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#define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK \
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(0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET)
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#define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10
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#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \
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(0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)
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#define HPIPE_G2_SETTINGS_1_REG 0x040
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#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET 11
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#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK \
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(0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET)
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#define HPIPE_G3_SETTINGS_1_REG 0x048
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#define HPIPE_G3_RX_SELMUPI_OFFSET 0
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#define HPIPE_G3_RX_SELMUPI_MASK \
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(0x7 << HPIPE_G3_RX_SELMUPI_OFFSET)
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#define HPIPE_G3_RX_SELMUPF_OFFSET 3
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#define HPIPE_G3_RX_SELMUPF_MASK \
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(0x7 << HPIPE_G3_RX_SELMUPF_OFFSET)
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#define HPIPE_G3_SETTING_BIT_OFFSET 13
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#define HPIPE_G3_SETTING_BIT_MASK \
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(0x1 << HPIPE_G3_SETTING_BIT_OFFSET)
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#define HPIPE_G2_SET_0_REG 0x3c
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#define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET 1
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#define HPIPE_G2_SET_0_G2_TX_AMP_MASK \
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(0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET)
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#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET 6
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#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK \
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(0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET)
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#define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET 7
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#define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK \
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(0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET)
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#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET 11
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#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK \
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(0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET)
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#define HPIPE_G2_SET_1_REG 0x040
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#define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0
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#define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \
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(0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET)
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#define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3
|
||||
#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \
|
||||
(0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET)
|
||||
#define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6
|
||||
#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \
|
||||
(0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET)
|
||||
#define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8
|
||||
#define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK \
|
||||
(0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET)
|
||||
#define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET 10
|
||||
#define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK \
|
||||
(0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET)
|
||||
#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET 11
|
||||
#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK \
|
||||
(0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET)
|
||||
|
||||
#define HPIPE_G3_SET_0_REG 0x44
|
||||
#define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET 1
|
||||
#define HPIPE_G3_SET_0_G3_TX_AMP_MASK \
|
||||
(0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET)
|
||||
#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET 6
|
||||
#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK \
|
||||
(0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET)
|
||||
#define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET 7
|
||||
#define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK \
|
||||
(0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET)
|
||||
#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET 11
|
||||
#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK \
|
||||
(0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET)
|
||||
#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12
|
||||
#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK \
|
||||
(0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET)
|
||||
#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15
|
||||
#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK \
|
||||
(0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET)
|
||||
|
||||
#define HPIPE_G3_SET_1_REG 0x048
|
||||
#define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0
|
||||
#define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK \
|
||||
(0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET)
|
||||
#define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET 3
|
||||
#define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK \
|
||||
(0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET)
|
||||
#define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET 6
|
||||
#define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK \
|
||||
(0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET)
|
||||
#define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET 8
|
||||
#define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK \
|
||||
(0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET)
|
||||
#define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET 10
|
||||
#define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK \
|
||||
(0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET)
|
||||
#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET 11
|
||||
#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK \
|
||||
(0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET)
|
||||
#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET 13
|
||||
#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \
|
||||
(0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET)
|
||||
|
||||
#define HPIPE_LOOPBACK_REG 0x08c
|
||||
#define HPIPE_LOOPBACK_SEL_OFFSET 1
|
||||
@ -166,6 +249,11 @@
|
||||
|
||||
#define HPIPE_VTHIMPCAL_CTRL_REG 0x104
|
||||
|
||||
#define HPIPE_VDD_CAL_CTRL_REG 0x114
|
||||
#define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5
|
||||
#define HPIPE_EXT_SELLV_RXSAMPL_MASK \
|
||||
(0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET)
|
||||
|
||||
#define HPIPE_PCIE_REG0 0x120
|
||||
#define HPIPE_PCIE_IDLE_SYNC_OFFSET 12
|
||||
#define HPIPE_PCIE_IDLE_SYNC_MASK \
|
||||
@ -227,12 +315,39 @@
|
||||
#define HPIPE_TX_REG1_SLC_EN_MASK \
|
||||
(0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
|
||||
|
||||
#define HPIPE_PWR_CTR_DTL_REG 0x184
|
||||
#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2
|
||||
#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \
|
||||
#define HPIPE_PWR_CTR_DTL_REG 0x184
|
||||
#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0
|
||||
#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK \
|
||||
(0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET)
|
||||
#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1
|
||||
#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK \
|
||||
(0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET)
|
||||
#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2
|
||||
#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \
|
||||
(0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)
|
||||
#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4
|
||||
#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK \
|
||||
(0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET)
|
||||
#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10
|
||||
#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK \
|
||||
(0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET)
|
||||
#define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12
|
||||
#define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK \
|
||||
(0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET)
|
||||
#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14
|
||||
#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK \
|
||||
(1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET)
|
||||
|
||||
#define HPIPE_RX_REG3 0x188
|
||||
#define HPIPE_PHASE_CONTROL_REG 0x188
|
||||
#define HPIPE_OS_PH_OFFSET_OFFSET 0
|
||||
#define HPIPE_OS_PH_OFFSET_MASK \
|
||||
(0x7f << HPIPE_OS_PH_OFFSET_OFFSET)
|
||||
#define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7
|
||||
#define HPIPE_OS_PH_OFFSET_FORCE_MASK \
|
||||
(0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET)
|
||||
#define HPIPE_OS_PH_VALID_OFFSET 8
|
||||
#define HPIPE_OS_PH_VALID_MASK \
|
||||
(0x1 << HPIPE_OS_PH_VALID_OFFSET)
|
||||
|
||||
#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268
|
||||
#define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15
|
||||
@ -291,10 +406,25 @@
|
||||
#define HPIPE_TX_SWEEP_PRESET_EN_MASK \
|
||||
(0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
|
||||
|
||||
#define HPIPE_G1_SETTINGS_3_REG 0x440
|
||||
#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9
|
||||
#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \
|
||||
#define HPIPE_G1_SETTINGS_3_REG 0x440
|
||||
#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0
|
||||
#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK \
|
||||
(0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET)
|
||||
#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET 4
|
||||
#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK \
|
||||
(0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET)
|
||||
#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET 7
|
||||
#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK \
|
||||
(0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET)
|
||||
#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9
|
||||
#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \
|
||||
(0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET)
|
||||
#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET 12
|
||||
#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK \
|
||||
(0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET)
|
||||
#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET 14
|
||||
#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK \
|
||||
(0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET)
|
||||
|
||||
#define HPIPE_G1_SETTINGS_4_REG 0x444
|
||||
#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8
|
||||
@ -305,6 +435,15 @@
|
||||
#define HPIPE_G2_SETTINGS_4_REG 0x44C
|
||||
|
||||
#define HPIPE_G3_SETTING_3_REG 0x450
|
||||
#define HPIPE_G3_FFE_CAP_SEL_OFFSET 0
|
||||
#define HPIPE_G3_FFE_CAP_SEL_MASK \
|
||||
(0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET)
|
||||
#define HPIPE_G3_FFE_RES_SEL_OFFSET 4
|
||||
#define HPIPE_G3_FFE_RES_SEL_MASK \
|
||||
(0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET)
|
||||
#define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7
|
||||
#define HPIPE_G3_FFE_SETTING_FORCE_MASK \
|
||||
(0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET)
|
||||
#define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12
|
||||
#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \
|
||||
(0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user