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riscv: Introduce CONFIG_XIP to support booting from flash
When U-Boot boots from flash, during the boot process, hart_lottery and available_harts_lock variable addresses point to flash which is not writable. This causes boot failures on AE350. Introduce a config option CONFIG_XIP to support such configuration. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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@ -162,6 +162,13 @@ config SBI_IPI
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default y if RISCV_SMODE
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default y if RISCV_SMODE
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depends on SMP
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depends on SMP
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config XIP
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bool "XIP mode"
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help
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XIP (eXecute In Place) is a method for executing code directly
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from a NOR flash memory without copying the code to ram.
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Say yes here if U-Boot boots from flash directly.
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config STACK_SIZE_SHIFT
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config STACK_SIZE_SHIFT
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int
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int
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default 13
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default 13
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@ -16,6 +16,7 @@
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* before the bss section is available.
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* before the bss section is available.
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*/
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*/
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phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
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phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
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#ifndef CONFIG_XIP
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u32 hart_lottery __attribute__((section(".data"))) = 0;
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u32 hart_lottery __attribute__((section(".data"))) = 0;
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/*
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/*
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@ -23,6 +24,7 @@ u32 hart_lottery __attribute__((section(".data"))) = 0;
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* finished initialization of global data.
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* finished initialization of global data.
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*/
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*/
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u32 available_harts_lock = 1;
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u32 available_harts_lock = 1;
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#endif
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static inline bool supports_extension(char ext)
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static inline bool supports_extension(char ext)
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{
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{
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@ -98,6 +98,7 @@ call_board_init_f_0:
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mv sp, a0
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mv sp, a0
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#endif
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#endif
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#ifndef CONFIG_XIP
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/*
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/*
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* Pick hart to initialize global data and run U-Boot. The other harts
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* Pick hart to initialize global data and run U-Boot. The other harts
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* wait for initialization to complete.
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* wait for initialization to complete.
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@ -106,6 +107,9 @@ call_board_init_f_0:
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li s2, 1
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li s2, 1
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amoswap.w s2, t1, 0(t0)
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amoswap.w s2, t1, 0(t0)
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bnez s2, wait_for_gd_init
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bnez s2, wait_for_gd_init
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#else
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bnez tp, secondary_hart_loop
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#endif
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la t0, prior_stage_fdt_address
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la t0, prior_stage_fdt_address
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SREG s1, 0(t0)
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SREG s1, 0(t0)
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@ -115,6 +119,7 @@ call_board_init_f_0:
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/* save the boot hart id to global_data */
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/* save the boot hart id to global_data */
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SREG tp, GD_BOOT_HART(gp)
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SREG tp, GD_BOOT_HART(gp)
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#ifndef CONFIG_XIP
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la t0, available_harts_lock
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la t0, available_harts_lock
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fence rw, w
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fence rw, w
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amoswap.w zero, zero, 0(t0)
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amoswap.w zero, zero, 0(t0)
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@ -141,6 +146,7 @@ wait_for_gd_init:
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* secondary_hart_loop.
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* secondary_hart_loop.
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*/
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*/
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bnez s2, secondary_hart_loop
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bnez s2, secondary_hart_loop
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#endif
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/* Enable cache */
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/* Enable cache */
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jal icache_enable
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jal icache_enable
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@ -27,7 +27,9 @@ struct arch_global_data {
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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struct ipi_data ipi[CONFIG_NR_CPUS];
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struct ipi_data ipi[CONFIG_NR_CPUS];
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#endif
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#endif
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#ifndef CONFIG_XIP
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ulong available_harts;
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ulong available_harts;
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#endif
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};
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};
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#include <asm-generic/global_data.h>
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#include <asm-generic/global_data.h>
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@ -14,7 +14,9 @@
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int main(void)
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int main(void)
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{
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{
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DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
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DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
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#ifndef CONFIG_XIP
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DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
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DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
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#endif
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return 0;
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return 0;
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}
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}
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@ -63,9 +63,11 @@ static int send_ipi_many(struct ipi_data *ipi)
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continue;
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continue;
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}
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}
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#ifndef CONFIG_XIP
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/* skip if hart is not available */
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/* skip if hart is not available */
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if (!(gd->arch.available_harts & (1 << reg)))
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if (!(gd->arch.available_harts & (1 << reg)))
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continue;
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continue;
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#endif
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gd->arch.ipi[reg].addr = ipi->addr;
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gd->arch.ipi[reg].addr = ipi->addr;
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gd->arch.ipi[reg].arg0 = ipi->arg0;
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gd->arch.ipi[reg].arg0 = ipi->arg0;
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