mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
riscv: Introduce CONFIG_XIP to support booting from flash
When U-Boot boots from flash, during the boot process, hart_lottery and available_harts_lock variable addresses point to flash which is not writable. This causes boot failures on AE350. Introduce a config option CONFIG_XIP to support such configuration. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
parent
8aa278df0a
commit
bdce38965e
|
@ -162,6 +162,13 @@ config SBI_IPI
|
|||
default y if RISCV_SMODE
|
||||
depends on SMP
|
||||
|
||||
config XIP
|
||||
bool "XIP mode"
|
||||
help
|
||||
XIP (eXecute In Place) is a method for executing code directly
|
||||
from a NOR flash memory without copying the code to ram.
|
||||
Say yes here if U-Boot boots from flash directly.
|
||||
|
||||
config STACK_SIZE_SHIFT
|
||||
int
|
||||
default 13
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
* before the bss section is available.
|
||||
*/
|
||||
phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
|
||||
#ifndef CONFIG_XIP
|
||||
u32 hart_lottery __attribute__((section(".data"))) = 0;
|
||||
|
||||
/*
|
||||
|
@ -23,6 +24,7 @@ u32 hart_lottery __attribute__((section(".data"))) = 0;
|
|||
* finished initialization of global data.
|
||||
*/
|
||||
u32 available_harts_lock = 1;
|
||||
#endif
|
||||
|
||||
static inline bool supports_extension(char ext)
|
||||
{
|
||||
|
|
|
@ -98,6 +98,7 @@ call_board_init_f_0:
|
|||
mv sp, a0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_XIP
|
||||
/*
|
||||
* Pick hart to initialize global data and run U-Boot. The other harts
|
||||
* wait for initialization to complete.
|
||||
|
@ -106,6 +107,9 @@ call_board_init_f_0:
|
|||
li s2, 1
|
||||
amoswap.w s2, t1, 0(t0)
|
||||
bnez s2, wait_for_gd_init
|
||||
#else
|
||||
bnez tp, secondary_hart_loop
|
||||
#endif
|
||||
|
||||
la t0, prior_stage_fdt_address
|
||||
SREG s1, 0(t0)
|
||||
|
@ -115,6 +119,7 @@ call_board_init_f_0:
|
|||
/* save the boot hart id to global_data */
|
||||
SREG tp, GD_BOOT_HART(gp)
|
||||
|
||||
#ifndef CONFIG_XIP
|
||||
la t0, available_harts_lock
|
||||
fence rw, w
|
||||
amoswap.w zero, zero, 0(t0)
|
||||
|
@ -141,6 +146,7 @@ wait_for_gd_init:
|
|||
* secondary_hart_loop.
|
||||
*/
|
||||
bnez s2, secondary_hart_loop
|
||||
#endif
|
||||
|
||||
/* Enable cache */
|
||||
jal icache_enable
|
||||
|
|
|
@ -27,7 +27,9 @@ struct arch_global_data {
|
|||
#ifdef CONFIG_SMP
|
||||
struct ipi_data ipi[CONFIG_NR_CPUS];
|
||||
#endif
|
||||
#ifndef CONFIG_XIP
|
||||
ulong available_harts;
|
||||
#endif
|
||||
};
|
||||
|
||||
#include <asm-generic/global_data.h>
|
||||
|
|
|
@ -14,7 +14,9 @@
|
|||
int main(void)
|
||||
{
|
||||
DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
|
||||
#ifndef CONFIG_XIP
|
||||
DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -63,9 +63,11 @@ static int send_ipi_many(struct ipi_data *ipi)
|
|||
continue;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_XIP
|
||||
/* skip if hart is not available */
|
||||
if (!(gd->arch.available_harts & (1 << reg)))
|
||||
continue;
|
||||
#endif
|
||||
|
||||
gd->arch.ipi[reg].addr = ipi->addr;
|
||||
gd->arch.ipi[reg].arg0 = ipi->arg0;
|
||||
|
|
Loading…
Reference in New Issue
Block a user