mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-27 23:20:26 +09:00
Merge tag 'ti-v2021.01-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti into next
- Hyperflash boot for J7200 - Update Main R5FSS lockstep mode - R5F remoteproc support for J7200 - Minor env fixes - Add SPI boot support for am335x-icev2
This commit is contained in:
Tom Rini
commit
bd4e8944cf
@ -436,3 +436,53 @@
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reg = <3>;
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};
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};
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&spi0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_pins_default>;
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sn65hvs882@1 {
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compatible = "pisosr-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
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reg = <1>;
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spi-max-frequency = <1000000>;
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spi-cpol;
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};
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spi_nor: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "winbond,w25q64", "jedec,spi-nor";
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spi-max-frequency = <80000000>;
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m25p,fast-read;
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reg = <0>;
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partition@0 {
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label = "u-boot-spl";
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reg = <0x0 0x80000>;
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read-only;
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};
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partition@1 {
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label = "u-boot";
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reg = <0x80000 0x100000>;
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read-only;
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};
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partition@2 {
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label = "u-boot-env";
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reg = <0x180000 0x20000>;
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read-only;
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};
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partition@3 {
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label = "misc";
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reg = <0x1A0000 0x660000>;
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};
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};
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};
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@ -131,3 +131,31 @@
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dr_mode = "peripheral";
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u-boot,dm-spl;
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};
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&wkup_gpio_pins_default {
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u-boot,dm-spl;
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};
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&wkup_gpio0 {
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u-boot,dm-spl;
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};
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&mcu_fss0_hpb0_pins_default {
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u-boot,dm-spl;
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};
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&fss {
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u-boot,dm-spl;
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};
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&hbmc {
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u-boot,dm-spl;
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flash@0,0 {
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u-boot,dm-spl;
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};
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};
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&hbmc_mux {
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u-boot,dm-spl;
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};
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@ -13,6 +13,13 @@
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stdout-path = "serial2:115200n8";
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bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
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};
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aliases {
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remoteproc0 = &mcu_r5fss0_core0;
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remoteproc1 = &mcu_r5fss0_core1;
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remoteproc2 = &main_r5fss0_core0;
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remoteproc3 = &main_r5fss0_core1;
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};
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};
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&wkup_pmx0 {
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@ -340,4 +340,44 @@
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dr_mode = "otg";
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};
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};
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main_r5fss0: r5fss@5c00000 {
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compatible = "ti,j7200-r5fss";
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lockstep-mode = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
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<0x5d00000 0x00 0x5d00000 0x20000>;
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power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
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main_r5fss0_core0: r5f@5c00000 {
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compatible = "ti,j7200-r5f";
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reg = <0x5c00000 0x00010000>,
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<0x5c10000 0x00010000>;
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reg-names = "atcm", "btcm";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <245>;
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ti,sci-proc-ids = <0x06 0xFF>;
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resets = <&k3_reset 245 1>;
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firmware-name = "j7200-main-r5f0_0-fw";
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atcm-enable = <1>;
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btcm-enable = <1>;
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loczrama = <1>;
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};
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main_r5fss0_core1: r5f@5d00000 {
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compatible = "ti,j7200-r5f";
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reg = <0x5d00000 0x00008000>,
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<0x5d10000 0x00008000>;
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reg-names = "atcm", "btcm";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <246>;
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ti,sci-proc-ids = <0x07 0xFF>;
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resets = <&k3_reset 246 1>;
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firmware-name = "j7200-main-r5f0_1-fw";
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atcm-enable = <1>;
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btcm-enable = <1>;
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loczrama = <1>;
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};
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};
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};
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@ -269,4 +269,44 @@
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ti,cpts-periodic-outputs = <2>;
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};
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};
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mcu_r5fss0: r5fss@41000000 {
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compatible = "ti,j7200-r5fss";
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lockstep-mode = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x41000000 0x00 0x41000000 0x20000>,
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<0x41400000 0x00 0x41400000 0x20000>;
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power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
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mcu_r5fss0_core0: r5f@41000000 {
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compatible = "ti,j7200-r5f";
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reg = <0x41000000 0x00010000>,
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<0x41010000 0x00010000>;
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reg-names = "atcm", "btcm";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <250>;
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ti,sci-proc-ids = <0x01 0xff>;
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resets = <&k3_reset 250 1>;
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firmware-name = "j7200-mcu-r5f0_0-fw";
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atcm-enable = <1>;
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btcm-enable = <1>;
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loczrama = <1>;
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};
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mcu_r5fss0_core1: r5f@41400000 {
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compatible = "ti,j7200-r5f";
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reg = <0x41400000 0x00008000>,
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<0x41410000 0x00008000>;
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reg-names = "atcm", "btcm";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <251>;
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ti,sci-proc-ids = <0x02 0xff>;
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resets = <&k3_reset 251 1>;
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firmware-name = "j7200-mcu-r5f0_1-fw";
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atcm-enable = <1>;
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btcm-enable = <1>;
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loczrama = <1>;
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};
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};
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};
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@ -18,6 +18,12 @@
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chosen {
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stdout-path = &main_uart0;
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tick-timer = &timer1;
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firmware-loader = &fs_loader0;
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};
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fs_loader0: fs_loader@0 {
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u-boot,dm-pre-reloc;
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compatible = "u-boot,fs-loader";
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};
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a72_0: a72@0 {
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@ -107,6 +113,31 @@
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J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
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>;
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};
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mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
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J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
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J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
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J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
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J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
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J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
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J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
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J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
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J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
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J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
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J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
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J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
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J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
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J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
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>;
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};
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wkup_gpio_pins_default: wkup-gpio-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
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>;
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};
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};
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&main_pmx0 {
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@ -214,4 +245,19 @@
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maximum-speed = "high-speed";
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};
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&hbmc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
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reg = <0x0 0x47040000 0x0 0x100>,
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<0x0 0x50000000 0x0 0x8000000>;
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ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */
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<0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */
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flash@0,0 {
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compatible = "cypress,hyperflash", "cfi-flash";
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reg = <0x0 0x0 0x4000000>;
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};
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};
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#include "k3-j7200-common-proc-board-u-boot.dtsi"
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@ -302,7 +302,7 @@
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main_r5fss1: r5fss@5e00000 {
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compatible = "ti,j721e-r5fss";
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lockstep-mode = <1>;
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lockstep-mode = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
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@ -2,8 +2,9 @@
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/*
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* K3: ARM64 MMU setup
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*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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* Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
|
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* Lokesh Vutla <lokeshvutla@ti.com>
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* Suman Anna <s-anna@ti.com>
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* (This file is derived from arch/arm/mach-zynqmp/cpu.c)
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*
|
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*/
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@ -66,6 +67,8 @@ struct mm_region *mem_map = am654_mem_map;
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#endif /* CONFIG_SOC_K3_AM6 */
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#ifdef CONFIG_SOC_K3_J721E
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#ifdef CONFIG_TARGET_J721E_A72_EVM
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/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
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#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6)
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|
||||
@ -122,4 +125,58 @@ struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
|
||||
};
|
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|
||||
struct mm_region *mem_map = j721e_mem_map;
|
||||
#endif /* CONFIG_TARGET_J721E_A72_EVM */
|
||||
|
||||
#ifdef CONFIG_TARGET_J7200_A72_EVM
|
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#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
|
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|
||||
/* ToDo: Add 64bit IO */
|
||||
struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
|
||||
{
|
||||
.virt = 0x0UL,
|
||||
.phys = 0x0UL,
|
||||
.size = 0x80000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
.virt = 0x80000000UL,
|
||||
.phys = 0x80000000UL,
|
||||
.size = 0x20000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
}, {
|
||||
.virt = 0xa0000000UL,
|
||||
.phys = 0xa0000000UL,
|
||||
.size = 0x04800000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
|
||||
PTE_BLOCK_NON_SHARE
|
||||
}, {
|
||||
.virt = 0xa4800000UL,
|
||||
.phys = 0xa4800000UL,
|
||||
.size = 0x5b800000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
}, {
|
||||
.virt = 0x880000000UL,
|
||||
.phys = 0x880000000UL,
|
||||
.size = 0x80000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
}, {
|
||||
.virt = 0x500000000UL,
|
||||
.phys = 0x500000000UL,
|
||||
.size = 0x400000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
/* List terminator */
|
||||
0,
|
||||
}
|
||||
};
|
||||
|
||||
struct mm_region *mem_map = j7200_mem_map;
|
||||
#endif /* CONFIG_TARGET_J7200_A72_EVM */
|
||||
|
||||
#endif /* CONFIG_SOC_K3_J721E */
|
||||
|
||||
@ -15,6 +15,7 @@
|
||||
#define BOOT_DEVICE_ETHERNET 0x04
|
||||
#define BOOT_DEVICE_I2C 0x06
|
||||
#define BOOT_DEVICE_UART 0x07
|
||||
#define BOOT_DEVICE_NOR BOOT_DEVICE_HYPERFLASH
|
||||
|
||||
/* With BootMode B = 1 */
|
||||
#define BOOT_DEVICE_MMC2 0x10
|
||||
|
||||
@ -14,6 +14,7 @@
|
||||
#include <init.h>
|
||||
#include <net.h>
|
||||
#include <ns16550.h>
|
||||
#include <omap3_spi.h>
|
||||
#include <spl.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
@ -49,6 +50,12 @@
|
||||
#define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC
|
||||
#define AM43XX_RDWRLVLFULL_START 0x80000000
|
||||
|
||||
/* SPI flash. */
|
||||
#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
|
||||
#define AM33XX_SPI0_BASE 0x48030000
|
||||
#define AM33XX_SPI0_OFFSET (AM33XX_SPI0_BASE + OMAP4_MCSPI_REG_OFFSET)
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int dram_init(void)
|
||||
@ -142,6 +149,17 @@ U_BOOT_DEVICES(am33xx_gpios) = {
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
|
||||
static const struct omap3_spi_plat omap3_spi_pdata = {
|
||||
.regs = (struct mcspi *)AM33XX_SPI0_OFFSET,
|
||||
.pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
|
||||
};
|
||||
|
||||
U_BOOT_DEVICE(am33xx_spi) = {
|
||||
.name = "omap3_spi",
|
||||
.platdata = &omap3_spi_pdata,
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if !CONFIG_IS_ENABLED(DM_GPIO)
|
||||
|
||||
@ -5,3 +5,4 @@ F: board/ti/am335x/
|
||||
F: include/configs/am335x_evm.h
|
||||
F: configs/am335x_boneblack_vboot_defconfig
|
||||
F: configs/am335x_evm_defconfig
|
||||
F: configs/am335x_evm_spiboot_defconfig
|
||||
|
||||
@ -117,6 +117,13 @@ static void __maybe_unused detect_enable_hyperflash(void *blob)
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TARGET_J7200_A72_EVM)
|
||||
void spl_perform_fixups(struct spl_image_info *spl_image)
|
||||
{
|
||||
detect_enable_hyperflash(spl_image->fdt_addr);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
||||
{
|
||||
|
||||
93
configs/am335x_evm_spiboot_defconfig
Normal file
93
configs/am335x_evm_spiboot_defconfig
Normal file
@ -0,0 +1,93 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_OMAP2PLUS=y
|
||||
CONFIG_TI_COMMON_CMD_OPTIONS=y
|
||||
CONFIG_ENV_OFFSET=0x100000
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
|
||||
CONFIG_SPL_DM_SPI=y
|
||||
CONFIG_AM33XX=y
|
||||
# CONFIG_SPL_MMC_SUPPORT is not set
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
|
||||
CONFIG_LOGLEVEL=3
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_ARCH_MISC_INIT=y
|
||||
CONFIG_SPL_FIT_IMAGE_TINY=y
|
||||
# CONFIG_SPL_FS_EXT4 is not set
|
||||
CONFIG_SPL_MTD_SUPPORT=y
|
||||
# CONFIG_SPL_NAND_SUPPORT is not set
|
||||
CONFIG_SPL_DM_SPI_FLASH=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_CMD_SPL=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_NAND=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_BOOTP_DNS2=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle"
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
# CONFIG_ENV_IS_IN_FAT is not set
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_SPL_ENV_IS_NOWHERE=y
|
||||
CONFIG_BOOTP_SEND_HOSTNAME=y
|
||||
CONFIG_BOOTCOUNT_LIMIT=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_CLK_CDCE9XX=y
|
||||
CONFIG_DFU_TFTP=y
|
||||
CONFIG_DFU_MMC=y
|
||||
CONFIG_DFU_NAND=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=1
|
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_DM_MMC=y
|
||||
# CONFIG_SPL_DM_MMC is not set
|
||||
# CONFIG_MMC_HW_PARTITIONING is not set
|
||||
CONFIG_MMC_OMAP_HS=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
# CONFIG_SPL_NAND_AM33XX_BCH is not set
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_SPEED=24000000
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_DRIVER_TI_CPSW=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_OMAP3_SPI=y
|
||||
CONFIG_TIMER=y
|
||||
CONFIG_OMAP_TIMER=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_DM_USB_GADGET=y
|
||||
CONFIG_USB_MUSB_HOST=y
|
||||
CONFIG_USB_MUSB_GADGET=y
|
||||
CONFIG_USB_MUSB_TI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
|
||||
CONFIG_USB_ETHER=y
|
||||
CONFIG_WDT=y
|
||||
# CONFIG_SPL_WDT is not set
|
||||
CONFIG_DYNAMIC_CRC_TABLE=y
|
||||
CONFIG_RSA=y
|
||||
CONFIG_LZO=y
|
||||
# CONFIG_OF_LIBFDT_OVERLAY is not set
|
||||
@ -30,7 +30,7 @@ CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
|
||||
# CONFIG_USE_SPL_FIT_GENERATOR is not set
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
|
||||
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
@ -41,7 +41,9 @@ CONFIG_SPL_DMA=y
|
||||
CONFIG_SPL_ENV_SUPPORT=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
CONFIG_SPL_DM_MAILBOX=y
|
||||
CONFIG_SPL_MTD_SUPPORT=y
|
||||
CONFIG_SPL_DM_SPI_FLASH=y
|
||||
CONFIG_SPL_NOR_SUPPORT=y
|
||||
CONFIG_SPL_DM_RESET=y
|
||||
CONFIG_SPL_POWER_SUPPORT=y
|
||||
CONFIG_SPL_POWER_DOMAIN=y
|
||||
@ -61,6 +63,7 @@ CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_MTD=y
|
||||
CONFIG_CMD_REMOTEPROC=y
|
||||
CONFIG_CMD_UFS=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
@ -87,6 +90,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_OF_TRANSLATE=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
@ -140,6 +144,7 @@ CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_TI_SCI_POWER_DOMAIN=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_REMOTEPROC_TI_K3_R5F=y
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_RESET_TI_SCI=y
|
||||
CONFIG_SCSI=y
|
||||
|
||||
@ -1,5 +1,6 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_K3=y
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x70000
|
||||
@ -37,7 +38,9 @@ CONFIG_SPL_ENV_SUPPORT=y
|
||||
CONFIG_SPL_FS_EXT4=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
CONFIG_SPL_DM_MAILBOX=y
|
||||
CONFIG_SPL_MTD_SUPPORT=y
|
||||
CONFIG_SPL_DM_SPI_FLASH=y
|
||||
CONFIG_SPL_NOR_SUPPORT=y
|
||||
CONFIG_SPL_DM_RESET=y
|
||||
CONFIG_SPL_POWER_SUPPORT=y
|
||||
CONFIG_SPL_POWER_DOMAIN=y
|
||||
@ -67,6 +70,8 @@ CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_OF_TRANSLATE=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
@ -81,12 +86,21 @@ CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
|
||||
CONFIG_SYS_I2C_OMAP24XX=y
|
||||
CONFIG_DM_MAILBOX=y
|
||||
CONFIG_K3_SEC_PROXY=y
|
||||
CONFIG_FS_LOADER=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_SPL_MMC_SDHCI_ADMA=y
|
||||
CONFIG_MMC_SDHCI_AM654=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_CFI_FLASH=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_HBMC_AM654=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
|
||||
@ -25,6 +25,8 @@ The following are the mandatory properties:
|
||||
K3 AM65x SoCs
|
||||
"ti,j721e-r5fss" for R5F clusters/subsystems on
|
||||
K3 J721E SoCs
|
||||
"ti,j7200-r5fss" for R5F clusters/subsystems on
|
||||
K3 J7200 SoCs
|
||||
- power-domains: Should contain a phandle to a PM domain provider node
|
||||
and an args specifier containing the R5FSS device id
|
||||
value. This property is as per the binding,
|
||||
@ -56,6 +58,7 @@ The following are the mandatory properties:
|
||||
- compatible: Should be one of the following,
|
||||
"ti,am654-r5f" for the R5F cores in K3 AM65x SoCs
|
||||
"ti,j721e-r5f" for the R5F cores in K3 J721E SOCs
|
||||
"ti,j7200-r5f" for the R5F cores in K3 J7200 SOCs
|
||||
- reg: Should contain an entry for each value in 'reg-names'.
|
||||
Each entry should have the memory region's start address
|
||||
and the size of the region, the representation matching
|
||||
@ -79,7 +82,7 @@ The following are the mandatory properties:
|
||||
specifier. Please refer to the following reset bindings
|
||||
for the reset argument specifier,
|
||||
Documentation/devicetree/bindings/reset/ti,sci-reset.txt
|
||||
for AM65x and J721E SoCs
|
||||
for AM65x, J721E and J7200 SoCs
|
||||
|
||||
Optional properties:
|
||||
--------------------
|
||||
|
||||
@ -2,8 +2,9 @@
|
||||
/*
|
||||
* Texas Instruments' K3 R5 Remoteproc driver
|
||||
*
|
||||
* Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Lokesh Vutla <lokeshvutla@ti.com>
|
||||
* Suman Anna <s-anna@ti.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
@ -37,6 +38,8 @@
|
||||
#define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000
|
||||
#define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000
|
||||
#define PROC_BOOT_CFG_FLAG_GEN_IGN_BOOTVECTOR 0x10000000
|
||||
/* Available from J7200 SoCs onwards */
|
||||
#define PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS 0x00004000
|
||||
|
||||
/* R5 TI-SCI Processor Control Flags */
|
||||
#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
|
||||
@ -54,6 +57,16 @@ enum cluster_mode {
|
||||
CLUSTER_MODE_LOCKSTEP,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct k3_r5f_ip_data - internal data structure used for IP variations
|
||||
* @tcm_is_double: flag to denote the larger unified TCMs in certain modes
|
||||
* @tcm_ecc_autoinit: flag to denote the auto-initialization of TCMs for ECC
|
||||
*/
|
||||
struct k3_r5f_ip_data {
|
||||
bool tcm_is_double;
|
||||
bool tcm_ecc_autoinit;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct k3_r5_mem - internal memory structure
|
||||
* @cpu_addr: MPU virtual address of the memory region
|
||||
@ -74,6 +87,7 @@ struct k3_r5f_mem {
|
||||
* @cluster: pointer to the parent cluster.
|
||||
* @reset: reset control handle
|
||||
* @tsp: TI-SCI processor control handle
|
||||
* @ipdata: cached pointer to R5F IP specific feature data
|
||||
* @mem: Array of available internal memories
|
||||
* @num_mem: Number of available memories
|
||||
* @atcm_enable: flag to control ATCM enablement
|
||||
@ -86,6 +100,7 @@ struct k3_r5f_core {
|
||||
struct k3_r5f_cluster *cluster;
|
||||
struct reset_ctl reset;
|
||||
struct ti_sci_proc tsp;
|
||||
struct k3_r5f_ip_data *ipdata;
|
||||
struct k3_r5f_mem *mem;
|
||||
int num_mems;
|
||||
u32 atcm_enable;
|
||||
@ -257,6 +272,18 @@ static int k3_r5f_core_sanity_check(struct k3_r5f_core *core)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Zero out TCMs so that ECC can be effective on all TCM addresses */
|
||||
void k3_r5f_init_tcm_memories(struct k3_r5f_core *core, bool auto_inited)
|
||||
{
|
||||
if (core->ipdata->tcm_ecc_autoinit && auto_inited)
|
||||
return;
|
||||
|
||||
if (core->atcm_enable)
|
||||
memset(core->mem[0].cpu_addr, 0x00, core->mem[0].size);
|
||||
if (core->btcm_enable)
|
||||
memset(core->mem[1].cpu_addr, 0x00, core->mem[1].size);
|
||||
}
|
||||
|
||||
/**
|
||||
* k3_r5f_load() - Load up the Remote processor image
|
||||
* @dev: rproc device pointer
|
||||
@ -268,7 +295,9 @@ static int k3_r5f_core_sanity_check(struct k3_r5f_core *core)
|
||||
static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size)
|
||||
{
|
||||
struct k3_r5f_core *core = dev_get_priv(dev);
|
||||
u32 boot_vector;
|
||||
u64 boot_vector;
|
||||
u32 ctrl, sts, cfg = 0;
|
||||
bool mem_auto_init;
|
||||
int ret;
|
||||
|
||||
dev_dbg(dev, "%s addr = 0x%lx, size = 0x%lx\n", __func__, addr, size);
|
||||
@ -281,6 +310,12 @@ static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size)
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = ti_sci_proc_get_status(&core->tsp, &boot_vector, &cfg, &ctrl,
|
||||
&sts);
|
||||
if (ret)
|
||||
return ret;
|
||||
mem_auto_init = !(cfg & PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS);
|
||||
|
||||
ret = k3_r5f_prepare(dev);
|
||||
if (ret) {
|
||||
dev_err(dev, "R5f prepare failed for core %d\n",
|
||||
@ -288,11 +323,7 @@ static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size)
|
||||
goto proc_release;
|
||||
}
|
||||
|
||||
/* Zero out TCMs so that ECC can be effective on all TCM addresses */
|
||||
if (core->atcm_enable)
|
||||
memset(core->mem[0].cpu_addr, 0x00, core->mem[0].size);
|
||||
if (core->btcm_enable)
|
||||
memset(core->mem[1].cpu_addr, 0x00, core->mem[1].size);
|
||||
k3_r5f_init_tcm_memories(core, mem_auto_init);
|
||||
|
||||
ret = rproc_elf_load_image(dev, addr, size);
|
||||
if (ret < 0) {
|
||||
@ -302,7 +333,7 @@ static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size)
|
||||
|
||||
boot_vector = rproc_elf_get_boot_addr(dev, addr);
|
||||
|
||||
dev_dbg(dev, "%s: Boot vector = 0x%x\n", __func__, boot_vector);
|
||||
dev_dbg(dev, "%s: Boot vector = 0x%llx\n", __func__, boot_vector);
|
||||
|
||||
ret = ti_sci_proc_set_config(&core->tsp, boot_vector, 0, 0);
|
||||
|
||||
@ -657,6 +688,8 @@ static int k3_r5f_of_to_priv(struct k3_r5f_core *core)
|
||||
return ret;
|
||||
}
|
||||
|
||||
core->ipdata = (struct k3_r5f_ip_data *)dev_get_driver_data(core->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -702,6 +735,38 @@ static int k3_r5f_core_of_get_memories(struct k3_r5f_core *core)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Each R5F core within a typical R5FSS instance has a total of 64 KB of TCMs,
|
||||
* split equally into two 32 KB banks between ATCM and BTCM. The TCMs from both
|
||||
* cores are usable in Split-mode, but only the Core0 TCMs can be used in
|
||||
* LockStep-mode. The newer revisions of the R5FSS IP maximizes these TCMs by
|
||||
* leveraging the Core1 TCMs as well in certain modes where they would have
|
||||
* otherwise been unusable (Eg: LockStep-mode on J7200 SoCs). This is done by
|
||||
* making a Core1 TCM visible immediately after the corresponding Core0 TCM.
|
||||
* The SoC memory map uses the larger 64 KB sizes for the Core0 TCMs, and the
|
||||
* dts representation reflects this increased size on supported SoCs. The Core0
|
||||
* TCM sizes therefore have to be adjusted to only half the original size in
|
||||
* Split mode.
|
||||
*/
|
||||
static void k3_r5f_core_adjust_tcm_sizes(struct k3_r5f_core *core)
|
||||
{
|
||||
struct k3_r5f_cluster *cluster = core->cluster;
|
||||
|
||||
if (cluster->mode == CLUSTER_MODE_LOCKSTEP)
|
||||
return;
|
||||
|
||||
if (!core->ipdata->tcm_is_double)
|
||||
return;
|
||||
|
||||
if (core == cluster->cores[0]) {
|
||||
core->mem[0].size /= 2;
|
||||
core->mem[1].size /= 2;
|
||||
|
||||
dev_dbg(core->dev, "adjusted TCM sizes, ATCM = 0x%zx BTCM = 0x%zx\n",
|
||||
core->mem[0].size, core->mem[1].size);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* k3_r5f_probe() - Basic probe
|
||||
* @dev: corresponding k3 remote processor device
|
||||
@ -755,6 +820,8 @@ static int k3_r5f_probe(struct udevice *dev)
|
||||
return ret;
|
||||
}
|
||||
|
||||
k3_r5f_core_adjust_tcm_sizes(core);
|
||||
|
||||
dev_dbg(dev, "Remoteproc successfully probed\n");
|
||||
|
||||
return 0;
|
||||
@ -771,9 +838,20 @@ static int k3_r5f_remove(struct udevice *dev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct k3_r5f_ip_data k3_data = {
|
||||
.tcm_is_double = false,
|
||||
.tcm_ecc_autoinit = false,
|
||||
};
|
||||
|
||||
static const struct k3_r5f_ip_data j7200_data = {
|
||||
.tcm_is_double = true,
|
||||
.tcm_ecc_autoinit = true,
|
||||
};
|
||||
|
||||
static const struct udevice_id k3_r5f_rproc_ids[] = {
|
||||
{ .compatible = "ti,am654-r5f"},
|
||||
{ .compatible = "ti,j721e-r5f"},
|
||||
{ .compatible = "ti,am654-r5f", .data = (ulong)&k3_data, },
|
||||
{ .compatible = "ti,j721e-r5f", .data = (ulong)&k3_data, },
|
||||
{ .compatible = "ti,j7200-r5f", .data = (ulong)&j7200_data, },
|
||||
{}
|
||||
};
|
||||
|
||||
@ -810,6 +888,7 @@ static int k3_r5f_cluster_probe(struct udevice *dev)
|
||||
static const struct udevice_id k3_r5fss_ids[] = {
|
||||
{ .compatible = "ti,am654-r5fss"},
|
||||
{ .compatible = "ti,j721e-r5fss"},
|
||||
{ .compatible = "ti,j7200-r5fss"},
|
||||
{}
|
||||
};
|
||||
|
||||
|
||||
@ -22,82 +22,14 @@
|
||||
#include <malloc.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <omap3_spi.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define OMAP4_MCSPI_REG_OFFSET 0x100
|
||||
|
||||
struct omap2_mcspi_platform_config {
|
||||
unsigned int regs_offset;
|
||||
};
|
||||
|
||||
/* per-register bitmasks */
|
||||
#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
|
||||
#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
|
||||
#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
|
||||
#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
|
||||
|
||||
#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
|
||||
|
||||
#define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0)
|
||||
#define OMAP3_MCSPI_MODULCTRL_MS BIT(2)
|
||||
#define OMAP3_MCSPI_MODULCTRL_STEST BIT(3)
|
||||
|
||||
#define OMAP3_MCSPI_CHCONF_PHA BIT(0)
|
||||
#define OMAP3_MCSPI_CHCONF_POL BIT(1)
|
||||
#define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2)
|
||||
#define OMAP3_MCSPI_CHCONF_EPOL BIT(6)
|
||||
#define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7)
|
||||
#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
|
||||
#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
|
||||
#define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12)
|
||||
#define OMAP3_MCSPI_CHCONF_DMAW BIT(14)
|
||||
#define OMAP3_MCSPI_CHCONF_DMAR BIT(15)
|
||||
#define OMAP3_MCSPI_CHCONF_DPE0 BIT(16)
|
||||
#define OMAP3_MCSPI_CHCONF_DPE1 BIT(17)
|
||||
#define OMAP3_MCSPI_CHCONF_IS BIT(18)
|
||||
#define OMAP3_MCSPI_CHCONF_TURBO BIT(19)
|
||||
#define OMAP3_MCSPI_CHCONF_FORCE BIT(20)
|
||||
|
||||
#define OMAP3_MCSPI_CHSTAT_RXS BIT(0)
|
||||
#define OMAP3_MCSPI_CHSTAT_TXS BIT(1)
|
||||
#define OMAP3_MCSPI_CHSTAT_EOT BIT(2)
|
||||
|
||||
#define OMAP3_MCSPI_CHCTRL_EN BIT(0)
|
||||
#define OMAP3_MCSPI_CHCTRL_DIS (0 << 0)
|
||||
|
||||
#define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0)
|
||||
#define MCSPI_PINDIR_D0_IN_D1_OUT 0
|
||||
#define MCSPI_PINDIR_D0_OUT_D1_IN 1
|
||||
|
||||
#define OMAP3_MCSPI_MAX_FREQ 48000000
|
||||
#define SPI_WAIT_TIMEOUT 10
|
||||
|
||||
/* OMAP3 McSPI registers */
|
||||
struct mcspi_channel {
|
||||
unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */
|
||||
unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */
|
||||
unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */
|
||||
unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */
|
||||
unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */
|
||||
};
|
||||
|
||||
struct mcspi {
|
||||
unsigned char res1[0x10];
|
||||
unsigned int sysconfig; /* 0x10 */
|
||||
unsigned int sysstatus; /* 0x14 */
|
||||
unsigned int irqstatus; /* 0x18 */
|
||||
unsigned int irqenable; /* 0x1C */
|
||||
unsigned int wakeupenable; /* 0x20 */
|
||||
unsigned int syst; /* 0x24 */
|
||||
unsigned int modulctrl; /* 0x28 */
|
||||
struct mcspi_channel channel[4];
|
||||
/* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
|
||||
/* channel1: 0x40 - 0x50, bus 0 & 1 */
|
||||
/* channel2: 0x54 - 0x64, bus 0 & 1 */
|
||||
/* channel3: 0x68 - 0x78, bus 0 */
|
||||
};
|
||||
|
||||
struct omap3_spi_priv {
|
||||
struct mcspi *regs;
|
||||
unsigned int cs;
|
||||
@ -482,17 +414,10 @@ static int omap3_spi_set_wordlen(struct udevice *dev, unsigned int wordlen)
|
||||
static int omap3_spi_probe(struct udevice *dev)
|
||||
{
|
||||
struct omap3_spi_priv *priv = dev_get_priv(dev);
|
||||
const void *blob = gd->fdt_blob;
|
||||
int node = dev_of_offset(dev);
|
||||
struct omap3_spi_plat *plat = dev_get_platdata(dev);
|
||||
|
||||
struct omap2_mcspi_platform_config* data =
|
||||
(struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
|
||||
|
||||
priv->regs = (struct mcspi *)(dev_read_addr(dev) + data->regs_offset);
|
||||
if (fdtdec_get_bool(blob, node, "ti,pindir-d0-out-d1-in"))
|
||||
priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
|
||||
else
|
||||
priv->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
|
||||
priv->regs = plat->regs;
|
||||
priv->pin_dir = plat->pin_dir;
|
||||
priv->wordlen = SPI_DEFAULT_WORDLEN;
|
||||
|
||||
spi_reset(priv->regs);
|
||||
@ -544,6 +469,7 @@ static const struct dm_spi_ops omap3_spi_ops = {
|
||||
*/
|
||||
};
|
||||
|
||||
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
static struct omap2_mcspi_platform_config omap2_pdata = {
|
||||
.regs_offset = 0,
|
||||
};
|
||||
@ -552,16 +478,37 @@ static struct omap2_mcspi_platform_config omap4_pdata = {
|
||||
.regs_offset = OMAP4_MCSPI_REG_OFFSET,
|
||||
};
|
||||
|
||||
static int omap3_spi_ofdata_to_platdata(struct udevice *dev)
|
||||
{
|
||||
struct omap2_mcspi_platform_config *data =
|
||||
(struct omap2_mcspi_platform_config *)dev_get_driver_data(dev);
|
||||
struct omap3_spi_plat *plat = dev_get_platdata(dev);
|
||||
|
||||
plat->regs = (struct mcspi *)(dev_read_addr(dev) + data->regs_offset);
|
||||
|
||||
if (dev_read_bool(dev, "ti,pindir-d0-out-d1-in"))
|
||||
plat->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
|
||||
else
|
||||
plat->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id omap3_spi_ids[] = {
|
||||
{ .compatible = "ti,omap2-mcspi", .data = (ulong)&omap2_pdata },
|
||||
{ .compatible = "ti,omap4-mcspi", .data = (ulong)&omap4_pdata },
|
||||
{ }
|
||||
};
|
||||
|
||||
#endif
|
||||
U_BOOT_DRIVER(omap3_spi) = {
|
||||
.name = "omap3_spi",
|
||||
.id = UCLASS_SPI,
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
.of_match = omap3_spi_ids,
|
||||
.ofdata_to_platdata = omap3_spi_ofdata_to_platdata,
|
||||
.platdata_auto_alloc_size = sizeof(struct omap3_spi_plat),
|
||||
#endif
|
||||
.probe = omap3_spi_probe,
|
||||
.ops = &omap3_spi_ops,
|
||||
.priv_auto_alloc_size = sizeof(struct omap3_spi_priv),
|
||||
|
||||
@ -497,7 +497,7 @@ UCLASS_DRIVER(spi) = {
|
||||
.id = UCLASS_SPI,
|
||||
.name = "spi",
|
||||
.flags = DM_UC_FLAG_SEQ_ALIAS,
|
||||
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
.post_bind = dm_scan_fdt_dev,
|
||||
#endif
|
||||
.post_probe = spi_post_probe,
|
||||
|
||||
@ -66,6 +66,12 @@
|
||||
#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
|
||||
#devtypel #instance " "
|
||||
|
||||
#if CONFIG_IS_ENABLED(CMD_USB)
|
||||
# define BOOT_TARGET_USB(func) func(USB, usb, 0)
|
||||
#else
|
||||
# define BOOT_TARGET_USB(func)
|
||||
#endif
|
||||
|
||||
#if CONFIG_IS_ENABLED(CMD_PXE)
|
||||
# define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
|
||||
#else
|
||||
@ -84,6 +90,7 @@
|
||||
func(MMC, mmc, 1) \
|
||||
func(LEGACY_MMC, legacy_mmc, 1) \
|
||||
func(NAND, nand, 0) \
|
||||
BOOT_TARGET_USB(func) \
|
||||
BOOT_TARGET_PXE(func) \
|
||||
BOOT_TARGET_DHCP(func)
|
||||
|
||||
@ -280,8 +287,6 @@
|
||||
#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
|
||||
#endif
|
||||
|
||||
/* SPI flash. */
|
||||
|
||||
/* Network. */
|
||||
/* Enable Atheros phy driver */
|
||||
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
/*
|
||||
* Configuration header file for K3 J721E EVM
|
||||
*
|
||||
* Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Lokesh Vutla <lokeshvutla@ti.com>
|
||||
*/
|
||||
|
||||
@ -23,8 +23,10 @@
|
||||
#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
|
||||
CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
|
||||
#define CONFIG_SYS_UBOOT_BASE 0x50280000
|
||||
/* Image load address in RAM for DFU boot*/
|
||||
#else
|
||||
#define CONFIG_SYS_UBOOT_BASE 0x50080000
|
||||
/*
|
||||
* Maximum size in memory allocated to the SPL BSS. Keep it as tight as
|
||||
* possible (to allow the build to go through), as this directly affects
|
||||
@ -81,16 +83,29 @@
|
||||
"uuid_disk=${uuid_gpt_disk};" \
|
||||
"name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0"
|
||||
|
||||
#ifdef CONFIG_SYS_K3_SPL_ATF
|
||||
#if defined(CONFIG_TARGET_J721E_R5_EVM)
|
||||
#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \
|
||||
"addr_mainr5f0_0load=0x88000000\0" \
|
||||
"name_mainr5f0_0fw=/lib/firmware/j7-main-r5f0_0-fw\0" \
|
||||
"addr_mcur5f0_0load=0x89000000\0" \
|
||||
"name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw\0"
|
||||
#elif defined(CONFIG_TARGET_J7200_R5_EVM)
|
||||
#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \
|
||||
"addr_mcur5f0_0load=0x89000000\0" \
|
||||
"name_mcur5f0_0fw=/lib/firmware/j7200-mcu-r5f0_0-fw\0"
|
||||
#endif /* CONFIG_TARGET_J721E_R5_EVM */
|
||||
#else
|
||||
#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC ""
|
||||
#endif /* CONFIG_SYS_K3_SPL_ATF */
|
||||
|
||||
/* U-Boot MMC-specific configuration */
|
||||
#define EXTRA_ENV_J721E_BOARD_SETTINGS_MMC \
|
||||
"boot=mmc\0" \
|
||||
"mmcdev=1\0" \
|
||||
"bootpart=1:2\0" \
|
||||
"bootdir=/boot\0" \
|
||||
"addr_mainr5f0_0load=88000000\0" \
|
||||
"name_mainr5f0_0fw=/lib/firmware/j7-main-r5f0_0-fw\0" \
|
||||
"addr_mcur5f0_0load=89000000\0" \
|
||||
"name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw\0" \
|
||||
EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \
|
||||
"rd_spec=-\0" \
|
||||
"init_mmc=run args_all args_mmc\0" \
|
||||
"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \
|
||||
@ -109,15 +124,28 @@
|
||||
"${bootdir}/${name_fit}\0" \
|
||||
"partitions=" PARTS_DEFAULT
|
||||
|
||||
/* Set the default list of remote processors to boot */
|
||||
#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
|
||||
#ifdef DEFAULT_RPROCS
|
||||
#undef DEFAULT_RPROCS
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TARGET_J721E_A72_EVM
|
||||
#define DEFAULT_RPROCS "" \
|
||||
"3 /lib/firmware/j7-main-r5f0_1-fw " \
|
||||
"4 /lib/firmware/j7-main-r5f1_0-fw " \
|
||||
"5 /lib/firmware/j7-main-r5f1_1-fw " \
|
||||
"6 /lib/firmware/j7-c66_0-fw " \
|
||||
"7 /lib/firmware/j7-c66_1-fw " \
|
||||
"8 /lib/firmware/j7-c71_0-fw "
|
||||
#endif /* CONFIG_TARGET_J721E_A72_EVM */
|
||||
|
||||
#ifdef CONFIG_TARGET_J7200_A72_EVM
|
||||
#define DEFAULT_RPROCS "" \
|
||||
"2 /lib/firmware/j7200-main-r5f0_0-fw " \
|
||||
"3 /lib/firmware/j7200-main-r5f0_1-fw "
|
||||
#endif /* CONFIG_TARGET_J7200_A72_EVM */
|
||||
|
||||
/* set default dfu_bufsiz to 128KB (sector size of OSPI) */
|
||||
#define EXTRA_ENV_DFUARGS \
|
||||
|
||||
@ -57,7 +57,7 @@
|
||||
"fi;\0" \
|
||||
"mmcboot=mmc dev ${mmcdev}; " \
|
||||
"devnum=${mmcdev}; " \
|
||||
"setenv devtype mmc; " \
|
||||
"devtype=mmc; " \
|
||||
"if mmc rescan; then " \
|
||||
"echo SD/MMC found on device ${mmcdev};" \
|
||||
"if run loadimage; then " \
|
||||
|
||||
78
include/omap3_spi.h
Normal file
78
include/omap3_spi.h
Normal file
@ -0,0 +1,78 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
#ifndef __OMAP3_SPI_H_
|
||||
#define __OMAP3_SPI_H_
|
||||
|
||||
/* per-register bitmasks */
|
||||
#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
|
||||
#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
|
||||
#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
|
||||
#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
|
||||
|
||||
#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
|
||||
|
||||
#define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0)
|
||||
#define OMAP3_MCSPI_MODULCTRL_MS BIT(2)
|
||||
#define OMAP3_MCSPI_MODULCTRL_STEST BIT(3)
|
||||
|
||||
#define OMAP3_MCSPI_CHCONF_PHA BIT(0)
|
||||
#define OMAP3_MCSPI_CHCONF_POL BIT(1)
|
||||
#define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2)
|
||||
#define OMAP3_MCSPI_CHCONF_EPOL BIT(6)
|
||||
#define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7)
|
||||
#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
|
||||
#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
|
||||
#define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12)
|
||||
#define OMAP3_MCSPI_CHCONF_DMAW BIT(14)
|
||||
#define OMAP3_MCSPI_CHCONF_DMAR BIT(15)
|
||||
#define OMAP3_MCSPI_CHCONF_DPE0 BIT(16)
|
||||
#define OMAP3_MCSPI_CHCONF_DPE1 BIT(17)
|
||||
#define OMAP3_MCSPI_CHCONF_IS BIT(18)
|
||||
#define OMAP3_MCSPI_CHCONF_TURBO BIT(19)
|
||||
#define OMAP3_MCSPI_CHCONF_FORCE BIT(20)
|
||||
|
||||
#define OMAP3_MCSPI_CHSTAT_RXS BIT(0)
|
||||
#define OMAP3_MCSPI_CHSTAT_TXS BIT(1)
|
||||
#define OMAP3_MCSPI_CHSTAT_EOT BIT(2)
|
||||
|
||||
#define OMAP3_MCSPI_CHCTRL_EN BIT(0)
|
||||
#define OMAP3_MCSPI_CHCTRL_DIS (0 << 0)
|
||||
|
||||
#define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0)
|
||||
#define MCSPI_PINDIR_D0_IN_D1_OUT 0
|
||||
#define MCSPI_PINDIR_D0_OUT_D1_IN 1
|
||||
|
||||
#define OMAP3_MCSPI_MAX_FREQ 48000000
|
||||
#define SPI_WAIT_TIMEOUT 10
|
||||
|
||||
#define OMAP4_MCSPI_REG_OFFSET 0x100
|
||||
|
||||
/* OMAP3 McSPI registers */
|
||||
struct mcspi_channel {
|
||||
unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */
|
||||
unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */
|
||||
unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */
|
||||
unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */
|
||||
unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */
|
||||
};
|
||||
|
||||
struct mcspi {
|
||||
unsigned char res1[0x10];
|
||||
unsigned int sysconfig; /* 0x10 */
|
||||
unsigned int sysstatus; /* 0x14 */
|
||||
unsigned int irqstatus; /* 0x18 */
|
||||
unsigned int irqenable; /* 0x1C */
|
||||
unsigned int wakeupenable; /* 0x20 */
|
||||
unsigned int syst; /* 0x24 */
|
||||
unsigned int modulctrl; /* 0x28 */
|
||||
struct mcspi_channel channel[4];
|
||||
/* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
|
||||
/* channel1: 0x40 - 0x50, bus 0 & 1 */
|
||||
/* channel2: 0x54 - 0x64, bus 0 & 1 */
|
||||
/* channel3: 0x68 - 0x78, bus 0 */
|
||||
};
|
||||
|
||||
struct omap3_spi_plat {
|
||||
struct mcspi *regs;
|
||||
unsigned int pin_dir:1;
|
||||
};
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user