mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-02 01:20:47 +09:00
arm: Remove pepper board
OF_CONTROL, DM_SPI and other driver model migration deadlines are expired for this board. Remove it. Cc: Ash Charles <ash@gumstix.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
parent
37559488a9
commit
bce26c45e2
@ -1921,7 +1921,6 @@ source "board/freescale/lx2160a/Kconfig"
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source "board/freescale/mx35pdk/Kconfig"
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source "board/freescale/s32v234evb/Kconfig"
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source "board/grinn/chiliboard/Kconfig"
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source "board/gumstix/pepper/Kconfig"
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source "board/hisilicon/hikey/Kconfig"
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source "board/hisilicon/hikey960/Kconfig"
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source "board/hisilicon/poplar/Kconfig"
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@ -160,13 +160,6 @@ config TARGET_PENGWYN
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select DM_SERIAL
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imply CMD_DM
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config TARGET_PEPPER
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bool "Support pepper"
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select DM
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select DM_GPIO
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select DM_SERIAL
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imply CMD_DM
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config TARGET_PHYCORE_AM335X_R2
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bool "Support phyCORE AM335X R2"
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select DM
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@ -1,15 +0,0 @@
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if TARGET_PEPPER
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config SYS_BOARD
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default "pepper"
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config SYS_VENDOR
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default "gumstix"
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config SYS_SOC
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default "am33xx"
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config SYS_CONFIG_NAME
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default "pepper"
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endif
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@ -1,6 +0,0 @@
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PEPPER BOARD
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M: Ash Charles <ash@gumstix.com>
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S: Maintained
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F: board/gumstix/pepper/
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F: include/configs/pepper.h
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F: configs/pepper_defconfig
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@ -1,11 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Makefile
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#
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# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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ifdef CONFIG_SPL_BUILD
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obj-y += mux.o
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endif
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obj-y += board.o
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@ -1,288 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Board functions for Gumstix Pepper and AM335x-based boards
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*
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* Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
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* Based on board/ti/am335x/board.c from Texas Instruments, Inc.
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*/
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#include <common.h>
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#include <env.h>
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#include <errno.h>
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#include <init.h>
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#include <net.h>
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#include <serial.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include <power/tps65217.h>
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#include <watchdog.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SPL_BUILD
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#define OSC (V_OSCK/1000000)
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = MT41K256M16HA125E_RD_DQS,
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.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
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.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
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.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = MT41K256M16HA125E_RATIO,
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.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd1csratio = MT41K256M16HA125E_RATIO,
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.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd2csratio = MT41K256M16HA125E_RATIO,
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.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
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.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
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.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
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.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
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.zq_config = MT41K256M16HA125E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
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};
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const struct dpll_params dpll_ddr3 = {400, OSC-1, 1, -1, -1, -1, -1};
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const struct ctrl_ioregs ioregs_ddr3 = {
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.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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};
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static const struct ddr_data ddr2_data = {
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.datardsratio0 = MT47H128M16RT25E_RD_DQS,
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.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
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.datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
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};
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static const struct cmd_control ddr2_cmd_ctrl_data = {
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.cmd0csratio = MT47H128M16RT25E_RATIO,
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.cmd1csratio = MT47H128M16RT25E_RATIO,
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.cmd2csratio = MT47H128M16RT25E_RATIO,
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};
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static const struct emif_regs ddr2_emif_reg_data = {
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.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
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.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
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.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
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.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
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.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
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.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
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};
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const struct dpll_params dpll_ddr2 = {266, OSC-1, 1, -1, -1, -1, -1};
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const struct ctrl_ioregs ioregs_ddr2 = {
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.cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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.cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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.cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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.dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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.dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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};
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static int read_eeprom(struct pepper_board_id *header)
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{
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if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
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return -ENODEV;
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}
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
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sizeof(struct pepper_board_id))) {
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return -EIO;
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}
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return 0;
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}
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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struct pepper_board_id header;
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enable_i2c0_pin_mux();
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i2c_set_bus_num(0);
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if (read_eeprom(&header) < 0)
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return &dpll_ddr3;
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switch (header.device_vendor) {
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case GUMSTIX_PEPPER:
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return &dpll_ddr2;
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case GUMSTIX_PEPPER_DVI:
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return &dpll_ddr3;
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default:
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return &dpll_ddr3;
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}
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}
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void sdram_init(void)
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{
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const struct dpll_params *dpll = get_dpll_ddr_params();
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/*
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* Here we are assuming PLL clock reveals the type of RAM.
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* DDR2 = 266
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* DDR3 = 400
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* Note that DDR3 is the default.
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*/
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if (dpll->m == 266) {
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config_ddr(dpll->m, &ioregs_ddr2, &ddr2_data,
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&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
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}
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else if (dpll->m == 400) {
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config_ddr(dpll->m, &ioregs_ddr3, &ddr3_data,
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&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
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}
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}
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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return serial_tstc() && serial_getc() == 'c';
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}
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#endif
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void set_uart_mux_conf(void)
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{
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enable_uart0_pin_mux();
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}
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void set_mux_conf_regs(void)
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{
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enable_board_pin_mux();
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}
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#endif
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int board_init(void)
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{
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#if defined(CONFIG_HW_WATCHDOG)
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hw_watchdog_init();
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#endif
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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gpmc_init();
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return 0;
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}
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#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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static void cpsw_control(int enabled)
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{
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/* VTP can be added here */
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return;
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}
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_addr = 0,
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.phy_if = PHY_INTERFACE_MODE_RGMII,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = CPSW_MDIO_BASE,
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.cpsw_base = CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 8,
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.cpdma_reg_ofs = 0x800,
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.slaves = 1,
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.slave_data = cpsw_slaves,
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.ale_reg_ofs = 0xd00,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x108,
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.hw_stats_reg_ofs = 0x900,
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.bd_ram_ofs = 0x2000,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_2,
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};
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int board_eth_init(bd_t *bis)
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{
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int rv, n = 0;
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uint8_t mac_addr[6];
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uint32_t mac_hi, mac_lo;
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const char *devname;
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if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
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/* try reading mac address from efuse */
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mac_lo = readl(&cdev->macid0l);
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mac_hi = readl(&cdev->macid0h);
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mac_addr[0] = mac_hi & 0xFF;
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mac_addr[1] = (mac_hi & 0xFF00) >> 8;
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mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
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mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
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mac_addr[4] = mac_lo & 0xFF;
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mac_addr[5] = (mac_lo & 0xFF00) >> 8;
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if (is_valid_ethaddr(mac_addr))
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eth_env_set_enetaddr("ethaddr", mac_addr);
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}
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writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
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rv = cpsw_register(&cpsw_data);
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if (rv < 0)
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printf("Error %d registering CPSW switch\n", rv);
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else
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n += rv;
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/*
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*
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* CPSW RGMII Internal Delay Mode is not supported in all PVT
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* operating points. So we must set the TX clock delay feature
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* in the KSZ9021 PHY. Since we only support a single ethernet
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* device in U-Boot, we only do this for the current instance.
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*/
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devname = miiphy_get_current_dev();
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/* max rx/tx clock delay, min rx/tx control delay */
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miiphy_write(devname, 0x0, 0x0b, 0x8104);
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miiphy_write(devname, 0x0, 0xc, 0xa0a0);
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/* min rx data delay */
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miiphy_write(devname, 0x0, 0x0b, 0x8105);
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miiphy_write(devname, 0x0, 0x0c, 0x0000);
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/* min tx data delay */
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miiphy_write(devname, 0x0, 0x0b, 0x8106);
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miiphy_write(devname, 0x0, 0x0c, 0x0000);
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return n;
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}
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#endif
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@ -1,31 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Gumstix Pepper and AM335x-based boards information header
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*
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* Copyright (C) 2014, Gumstix, Inc. - http://www.gumstix.com/
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*/
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#ifndef _BOARD_H_
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#define _BOARD_H_
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#define GUMSTIX_PEPPER 0x30000200
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#define GUMSTIX_PEPPER_DVI 0x31000200
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struct pepper_board_id {
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unsigned int device_vendor;
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unsigned char revision;
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unsigned char content;
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char fab_revision[8];
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char env_var[16];
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char en_setting[64];
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};
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/*
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* We must be able to enable uart0, for initial output. We then have a
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* main pinmux function that can be overridden to enable all other pinmux that
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* is required on the board.
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*/
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void enable_uart0_pin_mux(void);
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void enable_board_pin_mux(void);
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void enable_i2c0_pin_mux(void);
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#endif
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@ -1,82 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Muxing for Gumstix Pepper and AM335x-based boards
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*
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* Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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#include <i2c.h>
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#include "board.h"
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static struct module_pin_mux uart0_pin_mux[] = {
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{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
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{-1},
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};
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static struct module_pin_mux mmc0_pin_mux[] = {
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{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
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{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
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{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
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{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
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{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
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{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
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{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
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{-1},
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};
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static struct module_pin_mux i2c0_pin_mux[] = {
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/* I2C_DATA */
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{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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/* I2C_SCLK */
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{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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{-1},
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};
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static struct module_pin_mux rgmii1_pin_mux[] = {
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{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
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{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
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{OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
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{OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
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{OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
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{OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
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{OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
|
||||
{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
|
||||
{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
|
||||
{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
|
||||
{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
|
||||
{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
|
||||
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
|
||||
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
|
||||
{OFFSET(rmii1_refclk), MODE(7) | RXACTIVE}, /* ETH_INT */
|
||||
{OFFSET(mii1_col), MODE(7) | PULLUP_EN}, /* PHY_NRESET */
|
||||
{OFFSET(xdma_event_intr1), MODE(3)},
|
||||
{-1},
|
||||
};
|
||||
|
||||
void enable_uart0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_i2c0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(i2c0_pin_mux);
|
||||
}
|
||||
|
||||
/*
|
||||
* Do board-specific muxes.
|
||||
*/
|
||||
void enable_board_pin_mux(void)
|
||||
{
|
||||
/* I2C0 */
|
||||
configure_module_pin_mux(i2c0_pin_mux);
|
||||
/* SD Card */
|
||||
configure_module_pin_mux(mmc0_pin_mux);
|
||||
/* Ethernet pinmux. */
|
||||
configure_module_pin_mux(rgmii1_pin_mux);
|
||||
}
|
@ -1,43 +0,0 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_OMAP2PLUS=y
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_AM33XX=y
|
||||
CONFIG_TARGET_PEPPER=y
|
||||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_FS_FAT=y
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
# CONFIG_USE_BOOTCOMMAND is not set
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_SPL_FS_EXT4=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
# CONFIG_SPL_NAND_SUPPORT is not set
|
||||
CONFIG_SPL_POWER_SUPPORT=y
|
||||
CONFIG_SPL_WATCHDOG_SUPPORT=y
|
||||
CONFIG_SYS_PROMPT="pepper# "
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SPI=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_BOOTP_DNS2=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_MMC_OMAP_HS=y
|
||||
CONFIG_PHY_ADDR_ENABLE=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_DRIVER_TI_CPSW=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_OMAP3_SPI=y
|
||||
CONFIG_FAT_WRITE=y
|
||||
CONFIG_OF_LIBFDT=y
|
@ -1,78 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2013 Gumstix, Inc. - http://www.gumstix.com/
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_PEPPER_H
|
||||
#define __CONFIG_PEPPER_H
|
||||
|
||||
#include <configs/ti_am335x_common.h>
|
||||
|
||||
/* Clock defines */
|
||||
#define V_OSCK 24000000 /* Clock output from T2 */
|
||||
#define V_SCLK (V_OSCK)
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
|
||||
/* Mach type */
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_PEPPER
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
DEFAULT_LINUX_BOOT_ENV \
|
||||
"bootdir=/boot\0" \
|
||||
"bootfile=zImage\0" \
|
||||
"fdtfile=am335x-pepper.dtb\0" \
|
||||
"console=ttyO0,115200n8\0" \
|
||||
"optargs=\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 rw\0" \
|
||||
"mmcrootfstype=ext4 rootwait\0" \
|
||||
"mmcargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=${mmcroot} " \
|
||||
"rootfstype=${mmcrootfstype}\0" \
|
||||
"bootenv=uEnv.txt\0" \
|
||||
"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
|
||||
"importbootenv=echo Importing environment from mmc ...; " \
|
||||
"env import -t ${loadaddr} ${filesize}\0" \
|
||||
"mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \
|
||||
"load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \
|
||||
"loaduimage=fatload mmc ${mmcdev}:1 ${loadaddr} uImage\0" \
|
||||
"uimageboot=echo Booting from mmc${mmcdev} ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootz ${loadaddr} - ${fdtaddr}\0" \
|
||||
"ubiboot=echo Booting from nand (ubifs) ...; " \
|
||||
"run ubiargs; run ubiload; " \
|
||||
"bootz ${loadaddr} - ${fdtaddr}\0" \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"echo SD/MMC found on device ${mmcdev};" \
|
||||
"if run loadbootenv; then " \
|
||||
"echo Loaded environment from ${bootenv};" \
|
||||
"run importbootenv;" \
|
||||
"fi;" \
|
||||
"if test -n $uenvcmd; then " \
|
||||
"echo Running uenvcmd ...;" \
|
||||
"run uenvcmd;" \
|
||||
"fi;" \
|
||||
"if run mmcload; then " \
|
||||
"run mmcboot;" \
|
||||
"fi;" \
|
||||
"if run loaduimage; then " \
|
||||
"run uimageboot;" \
|
||||
"fi;" \
|
||||
"fi;" \
|
||||
|
||||
/* Serial console configuration */
|
||||
#define CONFIG_SYS_NS16550_COM1 0x44e09000
|
||||
|
||||
/* Ethernet support */
|
||||
#define CONFIG_PHY_RESET_DELAY 1000
|
||||
|
||||
/* SPL */
|
||||
|
||||
#endif /* __CONFIG_PEPPER_H */
|
Loading…
Reference in New Issue
Block a user