mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
arm: Remove pepper board
OF_CONTROL, DM_SPI and other driver model migration deadlines are expired for this board. Remove it. Cc: Ash Charles <ash@gumstix.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Jagan Teki
parent
37559488a9
commit
bce26c45e2
|
|
@ -1921,7 +1921,6 @@ source "board/freescale/lx2160a/Kconfig"
|
|||
source "board/freescale/mx35pdk/Kconfig"
|
||||
source "board/freescale/s32v234evb/Kconfig"
|
||||
source "board/grinn/chiliboard/Kconfig"
|
||||
source "board/gumstix/pepper/Kconfig"
|
||||
source "board/hisilicon/hikey/Kconfig"
|
||||
source "board/hisilicon/hikey960/Kconfig"
|
||||
source "board/hisilicon/poplar/Kconfig"
|
||||
|
|
|
|||
|
|
@ -160,13 +160,6 @@ config TARGET_PENGWYN
|
|||
select DM_SERIAL
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_PEPPER
|
||||
bool "Support pepper"
|
||||
select DM
|
||||
select DM_GPIO
|
||||
select DM_SERIAL
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_PHYCORE_AM335X_R2
|
||||
bool "Support phyCORE AM335X R2"
|
||||
select DM
|
||||
|
|
|
|||
|
|
@ -1,15 +0,0 @@
|
|||
if TARGET_PEPPER
|
||||
|
||||
config SYS_BOARD
|
||||
default "pepper"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "gumstix"
|
||||
|
||||
config SYS_SOC
|
||||
default "am33xx"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "pepper"
|
||||
|
||||
endif
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
PEPPER BOARD
|
||||
M: Ash Charles <ash@gumstix.com>
|
||||
S: Maintained
|
||||
F: board/gumstix/pepper/
|
||||
F: include/configs/pepper.h
|
||||
F: configs/pepper_defconfig
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Makefile
|
||||
#
|
||||
# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += mux.o
|
||||
endif
|
||||
|
||||
obj-y += board.o
|
||||
|
|
@ -1,288 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Board functions for Gumstix Pepper and AM335x-based boards
|
||||
*
|
||||
* Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
|
||||
* Based on board/ti/am335x/board.c from Texas Instruments, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <env.h>
|
||||
#include <errno.h>
|
||||
#include <init.h>
|
||||
#include <net.h>
|
||||
#include <serial.h>
|
||||
#include <spl.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/omap.h>
|
||||
#include <asm/arch/ddr_defs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/mmc_host_def.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/emif.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <i2c.h>
|
||||
#include <miiphy.h>
|
||||
#include <cpsw.h>
|
||||
#include <power/tps65217.h>
|
||||
#include <watchdog.h>
|
||||
#include "board.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define OSC (V_OSCK/1000000)
|
||||
|
||||
static const struct ddr_data ddr3_data = {
|
||||
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
|
||||
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
|
||||
.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
|
||||
.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
|
||||
};
|
||||
|
||||
static const struct cmd_control ddr3_cmd_ctrl_data = {
|
||||
.cmd0csratio = MT41K256M16HA125E_RATIO,
|
||||
.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
|
||||
|
||||
.cmd1csratio = MT41K256M16HA125E_RATIO,
|
||||
.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
|
||||
|
||||
.cmd2csratio = MT41K256M16HA125E_RATIO,
|
||||
.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
|
||||
};
|
||||
|
||||
static struct emif_regs ddr3_emif_reg_data = {
|
||||
.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
|
||||
.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
|
||||
.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
|
||||
.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
|
||||
.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
|
||||
.zq_config = MT41K256M16HA125E_ZQ_CFG,
|
||||
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
|
||||
};
|
||||
|
||||
const struct dpll_params dpll_ddr3 = {400, OSC-1, 1, -1, -1, -1, -1};
|
||||
|
||||
const struct ctrl_ioregs ioregs_ddr3 = {
|
||||
.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
};
|
||||
|
||||
static const struct ddr_data ddr2_data = {
|
||||
.datardsratio0 = MT47H128M16RT25E_RD_DQS,
|
||||
.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
|
||||
.datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
|
||||
};
|
||||
|
||||
static const struct cmd_control ddr2_cmd_ctrl_data = {
|
||||
.cmd0csratio = MT47H128M16RT25E_RATIO,
|
||||
|
||||
.cmd1csratio = MT47H128M16RT25E_RATIO,
|
||||
|
||||
.cmd2csratio = MT47H128M16RT25E_RATIO,
|
||||
};
|
||||
|
||||
static const struct emif_regs ddr2_emif_reg_data = {
|
||||
.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
|
||||
.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
|
||||
.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
|
||||
.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
|
||||
.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
|
||||
.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
|
||||
};
|
||||
|
||||
const struct dpll_params dpll_ddr2 = {266, OSC-1, 1, -1, -1, -1, -1};
|
||||
|
||||
const struct ctrl_ioregs ioregs_ddr2 = {
|
||||
.cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
|
||||
.cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
|
||||
.cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
|
||||
.dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
|
||||
.dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
|
||||
};
|
||||
|
||||
static int read_eeprom(struct pepper_board_id *header)
|
||||
{
|
||||
if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
|
||||
sizeof(struct pepper_board_id))) {
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct dpll_params *get_dpll_ddr_params(void)
|
||||
{
|
||||
struct pepper_board_id header;
|
||||
|
||||
enable_i2c0_pin_mux();
|
||||
i2c_set_bus_num(0);
|
||||
|
||||
if (read_eeprom(&header) < 0)
|
||||
return &dpll_ddr3;
|
||||
|
||||
switch (header.device_vendor) {
|
||||
case GUMSTIX_PEPPER:
|
||||
return &dpll_ddr2;
|
||||
case GUMSTIX_PEPPER_DVI:
|
||||
return &dpll_ddr3;
|
||||
default:
|
||||
return &dpll_ddr3;
|
||||
}
|
||||
}
|
||||
|
||||
void sdram_init(void)
|
||||
{
|
||||
const struct dpll_params *dpll = get_dpll_ddr_params();
|
||||
|
||||
/*
|
||||
* Here we are assuming PLL clock reveals the type of RAM.
|
||||
* DDR2 = 266
|
||||
* DDR3 = 400
|
||||
* Note that DDR3 is the default.
|
||||
*/
|
||||
if (dpll->m == 266) {
|
||||
config_ddr(dpll->m, &ioregs_ddr2, &ddr2_data,
|
||||
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
|
||||
}
|
||||
else if (dpll->m == 400) {
|
||||
config_ddr(dpll->m, &ioregs_ddr3, &ddr3_data,
|
||||
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
int spl_start_uboot(void)
|
||||
{
|
||||
/* break into full u-boot on 'c' */
|
||||
return serial_tstc() && serial_getc() == 'c';
|
||||
}
|
||||
#endif
|
||||
|
||||
void set_uart_mux_conf(void)
|
||||
{
|
||||
enable_uart0_pin_mux();
|
||||
}
|
||||
|
||||
void set_mux_conf_regs(void)
|
||||
{
|
||||
enable_board_pin_mux();
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
#if defined(CONFIG_HW_WATCHDOG)
|
||||
hw_watchdog_init();
|
||||
#endif
|
||||
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
gpmc_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
|
||||
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
|
||||
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
|
||||
|
||||
static void cpsw_control(int enabled)
|
||||
{
|
||||
/* VTP can be added here */
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static struct cpsw_slave_data cpsw_slaves[] = {
|
||||
{
|
||||
.slave_reg_ofs = 0x208,
|
||||
.sliver_reg_ofs = 0xd80,
|
||||
.phy_addr = 0,
|
||||
.phy_if = PHY_INTERFACE_MODE_RGMII,
|
||||
},
|
||||
};
|
||||
|
||||
static struct cpsw_platform_data cpsw_data = {
|
||||
.mdio_base = CPSW_MDIO_BASE,
|
||||
.cpsw_base = CPSW_BASE,
|
||||
.mdio_div = 0xff,
|
||||
.channels = 8,
|
||||
.cpdma_reg_ofs = 0x800,
|
||||
.slaves = 1,
|
||||
.slave_data = cpsw_slaves,
|
||||
.ale_reg_ofs = 0xd00,
|
||||
.ale_entries = 1024,
|
||||
.host_port_reg_ofs = 0x108,
|
||||
.hw_stats_reg_ofs = 0x900,
|
||||
.bd_ram_ofs = 0x2000,
|
||||
.mac_control = (1 << 5),
|
||||
.control = cpsw_control,
|
||||
.host_port_num = 0,
|
||||
.version = CPSW_CTRL_VERSION_2,
|
||||
};
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rv, n = 0;
|
||||
uint8_t mac_addr[6];
|
||||
uint32_t mac_hi, mac_lo;
|
||||
const char *devname;
|
||||
|
||||
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
|
||||
/* try reading mac address from efuse */
|
||||
mac_lo = readl(&cdev->macid0l);
|
||||
mac_hi = readl(&cdev->macid0h);
|
||||
mac_addr[0] = mac_hi & 0xFF;
|
||||
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
|
||||
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
|
||||
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
|
||||
mac_addr[4] = mac_lo & 0xFF;
|
||||
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
|
||||
if (is_valid_ethaddr(mac_addr))
|
||||
eth_env_set_enetaddr("ethaddr", mac_addr);
|
||||
}
|
||||
|
||||
writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
|
||||
|
||||
rv = cpsw_register(&cpsw_data);
|
||||
if (rv < 0)
|
||||
printf("Error %d registering CPSW switch\n", rv);
|
||||
else
|
||||
n += rv;
|
||||
|
||||
/*
|
||||
*
|
||||
* CPSW RGMII Internal Delay Mode is not supported in all PVT
|
||||
* operating points. So we must set the TX clock delay feature
|
||||
* in the KSZ9021 PHY. Since we only support a single ethernet
|
||||
* device in U-Boot, we only do this for the current instance.
|
||||
*/
|
||||
devname = miiphy_get_current_dev();
|
||||
/* max rx/tx clock delay, min rx/tx control delay */
|
||||
miiphy_write(devname, 0x0, 0x0b, 0x8104);
|
||||
miiphy_write(devname, 0x0, 0xc, 0xa0a0);
|
||||
|
||||
/* min rx data delay */
|
||||
miiphy_write(devname, 0x0, 0x0b, 0x8105);
|
||||
miiphy_write(devname, 0x0, 0x0c, 0x0000);
|
||||
|
||||
/* min tx data delay */
|
||||
miiphy_write(devname, 0x0, 0x0b, 0x8106);
|
||||
miiphy_write(devname, 0x0, 0x0c, 0x0000);
|
||||
|
||||
return n;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Gumstix Pepper and AM335x-based boards information header
|
||||
*
|
||||
* Copyright (C) 2014, Gumstix, Inc. - http://www.gumstix.com/
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
#define GUMSTIX_PEPPER 0x30000200
|
||||
#define GUMSTIX_PEPPER_DVI 0x31000200
|
||||
|
||||
struct pepper_board_id {
|
||||
unsigned int device_vendor;
|
||||
unsigned char revision;
|
||||
unsigned char content;
|
||||
char fab_revision[8];
|
||||
char env_var[16];
|
||||
char en_setting[64];
|
||||
};
|
||||
|
||||
/*
|
||||
* We must be able to enable uart0, for initial output. We then have a
|
||||
* main pinmux function that can be overridden to enable all other pinmux that
|
||||
* is required on the board.
|
||||
*/
|
||||
void enable_uart0_pin_mux(void);
|
||||
void enable_board_pin_mux(void);
|
||||
void enable_i2c0_pin_mux(void);
|
||||
#endif
|
||||
|
|
@ -1,82 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Muxing for Gumstix Pepper and AM335x-based boards
|
||||
*
|
||||
* Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/io.h>
|
||||
#include <i2c.h>
|
||||
#include "board.h"
|
||||
|
||||
static struct module_pin_mux uart0_pin_mux[] = {
|
||||
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
|
||||
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux mmc0_pin_mux[] = {
|
||||
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
|
||||
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
|
||||
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
|
||||
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
|
||||
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
|
||||
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
|
||||
{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux i2c0_pin_mux[] = {
|
||||
/* I2C_DATA */
|
||||
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
|
||||
/* I2C_SCLK */
|
||||
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux rgmii1_pin_mux[] = {
|
||||
{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
|
||||
{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
|
||||
{OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
|
||||
{OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
|
||||
{OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
|
||||
{OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
|
||||
{OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
|
||||
{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
|
||||
{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
|
||||
{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
|
||||
{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
|
||||
{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
|
||||
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
|
||||
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
|
||||
{OFFSET(rmii1_refclk), MODE(7) | RXACTIVE}, /* ETH_INT */
|
||||
{OFFSET(mii1_col), MODE(7) | PULLUP_EN}, /* PHY_NRESET */
|
||||
{OFFSET(xdma_event_intr1), MODE(3)},
|
||||
{-1},
|
||||
};
|
||||
|
||||
void enable_uart0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_i2c0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(i2c0_pin_mux);
|
||||
}
|
||||
|
||||
/*
|
||||
* Do board-specific muxes.
|
||||
*/
|
||||
void enable_board_pin_mux(void)
|
||||
{
|
||||
/* I2C0 */
|
||||
configure_module_pin_mux(i2c0_pin_mux);
|
||||
/* SD Card */
|
||||
configure_module_pin_mux(mmc0_pin_mux);
|
||||
/* Ethernet pinmux. */
|
||||
configure_module_pin_mux(rgmii1_pin_mux);
|
||||
}
|
||||
|
|
@ -1,43 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_OMAP2PLUS=y
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_AM33XX=y
|
||||
CONFIG_TARGET_PEPPER=y
|
||||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_FS_FAT=y
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
# CONFIG_USE_BOOTCOMMAND is not set
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_SPL_FS_EXT4=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
# CONFIG_SPL_NAND_SUPPORT is not set
|
||||
CONFIG_SPL_POWER_SUPPORT=y
|
||||
CONFIG_SPL_WATCHDOG_SUPPORT=y
|
||||
CONFIG_SYS_PROMPT="pepper# "
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SPI=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_BOOTP_DNS2=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_MMC_OMAP_HS=y
|
||||
CONFIG_PHY_ADDR_ENABLE=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_DRIVER_TI_CPSW=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_OMAP3_SPI=y
|
||||
CONFIG_FAT_WRITE=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
@ -1,78 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2013 Gumstix, Inc. - http://www.gumstix.com/
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_PEPPER_H
|
||||
#define __CONFIG_PEPPER_H
|
||||
|
||||
#include <configs/ti_am335x_common.h>
|
||||
|
||||
/* Clock defines */
|
||||
#define V_OSCK 24000000 /* Clock output from T2 */
|
||||
#define V_SCLK (V_OSCK)
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
|
||||
/* Mach type */
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_PEPPER
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
DEFAULT_LINUX_BOOT_ENV \
|
||||
"bootdir=/boot\0" \
|
||||
"bootfile=zImage\0" \
|
||||
"fdtfile=am335x-pepper.dtb\0" \
|
||||
"console=ttyO0,115200n8\0" \
|
||||
"optargs=\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 rw\0" \
|
||||
"mmcrootfstype=ext4 rootwait\0" \
|
||||
"mmcargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=${mmcroot} " \
|
||||
"rootfstype=${mmcrootfstype}\0" \
|
||||
"bootenv=uEnv.txt\0" \
|
||||
"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
|
||||
"importbootenv=echo Importing environment from mmc ...; " \
|
||||
"env import -t ${loadaddr} ${filesize}\0" \
|
||||
"mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \
|
||||
"load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \
|
||||
"loaduimage=fatload mmc ${mmcdev}:1 ${loadaddr} uImage\0" \
|
||||
"uimageboot=echo Booting from mmc${mmcdev} ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootz ${loadaddr} - ${fdtaddr}\0" \
|
||||
"ubiboot=echo Booting from nand (ubifs) ...; " \
|
||||
"run ubiargs; run ubiload; " \
|
||||
"bootz ${loadaddr} - ${fdtaddr}\0" \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"echo SD/MMC found on device ${mmcdev};" \
|
||||
"if run loadbootenv; then " \
|
||||
"echo Loaded environment from ${bootenv};" \
|
||||
"run importbootenv;" \
|
||||
"fi;" \
|
||||
"if test -n $uenvcmd; then " \
|
||||
"echo Running uenvcmd ...;" \
|
||||
"run uenvcmd;" \
|
||||
"fi;" \
|
||||
"if run mmcload; then " \
|
||||
"run mmcboot;" \
|
||||
"fi;" \
|
||||
"if run loaduimage; then " \
|
||||
"run uimageboot;" \
|
||||
"fi;" \
|
||||
"fi;" \
|
||||
|
||||
/* Serial console configuration */
|
||||
#define CONFIG_SYS_NS16550_COM1 0x44e09000
|
||||
|
||||
/* Ethernet support */
|
||||
#define CONFIG_PHY_RESET_DELAY 1000
|
||||
|
||||
/* SPL */
|
||||
|
||||
#endif /* __CONFIG_PEPPER_H */
|
||||
Loading…
Reference in New Issue
Block a user