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https://github.com/brain-hackers/u-boot-brain
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riscv: timer: Add support for an early timer
Added support for timer_early_get_count() and timer_early_get_rate() This is mostly useful in tracing. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
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@ -18,11 +18,30 @@
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/* mtime register */
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/* mtime register */
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#define MTIME_REG(base) ((ulong)(base))
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#define MTIME_REG(base) ((ulong)(base))
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static u64 andes_plmt_get_count(struct udevice *dev)
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static u64 notrace andes_plmt_get_count(struct udevice *dev)
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{
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{
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return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
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return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
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}
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}
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#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
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/**
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* timer_early_get_rate() - Get the timer rate before driver model
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*/
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unsigned long notrace timer_early_get_rate(void)
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{
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return RISCV_MMODE_TIMER_FREQ;
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}
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/**
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* timer_early_get_count() - Get the timer count before driver model
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*
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*/
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u64 notrace timer_early_get_count(void)
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{
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return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
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}
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#endif
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static const struct timer_ops andes_plmt_ops = {
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static const struct timer_ops andes_plmt_ops = {
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.get_count = andes_plmt_get_count,
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.get_count = andes_plmt_get_count,
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};
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};
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@ -16,7 +16,7 @@
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#include <timer.h>
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#include <timer.h>
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#include <asm/csr.h>
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#include <asm/csr.h>
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static u64 riscv_timer_get_count(struct udevice *dev)
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static u64 notrace riscv_timer_get_count(struct udevice *dev)
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{
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{
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__maybe_unused u32 hi, lo;
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__maybe_unused u32 hi, lo;
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@ -31,6 +31,25 @@ static u64 riscv_timer_get_count(struct udevice *dev)
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return ((u64)hi << 32) | lo;
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return ((u64)hi << 32) | lo;
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}
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}
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#if CONFIG_IS_ENABLED(RISCV_SMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
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/**
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* timer_early_get_rate() - Get the timer rate before driver model
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*/
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unsigned long notrace timer_early_get_rate(void)
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{
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return RISCV_SMODE_TIMER_FREQ;
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}
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/**
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* timer_early_get_count() - Get the timer count before driver model
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*
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*/
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u64 notrace timer_early_get_count(void)
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{
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return riscv_timer_get_count(NULL);
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}
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#endif
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static int riscv_timer_probe(struct udevice *dev)
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static int riscv_timer_probe(struct udevice *dev)
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{
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{
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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@ -15,11 +15,30 @@
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/* mtime register */
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/* mtime register */
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#define MTIME_REG(base) ((ulong)(base) + 0xbff8)
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#define MTIME_REG(base) ((ulong)(base) + 0xbff8)
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static u64 sifive_clint_get_count(struct udevice *dev)
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static u64 notrace sifive_clint_get_count(struct udevice *dev)
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{
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{
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return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
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return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
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}
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}
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#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
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/**
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* timer_early_get_rate() - Get the timer rate before driver model
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*/
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unsigned long notrace timer_early_get_rate(void)
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{
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return RISCV_MMODE_TIMER_FREQ;
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}
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/**
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* timer_early_get_count() - Get the timer count before driver model
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*
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*/
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u64 notrace timer_early_get_count(void)
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{
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return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
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}
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#endif
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static const struct timer_ops sifive_clint_ops = {
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static const struct timer_ops sifive_clint_ops = {
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.get_count = sifive_clint_get_count,
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.get_count = sifive_clint_get_count,
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};
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};
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@ -17,6 +17,11 @@
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#endif
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#endif
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#endif
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#endif
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#define RISCV_MMODE_TIMERBASE 0xe6000000
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#define RISCV_MMODE_TIMER_FREQ 60000000
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#define RISCV_SMODE_TIMER_FREQ 60000000
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/*
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/*
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* CPU and Board Configuration Options
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* CPU and Board Configuration Options
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*/
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*/
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@ -29,6 +29,11 @@
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#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
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#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
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#define RISCV_MMODE_TIMERBASE 0x2000000
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#define RISCV_MMODE_TIMER_FREQ 1000000
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#define RISCV_SMODE_TIMER_FREQ 1000000
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/* Environment options */
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/* Environment options */
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#ifndef CONFIG_SPL_BUILD
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#ifndef CONFIG_SPL_BUILD
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@ -36,6 +36,11 @@
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#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
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#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
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#define RISCV_MMODE_TIMERBASE 0x2000000
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#define RISCV_MMODE_TIMER_FREQ 1000000
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#define RISCV_SMODE_TIMER_FREQ 1000000
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/* Environment options */
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/* Environment options */
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#ifndef CONFIG_SPL_BUILD
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#ifndef CONFIG_SPL_BUILD
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