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https://github.com/brain-hackers/u-boot-brain
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powerpc/t4qds: cleanup board header file
CONFIG_PHYS_64BIT is always defined for t4qds. Removed unused #ifdef. Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun
parent
cb93071bb6
commit
bc4804516e
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@ -128,14 +128,9 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_ENABLE_36BIT_PHYS
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_ADDR_MAP
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#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
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#endif
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#if 0
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#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
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#endif
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00400000
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#define CONFIG_SYS_ALT_MEMTEST
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@ -146,10 +141,8 @@ unsigned long get_board_ddr_clk(void);
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*/
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#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_DCSRBAR 0xf0000000
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#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
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#endif
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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@ -187,11 +180,7 @@ unsigned long get_board_ddr_clk(void);
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* IFC Definitions
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*/
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#define CONFIG_SYS_FLASH_BASE 0xe0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
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#else
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#endif
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#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
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#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
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@ -243,11 +232,7 @@ unsigned long get_board_ddr_clk(void);
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#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
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#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
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#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
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#ifdef CONFIG_PHYS_64BIT
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#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
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#else
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#define QIXIS_BASE_PHYS QIXIS_BASE
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#endif
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#define CONFIG_SYS_CSPR3_EXT (0xf)
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#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
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@ -270,11 +255,7 @@ unsigned long get_board_ddr_clk(void);
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/* NAND Flash on IFC */
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#define CONFIG_NAND_FSL_IFC
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#define CONFIG_SYS_NAND_BASE 0xff800000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
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#else
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#endif
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#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
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#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
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@ -375,18 +356,12 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_L1_INIT_RAM
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
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/* The assembler doesn't like typecast */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
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((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
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CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
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#else
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
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#endif
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#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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@ -460,19 +435,11 @@ unsigned long get_board_ddr_clk(void);
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* RapidIO
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*/
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#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
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#else
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#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
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#endif
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#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
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#else
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#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
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#endif
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#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
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/*
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@ -520,59 +487,32 @@ unsigned long get_board_ddr_clk(void);
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/* controller 1, direct to uli, tgtid 3, Base address 20000 */
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
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#else
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#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
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#endif
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
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#else
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
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#endif
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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/* controller 2, Slot 2, tgtid 2, Base address 201000 */
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#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
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#else
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#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
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#endif
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
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#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
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#else
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
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#endif
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#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
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/* controller 3, Slot 1, tgtid 1, Base address 202000 */
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#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
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#else
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#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
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#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
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#endif
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#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
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#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
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#else
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#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
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#endif
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#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
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/* controller 4, Base address 203000 */
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@ -588,19 +528,11 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
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#define CONFIG_SYS_BMAN_NUM_PORTALS 50
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#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
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#else
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#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
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#endif
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#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
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#define CONFIG_SYS_QMAN_NUM_PORTALS 50
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#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
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#else
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#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
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#endif
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#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
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#define CONFIG_SYS_DPAA_FMAN
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