From d42ab39f58e828c99a0cba6890e29986e87d11f5 Mon Sep 17 00:00:00 2001 From: Adrian Fiergolski Date: Tue, 24 Nov 2020 16:13:07 +0100 Subject: [PATCH 01/19] tools: zynqmp: Fix regex expression around XPm_ConfigObject The XPm_ConfigObject array definition generated by Vitis 2020.1 differs from previous Vivado versions (before 2019.2). -const u32 XPm_ConfigObject[] __attribute__((used, section(".sys_cfg_data"))) = { +const u32 XPm_ConfigObject[] __attribute__((used, section(".sys_cfg_data"))) = +#elif defined (__ICCARM__) +#pragma location = ".sys_cfg_data" +__root const u32 XPm_ConfigObject[] = +#endif +{ Change the matching regex to handle both cases. Signed-off-by: Adrian Fiergolski Reviewed-by: Luca Ceresoli Signed-off-by: Michal Simek --- tools/zynqmp_pm_cfg_obj_convert.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/zynqmp_pm_cfg_obj_convert.py b/tools/zynqmp_pm_cfg_obj_convert.py index dd27f47921..0a44710e1e 100755 --- a/tools/zynqmp_pm_cfg_obj_convert.py +++ b/tools/zynqmp_pm_cfg_obj_convert.py @@ -289,7 +289,7 @@ code = in_file.read() code = re.sub('//.*?\n|/\*.*?\*/', '', code, flags=re.DOTALL) # remove everything outside the XPm_ConfigObject array definition -code = re.search('const u32 XPm_ConfigObject.*= {\n(.*)};', +code = re.search('const u32 XPm_ConfigObject.*=.*{\n(.*)};', code, flags=re.DOTALL).group(1) # Process each comma-separated array item From e7fcfef431af04f38819555ae407d540f5ba1c93 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 1 Dec 2020 13:58:28 +0100 Subject: [PATCH 02/19] cmd: load: Fix code indentation Reported by smatch like: cmd/load.c:228 read_record() warn: inconsistent indenting Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- cmd/load.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/cmd/load.c b/cmd/load.c index 9a3a16979c..c6a7cc4651 100644 --- a/cmd/load.c +++ b/cmd/load.c @@ -228,12 +228,11 @@ static int read_record(char *buf, ulong len) *p = c; } - /* Check for the console hangup (if any different from serial) */ - if (gd->jt->getc != getchar) { - if (ctrlc()) { - return (-1); + /* Check for the console hangup (if any different from serial) */ + if (gd->jt->getc != getchar) { + if (ctrlc()) + return (-1); } - } } /* line too long - truncate */ From d91a652cfd96e2c4217946a1839cf3c8c0523e85 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 1 Dec 2020 14:02:58 +0100 Subject: [PATCH 03/19] common: usb_storage: Fix code indentation Reported by smatch like: common/usb_storage.c:430 us_one_transfer() warn: inconsistent indenting Signed-off-by: Michal Simek --- common/usb_storage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/usb_storage.c b/common/usb_storage.c index ff25441995..7742bad144 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -431,8 +431,8 @@ static int us_one_transfer(struct us_data *us, int pipe, char *buf, int length) return 0; } /* if our try counter reaches 0, bail out */ - debug(" %ld, data %d\n", - us->pusb_dev->status, partial); + debug(" %ld, data %d\n", + us->pusb_dev->status, partial); if (!maxtry--) return result; } From e5e8bbd25a499e65e7403b0b054fe35abe5187b3 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Tue, 1 Dec 2020 00:34:47 -0700 Subject: [PATCH 04/19] serial: uartlite: Fix uninitialized ret in debug uartlite Endianness detection is checked against uninitialized ret variable. Assign ret with read value from status register to fix this. Fixes: 31a359f87eaa ("serial: uartlite: Add support to work with any endianness") Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek --- drivers/serial/serial_xuartlite.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c index 236ab860ad..1453fb4257 100644 --- a/drivers/serial/serial_xuartlite.c +++ b/drivers/serial/serial_xuartlite.c @@ -148,7 +148,7 @@ static inline void _debug_uart_init(void) uart_out32(®s->control, 0); uart_out32(®s->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX); - uart_in32(®s->status); + ret = uart_in32(®s->status); /* Endianness detection */ if ((ret & SR_TX_FIFO_EMPTY) != SR_TX_FIFO_EMPTY) { little_endian = true; From 2d381d2fe2d202694d0b201ee81034c486028641 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 29 Sep 2020 13:43:22 +0200 Subject: [PATCH 05/19] arm64: zynqmp: Sync DT with Linux kernel All changes are recorded in lore.kernel.org. Here are links to that patches for the record. Link: https://lore.kernel.org/r/f59a63d8cb941592de6d2dee8afa6f120b2e40c8.1601379794.git.michal.simek@xilinx.com Link: https://lore.kernel.org/r/68f20a2b2bb0feee80bc3348619c2ee98aa69963.1598263539.git.michal.simek@xilinx.com Link: https://lore.kernel.org/r/f767fe007e446a2299fda9905e75b723c650a424.1605021644.git.michal.simek@xilinx.com Link: https://lore.kernel.org/r/cc294ae1a79ef845af6809ddb4049f0c0f5bb87a.1598259551.git.michal.simek@xilinx.com Link: https://lore.kernel.org/r/20200629081744.13916-1-krzk@kernel.org And there are other minor changes (just moving things around). Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 61 ++++++++++++++++++---------------------- 1 file changed, 28 insertions(+), 33 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 1634af0bd8..aa0ac95e12 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -115,8 +115,10 @@ <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, <0x0 0xff990ea0 0x0 0x20>; - reg-names = "local_request_region", "local_response_region", - "remote_request_region", "remote_response_region"; + reg-names = "local_request_region", + "local_response_region", + "remote_request_region", + "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <4>; }; @@ -145,15 +147,10 @@ firmware { zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; + #power-domain-cells = <1>; method = "smc"; - #power-domain-cells = <0x1>; u-boot,dm-pre-reloc; - zynqmp_pcap: pcap { - compatible = "xlnx,zynqmp-pcap-fpga"; - clock-names = "ref_clk"; - }; - zynqmp_power: zynqmp-power { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-power"; @@ -163,6 +160,11 @@ mbox-names = "tx", "rx"; }; + zynqmp_pcap: pcap { + compatible = "xlnx,zynqmp-pcap-fpga"; + clock-names = "ref_clk"; + }; + zynqmp_reset: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; @@ -206,26 +208,7 @@ }; }; - amba_apu: amba-apu@0 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0 0xffffffff>; - - gic: interrupt-controller@f9010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - reg = <0x0 0xf9010000 0x10000>, - <0x0 0xf9020000 0x20000>, - <0x0 0xf9040000 0x20000>, - <0x0 0xf9060000 0x20000>; - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <1 9 0xf04>; - }; - }; - - amba: amba { + amba: axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; @@ -380,6 +363,18 @@ power-domains = <&zynqmp_firmware PD_GDMA>; }; + gic: interrupt-controller@f9010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + reg = <0x0 0xf9010000 0x0 0x10000>, + <0x0 0xf9020000 0x0 0x20000>, + <0x0 0xf9040000 0x0 0x20000>, + <0x0 0xf9060000 0x0 0x20000>; + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <1 9 0xf04>; + }; + gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; @@ -590,7 +585,7 @@ }; i2c0: i2c@ff020000 { - compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; + compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; @@ -601,7 +596,7 @@ }; i2c1: i2c@ff030000 { - compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; + compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; @@ -639,8 +634,8 @@ <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; - ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ - 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ + ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ + <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, @@ -770,7 +765,7 @@ clock-output-names = "clk_out_sd1", "clk_in_sd1"; }; - smmu: smmu@fd800000 { + smmu: iommu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; From 5766429b7c7b71f5cc333b727c569809d5c82d34 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Thu, 17 Dec 2020 03:15:55 -0700 Subject: [PATCH 06/19] microblaze: Set script_offset_nor env variable Set script_offset_nor env variable using CONFIG_BOOT_SCRIPT_OFFSET and nor flash start address to keep bootscript offset configurable. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek --- board/xilinx/microblaze-generic/microblaze-generic.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index e590999769..d4095c07c1 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -67,7 +67,10 @@ int board_late_init(void) status |= env_set_hex("ramdisk_addr_r", gd->ram_base + SZ_32M + SZ_4M + SZ_2M); - + if (IS_ENABLED(CONFIG_MTD_NOR_FLASH)) + status |= env_set_hex("script_offset_nor", + gd->bd->bi_flashstart + + CONFIG_BOOT_SCRIPT_OFFSET); if (status) printf("%s: Saving run time variables FAILED\n", __func__); From 6b80de790cf95c5e2e3fab57b33a9db1004e4ccb Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Thu, 17 Dec 2020 03:15:56 -0700 Subject: [PATCH 07/19] microblaze: Add nor device to distro boot Add parallel nor device to distroboot for microblaze. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek --- include/configs/microblaze-generic.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index bc0bf04973..59b20cf116 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -81,6 +81,20 @@ # define BOOT_TARGET_DEVICES_QSPI(func) #endif +#if defined(CONFIG_MTD_NOR_FLASH) +# define BOOT_TARGET_DEVICES_NOR(func) func(NOR, nor, na) +#else +# define BOOT_TARGET_DEVICES_NOR(func) +#endif + +#define BOOTENV_DEV_NOR(devtypeu, devtypel, instance) \ + "bootcmd_nor=cp.b ${script_offset_nor} ${scriptaddr} ${script_size_f} && " \ + "echo NOR: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo NOR: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_NOR(devtypeu, devtypel, instance) \ + "nor " + #define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ "bootcmd_qspi=sf probe 0 0 0 && " \ "sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \ @@ -101,7 +115,8 @@ #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_JTAG(func) \ - BOOT_TARGET_DEVICES_QSPI(func) \ + BOOT_TARGET_DEVICES_QSPI(func) \ + BOOT_TARGET_DEVICES_NOR(func) \ BOOT_TARGET_DEVICES_DHCP(func) \ BOOT_TARGET_DEVICES_PXE(func) From 90217487a13f73001654e41e152303644736617b Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Thu, 19 Nov 2020 05:00:36 -0700 Subject: [PATCH 08/19] spi: zynqmp_gqspi: Fix unaligned data writes issue When unaligned 3 bytes data write operation is performed, 3rd byte is being over written by 1st byte of 3 bytes data. This patch fixes it. Signed-off-by: T Karthik Reddy Signed-off-by: Michal Simek --- drivers/spi/zynqmp_gqspi.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index e0e6687037..a56e8b2509 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -429,10 +429,8 @@ static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size) data |= GENMASK(31, 16); break; case 3: - data = *((u16 *)buf); - buf += 2; - data |= (*((u8 *)buf) << 16); - buf += 1; + data = *buf; + buf += 3; data |= GENMASK(31, 24); break; } From 59fbd5c1f80fc730d003dfaa5bd16ad6fe3c04a2 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 12 Oct 2018 16:55:36 +0530 Subject: [PATCH 09/19] arm64: zynqmp: Add ethernet node for zcu1275 revB This patch add ethernet node gem1 to zcu1275 RevB. GMII to RGMII converter sits between MAC and external phy connected over GMII to MAC and RGMMI to external phy. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu1275-revB.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index b612215f40..1de890c30f 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -23,6 +23,7 @@ serial1 = &dcc; spi0 = &qspi; mmc0 = &sdhci1; + ethernet0 = &gem1; }; chosen { @@ -40,6 +41,29 @@ status = "okay"; }; +&gem1 { + status = "okay"; + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy1: ethernet-phy@1 { + reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ + rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ + txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ + txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ + rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ + rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ + rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ + rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ + rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ + txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ + txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ + txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ + txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ + }; + }; +}; + &qspi { status = "okay"; flash@0 { From 0e3a7aa7a9cbf5764cae8ffbda09985c677d4476 Mon Sep 17 00:00:00 2001 From: Harini Katakam Date: Tue, 18 Feb 2020 14:20:18 +0530 Subject: [PATCH 10/19] arm64: zynqmp: Add Ethernet node for zcu1285 revA This patch add ethernet node gem1 to zcu1285 RevB. GMII to RGMII converter sits between MAC and external phy connected over GMII to MAC and RGMMI to external phy Signed-off-by: Harini Katakam Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu1285-revA.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts index f041df83da..21d62e993a 100644 --- a/arch/arm/dts/zynqmp-zcu1285-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts @@ -23,6 +23,7 @@ serial1 = &dcc; spi0 = &qspi; mmc0 = &sdhci1; + ethernet0 = &gem1; /* EMIO */ i2c = &i2c0; /* EMIO */ }; @@ -222,6 +223,28 @@ }; }; +&gem1 { + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy1: ethernet-phy@1 { + reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ + rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ + txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ + txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ + rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ + rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ + rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ + rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ + rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ + txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ + txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ + txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ + txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ + }; + }; +}; + &qspi { status = "okay"; flash@0 { From 389b45d6b05784c0043bac859666b98a5f704402 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 27 Dec 2020 11:28:12 +0100 Subject: [PATCH 11/19] zynq: mtd: nand: remove superfluous if This sort of code does not make much sense: if (ondie_ecc_enabled) { if (ondie_ecc_enabled) { Remove the inner if. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt Signed-off-by: Michal Simek --- drivers/mtd/nand/raw/zynq_nand.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c index 92db2aa19c..65817ea7f2 100644 --- a/drivers/mtd/nand/raw/zynq_nand.c +++ b/drivers/mtd/nand/raw/zynq_nand.c @@ -1206,12 +1206,10 @@ static int zynq_nand_probe(struct udevice *dev) nand_chip->options |= NAND_SUBPAGE_READ; /* On-Die ECC spare bytes offset 8 is used for ECC codes */ - if (ondie_ecc_enabled) { - nand_chip->ecc.layout = &ondie_nand_oob_64; - /* Use the BBT pattern descriptors */ - nand_chip->bbt_td = &bbt_main_descr; - nand_chip->bbt_md = &bbt_mirror_descr; - } + nand_chip->ecc.layout = &ondie_nand_oob_64; + /* Use the BBT pattern descriptors */ + nand_chip->bbt_td = &bbt_main_descr; + nand_chip->bbt_md = &bbt_mirror_descr; } else { /* Hardware ECC generates 3 bytes ECC code for each 512 bytes */ nand_chip->ecc.mode = NAND_ECC_HW; From b6d14c52f91b57367e7bd8499c963b74fb74b41e Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 3 Jan 2021 18:07:53 +0100 Subject: [PATCH 12/19] fru: ops: avoid out of bounds access MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Building xilinx_zynq_virt_defconfig fails on origin/next as reported by GCC 10.2 (as provided by Debian Bullseye): CC board/xilinx/common/fru_ops.o board/xilinx/common/fru_ops.c: In function ‘fru_capture’: board/xilinx/common/fru_ops.c:173:8: error: array subscript 284 is outside array bounds of ‘struct fru_table[1]’ [-Werror=array-bounds] 173 | limit = data + sizeof(struct fru_board_data); | ~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ board/xilinx/common/fru_ops.c:17:18: note: while referencing ‘fru_data’ 17 | struct fru_table fru_data __section(.data); | ^~~~~~~~ When using sizeof(struct fru_board_data) to find the end of the structure you should add it to the start of the structure. Signed-off-by: Heinrich Schuchardt Signed-off-by: Michal Simek --- board/xilinx/common/fru_ops.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/xilinx/common/fru_ops.c b/board/xilinx/common/fru_ops.c index b4cd3d4998..44f0913f2e 100644 --- a/board/xilinx/common/fru_ops.c +++ b/board/xilinx/common/fru_ops.c @@ -170,7 +170,7 @@ static int fru_parse_board(unsigned long addr) data = (u8 *)&fru_data.brd.manufacturer_type_len; /* Record max structure limit not to write data over allocated space */ - limit = data + sizeof(struct fru_board_data); + limit = (u8 *)&fru_data.brd + sizeof(struct fru_board_data); for (i = 0; ; i++, data += FRU_BOARD_MAX_LEN) { len = fru_check_type_len(*(u8 *)addr, fru_data.brd.lang_code, From 17da310ac41424f056af3a88a0ff081925a027ff Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 14 Dec 2020 09:14:03 +0100 Subject: [PATCH 13/19] video: Fix video sync kernel-doc format Place description below function parameters to make kernel-doc stript happy. Also rename dev to vid to be aligned with function parameters. Fixes: 1acafc73bfc7 ("dm: video: Add a video uclass") Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- include/video.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/video.h b/include/video.h index 9d09d2409a..7313b17f7c 100644 --- a/include/video.h +++ b/include/video.h @@ -151,13 +151,13 @@ int video_clear(struct udevice *dev); /** * video_sync() - Sync a device's frame buffer with its hardware * + * @vid: Device to sync + * @force: True to force a sync even if there was one recently (this is + * very expensive on sandbox) + * * Some frame buffers are cached or have a secondary frame buffer. This * function syncs these up so that the current contents of the U-Boot frame * buffer are displayed to the user. - * - * @dev: Device to sync - * @force: True to force a sync even if there was one recently (this is - * very expensive on sandbox) */ void video_sync(struct udevice *vid, bool force); From 9de731f295c5f1aa0f55f30b076b94f9cb72428e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 14 Dec 2020 08:47:52 +0100 Subject: [PATCH 14/19] video: Let video_sync to return error value This patch is preparation for follow up one to support cases where synchronization can fail. Suggested-by: Simon Glass Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- drivers/video/vidconsole-uclass.c | 40 ++++++++++++++++++++++--------- drivers/video/video-uclass.c | 12 +++++++--- drivers/video/video_bmp.c | 5 +--- include/video.h | 4 +++- 4 files changed, 42 insertions(+), 19 deletions(-) diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c index 3a07f36ce2..f29c0e58c7 100644 --- a/drivers/video/vidconsole-uclass.c +++ b/drivers/video/vidconsole-uclass.c @@ -89,9 +89,7 @@ static int vidconsole_back(struct udevice *dev) if (priv->ycur < 0) priv->ycur = 0; } - video_sync(dev->parent, false); - - return 0; + return video_sync(dev->parent, false); } /* Move to a newline, scrolling the display if necessary */ @@ -101,7 +99,7 @@ static void vidconsole_newline(struct udevice *dev) struct udevice *vid_dev = dev->parent; struct video_priv *vid_priv = dev_get_uclass_priv(vid_dev); const int rows = CONFIG_CONSOLE_SCROLL_LINES; - int i; + int i, ret; priv->xcur_frac = priv->xstart_frac; priv->ycur += priv->y_charsize; @@ -116,7 +114,12 @@ static void vidconsole_newline(struct udevice *dev) } priv->last_ch = 0; - video_sync(dev->parent, false); + ret = video_sync(dev->parent, false); + if (ret) { +#ifdef DEBUG + console_puts_select_stderr(true, "[vc err: video_sync]"); +#endif + } } static const struct vid_rgb colors[VID_COLOR_COUNT] = { @@ -348,8 +351,15 @@ static void vidconsole_escape_char(struct udevice *dev, char ch) parsenum(priv->escape_buf + 1, &mode); if (mode == 2) { + int ret; + video_clear(dev->parent); - video_sync(dev->parent, false); + ret = video_sync(dev->parent, false); + if (ret) { +#ifdef DEBUG + console_puts_select_stderr(true, "[vc err: video_sync]"); +#endif + } priv->ycur = 0; priv->xcur_frac = priv->xstart_frac; } else { @@ -565,7 +575,12 @@ static void vidconsole_putc(struct stdio_dev *sdev, const char ch) console_puts_select_stderr(true, "[vc err: putc]"); #endif } - video_sync(dev->parent, false); + ret = video_sync(dev->parent, false); + if (ret) { +#ifdef DEBUG + console_puts_select_stderr(true, "[vc err: video_sync]"); +#endif + } } static void vidconsole_puts(struct stdio_dev *sdev, const char *s) @@ -582,7 +597,12 @@ static void vidconsole_puts(struct stdio_dev *sdev, const char *s) console_puts_select_stderr(true, str); #endif } - video_sync(dev->parent, false); + ret = video_sync(dev->parent, false); + if (ret) { +#ifdef DEBUG + console_puts_select_stderr(true, "[vc err: video_sync]"); +#endif + } } /* Set up the number of rows and colours (rotated drivers override this) */ @@ -691,9 +711,7 @@ static int do_video_puts(struct cmd_tbl *cmdtp, int flag, int argc, for (s = argv[1]; *s; s++) vidconsole_put_char(dev, *s); - video_sync(dev->parent, false); - - return 0; + return video_sync(dev->parent, false); } U_BOOT_CMD( diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index 650891e49d..6fc4128017 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #ifdef CONFIG_SANDBOX @@ -172,7 +173,7 @@ void video_set_default_colors(struct udevice *dev, bool invert) } /* Flush video activity to the caches */ -void video_sync(struct udevice *vid, bool force) +int video_sync(struct udevice *vid, bool force) { /* * flush_dcache_range() is declared in common.h but it seems that some @@ -196,17 +197,22 @@ void video_sync(struct udevice *vid, bool force) last_sync = get_timer(0); } #endif + return 0; } void video_sync_all(void) { struct udevice *dev; + int ret; for (uclass_find_first_device(UCLASS_VIDEO, &dev); dev; uclass_find_next_device(&dev)) { - if (device_active(dev)) - video_sync(dev, true); + if (device_active(dev)) { + ret = video_sync(dev, true); + if (ret) + dev_dbg(dev, "Video sync failed\n"); + } } } diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c index 5a4d12c68d..66de22318f 100644 --- a/drivers/video/video_bmp.c +++ b/drivers/video/video_bmp.c @@ -379,8 +379,5 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, if (ret) return log_ret(ret); - video_sync(dev, false); - - return 0; + return video_sync(dev, false); } - diff --git a/include/video.h b/include/video.h index 7313b17f7c..1bfe6843a8 100644 --- a/include/video.h +++ b/include/video.h @@ -155,11 +155,13 @@ int video_clear(struct udevice *dev); * @force: True to force a sync even if there was one recently (this is * very expensive on sandbox) * + * @return: 0 always + * * Some frame buffers are cached or have a secondary frame buffer. This * function syncs these up so that the current contents of the U-Boot frame * buffer are displayed to the user. */ -void video_sync(struct udevice *vid, bool force); +int video_sync(struct udevice *vid, bool force); /** * video_sync_all() - Sync all devices' frame buffers with there hardware From 9d69c2d9a8eb27bfa2ac0ac1a0fc779f5eccb49b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 3 Dec 2020 09:30:00 +0100 Subject: [PATCH 15/19] video: Introduce video_sync operation Some drivers like LCD connected via SPI requires explicit sync function which copy framebuffer content over SPI to controller to display. This hook doesn't exist yet that's why introduce it via video operations. Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- drivers/video/video-uclass.c | 9 +++++++++ include/video.h | 12 ++++++++++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index 6fc4128017..938e7d3713 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -175,6 +175,15 @@ void video_set_default_colors(struct udevice *dev, bool invert) /* Flush video activity to the caches */ int video_sync(struct udevice *vid, bool force) { + struct video_ops *ops = video_get_ops(vid); + int ret; + + if (ops && ops->video_sync) { + ret = ops->video_sync(vid); + if (ret) + return ret; + } + /* * flush_dcache_range() is declared in common.h but it seems that some * architectures do not actually implement it. Is there a way to find diff --git a/include/video.h b/include/video.h index 1bfe6843a8..12fc525ab4 100644 --- a/include/video.h +++ b/include/video.h @@ -114,8 +114,16 @@ struct video_priv { u8 bg_col_idx; }; -/* Placeholder - there are no video operations at present */ +/** + * struct video_ops - structure for keeping video operations + * @video_sync: Synchronize FB with device. Some device like SPI based LCD + * displays needs synchronization when data in an FB is available. + * For these devices implement video_sync hook to call a sync + * function. vid is pointer to video device udevice. Function + * should return 0 on success video_sync and error code otherwise + */ struct video_ops { + int (*video_sync)(struct udevice *vid); }; #define video_get_ops(dev) ((struct video_ops *)(dev)->driver->ops) @@ -155,7 +163,7 @@ int video_clear(struct udevice *dev); * @force: True to force a sync even if there was one recently (this is * very expensive on sandbox) * - * @return: 0 always + * @return: 0 on success, error code otherwise * * Some frame buffers are cached or have a secondary frame buffer. This * function syncs these up so that the current contents of the U-Boot frame From 1ac1a04b9ed809e8f9510f6ec6b4d4b9139984c0 Mon Sep 17 00:00:00 2001 From: Vikhyat Goyal Date: Wed, 2 Dec 2020 15:21:51 -0700 Subject: [PATCH 16/19] video: seps525: Add dt binding description Added dt binding for seps525 display driver. Signed-off-by: Vikhyat Goyal Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- MAINTAINERS | 1 + .../video/syncoam,seps525.txt | 24 +++++++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 doc/device-tree-bindings/video/syncoam,seps525.txt diff --git a/MAINTAINERS b/MAINTAINERS index 52d7307525..8e2ccc24df 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -548,6 +548,7 @@ S: Maintained T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/mach-zynq/ F: doc/board/xilinx/ +F: doc/device-tree-bindings/video/syncoam,seps525.txt F: drivers/clk/clk_zynq.c F: drivers/fpga/zynqpl.c F: drivers/gpio/zynq_gpio.c diff --git a/doc/device-tree-bindings/video/syncoam,seps525.txt b/doc/device-tree-bindings/video/syncoam,seps525.txt new file mode 100644 index 0000000000..e1e0db9d71 --- /dev/null +++ b/doc/device-tree-bindings/video/syncoam,seps525.txt @@ -0,0 +1,24 @@ +spi based seps525 framebuffer display driver + +Driver for seps525 display controller (in spi mode), This binding supports selection +of spi chipselect, spi max frequency, gpio to drive dc and reset pin of seps525 +controller and spi transaction bit length. + +Required properties: +- compatible: "syncoam,seps525" +- reg: Specifies the chip-select the seps525 is connected to on the spi bus +- reset-gpios: gpio connected to reset pin of seps525 controller. +- dc-gpios: gpio connected to dc pin of seps525 controller: +- buswidth: bitlength of each spi transaction + +Example: + displayspi@0 { + compatible = "syncoam,seps525"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-cpol; + spi-cpha; + buswidth = <8>; + reset-gpios = <&gpio 0x1c GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio 0x1b GPIO_ACTIVE_HIGH>; + }; From b66d7af41f333f3fc960a18714d25474c512bcaa Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 3 Dec 2020 09:31:35 +0100 Subject: [PATCH 17/19] video: seps525: Add seps525 SPI driver Add support for the WiseChip Semiconductor Inc. (UG-6028GDEBF02) display using the SEPS525 (Syncoam) LCD Controller. Syncoam Seps525 PM-Oled is RGB 160x128 display. This driver has been tested through zynq-spi driver. ZynqMP> load mmc 1 100000 rainbow.bmp 61562 bytes read in 20 ms (2.9 MiB/s) ZynqMP> bmp info 100000 Image size : 160 x 128 Bits per pixel: 24 Compression : 0 ZynqMP> bmp display 100000 ZynqMP> setenv stdout vidconsole Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- MAINTAINERS | 1 + drivers/video/Kconfig | 7 + drivers/video/Makefile | 1 + drivers/video/seps525.c | 327 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 336 insertions(+) create mode 100644 drivers/video/seps525.c diff --git a/MAINTAINERS b/MAINTAINERS index 8e2ccc24df..26dd2543e5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -590,6 +590,7 @@ F: drivers/spi/zynq_qspi.c F: drivers/spi/zynq_spi.c F: drivers/timer/cadence-ttc.c F: drivers/usb/host/ehci-zynq.c +F: drivers/video/seps525.c F: drivers/watchdog/cdns_wdt.c F: include/zynqmppl.h F: include/zynqmp_firmware.h diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 998271b9b6..71363409f0 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -652,6 +652,13 @@ config VIDEO_NX HDMI. This option enables this support which can be used on devices which have an eDP display connected. +config VIDEO_SEPS525 + bool "Enable video support for Seps525" + depends on DM_VIDEO + help + Enable support for the Syncoam PM-OLED display driver (RGB 160x128). + Currently driver is supporting only SPI interface. + source "drivers/video/nexell/Kconfig" config VIDEO diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 67a492a2d6..9db96aa891 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o obj-$(CONFIG_VIDEO_VESA) += vesa.o +obj-$(CONFIG_VIDEO_SEPS525) += seps525.o obj-y += bridge/ obj-y += sunxi/ diff --git a/drivers/video/seps525.c b/drivers/video/seps525.c new file mode 100644 index 0000000000..369e5e6afc --- /dev/null +++ b/drivers/video/seps525.c @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * FB driver for the WiseChip Semiconductor Inc. (UG-6028GDEBF02) display + * using the SEPS525 (Syncoam) LCD Controller + * + * Copyright (C) 2020 Xilinx Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define WIDTH 160 +#define HEIGHT 128 + +#define SEPS525_INDEX 0x00 +#define SEPS525_STATUS_RD 0x01 +#define SEPS525_OSC_CTL 0x02 +#define SEPS525_IREF 0x80 +#define SEPS525_CLOCK_DIV 0x03 +#define SEPS525_REDUCE_CURRENT 0x04 +#define SEPS525_SOFT_RST 0x05 +#define SEPS525_DISP_ONOFF 0x06 +#define SEPS525_PRECHARGE_TIME_R 0x08 +#define SEPS525_PRECHARGE_TIME_G 0x09 +#define SEPS525_PRECHARGE_TIME_B 0x0A +#define SEPS525_PRECHARGE_CURRENT_R 0x0B +#define SEPS525_PRECHARGE_CURRENT_G 0x0C +#define SEPS525_PRECHARGE_CURRENT_B 0x0D +#define SEPS525_DRIVING_CURRENT_R 0x10 +#define SEPS525_DRIVING_CURRENT_G 0x11 +#define SEPS525_DRIVING_CURRENT_B 0x12 +#define SEPS525_DISPLAYMODE_SET 0x13 +#define SEPS525_RGBIF 0x14 +#define SEPS525_RGB_POL 0x15 +#define SEPS525_MEMORY_WRITEMODE 0x16 +#define SEPS525_MX1_ADDR 0x17 +#define SEPS525_MX2_ADDR 0x18 +#define SEPS525_MY1_ADDR 0x19 +#define SEPS525_MY2_ADDR 0x1A +#define SEPS525_MEMORY_ACCESS_POINTER_X 0x20 +#define SEPS525_MEMORY_ACCESS_POINTER_Y 0x21 +#define SEPS525_DDRAM_DATA_ACCESS_PORT 0x22 +#define SEPS525_GRAY_SCALE_TABLE_INDEX 0x50 +#define SEPS525_GRAY_SCALE_TABLE_DATA 0x51 +#define SEPS525_DUTY 0x28 +#define SEPS525_DSL 0x29 +#define SEPS525_D1_DDRAM_FAC 0x2E +#define SEPS525_D1_DDRAM_FAR 0x2F +#define SEPS525_D2_DDRAM_SAC 0x31 +#define SEPS525_D2_DDRAM_SAR 0x32 +#define SEPS525_SCR1_FX1 0x33 +#define SEPS525_SCR1_FX2 0x34 +#define SEPS525_SCR1_FY1 0x35 +#define SEPS525_SCR1_FY2 0x36 +#define SEPS525_SCR2_SX1 0x37 +#define SEPS525_SCR2_SX2 0x38 +#define SEPS525_SCR2_SY1 0x39 +#define SEPS525_SCR2_SY2 0x3A +#define SEPS525_SCREEN_SAVER_CONTEROL 0x3B +#define SEPS525_SS_SLEEP_TIMER 0x3C +#define SEPS525_SCREEN_SAVER_MODE 0x3D +#define SEPS525_SS_SCR1_FU 0x3E +#define SEPS525_SS_SCR1_MXY 0x3F +#define SEPS525_SS_SCR2_FU 0x40 +#define SEPS525_SS_SCR2_MXY 0x41 +#define SEPS525_MOVING_DIRECTION 0x42 +#define SEPS525_SS_SCR2_SX1 0x47 +#define SEPS525_SS_SCR2_SX2 0x48 +#define SEPS525_SS_SCR2_SY1 0x49 +#define SEPS525_SS_SCR2_SY2 0x4A + +/* SEPS525_DISPLAYMODE_SET */ +#define MODE_SWAP_BGR BIT(7) +#define MODE_SM BIT(6) +#define MODE_RD BIT(5) +#define MODE_CD BIT(4) + +/** + * struct seps525_priv - Private structure + * @reset_gpio: Reset gpio pin + * @dc_gpio: Data/command control gpio pin + * @dev: Device uclass for video_ops + */ +struct seps525_priv { + struct gpio_desc reset_gpio; + struct gpio_desc dc_gpio; + struct udevice *dev; +}; + +static int seps525_spi_write_cmd(struct udevice *dev, u32 reg) +{ + struct seps525_priv *priv = dev_get_priv(dev); + u8 buf8 = reg; + int ret; + + ret = dm_gpio_set_value(&priv->dc_gpio, 0); + if (ret) { + dev_dbg(dev, "Failed to handle dc\n"); + return ret; + } + + ret = dm_spi_xfer(dev, 8, &buf8, NULL, SPI_XFER_BEGIN | SPI_XFER_END); + if (ret) + dev_dbg(dev, "Failed to write command\n"); + + return ret; +} + +static int seps525_spi_write_data(struct udevice *dev, u32 val) +{ + struct seps525_priv *priv = dev_get_priv(dev); + u8 buf8 = val; + int ret; + + ret = dm_gpio_set_value(&priv->dc_gpio, 1); + if (ret) { + dev_dbg(dev, "Failed to handle dc\n"); + return ret; + } + + ret = dm_spi_xfer(dev, 8, &buf8, NULL, SPI_XFER_BEGIN | SPI_XFER_END); + if (ret) + dev_dbg(dev, "Failed to write data\n"); + + return ret; +} + +static void seps525_spi_write(struct udevice *dev, u32 reg, u32 val) +{ + (void)seps525_spi_write_cmd(dev, reg); + (void)seps525_spi_write_data(dev, val); +} + +static int seps525_display_init(struct udevice *dev) +{ + /* Disable Oscillator Power Down */ + seps525_spi_write(dev, SEPS525_REDUCE_CURRENT, 0x03); + mdelay(5); + + /* Set Normal Driving Current */ + seps525_spi_write(dev, SEPS525_REDUCE_CURRENT, 0x00); + mdelay(5); + + seps525_spi_write(dev, SEPS525_SCREEN_SAVER_CONTEROL, 0x00); + /* Set EXPORT1 Pin at Internal Clock */ + seps525_spi_write(dev, SEPS525_OSC_CTL, 0x01); + /* Set Clock as 120 Frames/Sec */ + seps525_spi_write(dev, SEPS525_CLOCK_DIV, 0x90); + /* Set Reference Voltage Controlled by External Resister */ + seps525_spi_write(dev, SEPS525_IREF, 0x01); + + /* precharge time R G B */ + seps525_spi_write(dev, SEPS525_PRECHARGE_TIME_R, 0x04); + seps525_spi_write(dev, SEPS525_PRECHARGE_TIME_G, 0x05); + seps525_spi_write(dev, SEPS525_PRECHARGE_TIME_B, 0x05); + + /* precharge current R G B (uA) */ + seps525_spi_write(dev, SEPS525_PRECHARGE_CURRENT_R, 0x9D); + seps525_spi_write(dev, SEPS525_PRECHARGE_CURRENT_G, 0x8C); + seps525_spi_write(dev, SEPS525_PRECHARGE_CURRENT_B, 0x57); + + /* driving current R G B (uA) */ + seps525_spi_write(dev, SEPS525_DRIVING_CURRENT_R, 0x56); + seps525_spi_write(dev, SEPS525_DRIVING_CURRENT_G, 0x4D); + seps525_spi_write(dev, SEPS525_DRIVING_CURRENT_B, 0x46); + /* Set Color Sequence */ + seps525_spi_write(dev, SEPS525_DISPLAYMODE_SET, 0x00); + /* Set MCU Interface Mode */ + seps525_spi_write(dev, SEPS525_RGBIF, 0x01); + /* Set Memory Write Mode */ + seps525_spi_write(dev, SEPS525_MEMORY_WRITEMODE, 0x66); + /* 1/128 Duty (0x0F~0x7F) */ + seps525_spi_write(dev, SEPS525_DUTY, 0x7F); + /* Set Mapping RAM Display Start Line (0x00~0x7F) */ + seps525_spi_write(dev, SEPS525_DSL, 0x00); + /* Display On (0x00/0x01) */ + seps525_spi_write(dev, SEPS525_DISP_ONOFF, 0x01); + /* Set All Internal Register Value as Normal Mode */ + seps525_spi_write(dev, SEPS525_SOFT_RST, 0x00); + /* Set RGB Interface Polarity as Active Low */ + seps525_spi_write(dev, SEPS525_RGB_POL, 0x00); + + /* Enable access for data */ + (void)seps525_spi_write_cmd(dev, SEPS525_DDRAM_DATA_ACCESS_PORT); + + return 0; +} + +static int seps525_spi_startup(struct udevice *dev) +{ + struct seps525_priv *priv = dev_get_priv(dev); + int ret; + + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) + return ret; + + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) + return ret; + + ret = dm_spi_claim_bus(dev); + if (ret) { + dev_err(dev, "Failed to claim SPI bus: %d\n", ret); + return ret; + } + + ret = seps525_display_init(dev); + if (ret) + return ret; + + dm_spi_release_bus(dev); + + return 0; +} + +static int seps525_sync(struct udevice *vid) +{ + struct video_priv *uc_priv = dev_get_uclass_priv(vid); + struct seps525_priv *priv = dev_get_priv(vid); + struct udevice *dev = priv->dev; + int i, ret; + u8 data1, data2; + u8 *start = uc_priv->fb; + + ret = dm_spi_claim_bus(dev); + if (ret) { + dev_err(dev, "Failed to claim SPI bus: %d\n", ret); + return ret; + } + + /* start position X,Y */ + seps525_spi_write(dev, SEPS525_MEMORY_ACCESS_POINTER_X, 0); + seps525_spi_write(dev, SEPS525_MEMORY_ACCESS_POINTER_Y, 0); + + /* Enable access for data */ + (void)seps525_spi_write_cmd(dev, SEPS525_DDRAM_DATA_ACCESS_PORT); + + for (i = 0; i < (uc_priv->xsize * uc_priv->ysize); i++) { + data2 = *start++; + data1 = *start++; + (void)seps525_spi_write_data(dev, data1); + (void)seps525_spi_write_data(dev, data2); + } + + dm_spi_release_bus(dev); + + return 0; +} + +static int seps525_probe(struct udevice *dev) +{ + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct seps525_priv *priv = dev_get_priv(dev); + u32 buswidth; + int ret; + + buswidth = dev_read_u32_default(dev, "buswidth", 0); + if (buswidth != 8) { + dev_err(dev, "Only 8bit buswidth is supported now"); + return -EINVAL; + } + + ret = gpio_request_by_name(dev, "reset-gpios", 0, + &priv->reset_gpio, GPIOD_IS_OUT); + if (ret) { + dev_err(dev, "missing reset GPIO\n"); + return ret; + } + + ret = gpio_request_by_name(dev, "dc-gpios", 0, + &priv->dc_gpio, GPIOD_IS_OUT); + if (ret) { + dev_err(dev, "missing dc GPIO\n"); + return ret; + } + + uc_priv->bpix = VIDEO_BPP16; + uc_priv->xsize = WIDTH; + uc_priv->ysize = HEIGHT; + uc_priv->rot = 0; + + priv->dev = dev; + + ret = seps525_spi_startup(dev); + if (ret) + return ret; + + return 0; +} + +static int seps525_bind(struct udevice *dev) +{ + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + + plat->size = WIDTH * HEIGHT * 16; + + return 0; +} + +static const struct video_ops seps525_ops = { + .video_sync = seps525_sync, +}; + +static const struct udevice_id seps525_ids[] = { + { .compatible = "syncoam,seps525" }, + { } +}; + +U_BOOT_DRIVER(seps525_video) = { + .name = "seps525_video", + .id = UCLASS_VIDEO, + .of_match = seps525_ids, + .ops = &seps525_ops, + .platdata_auto_alloc_size = sizeof(struct video_uc_platdata), + .bind = seps525_bind, + .probe = seps525_probe, + .priv_auto_alloc_size = sizeof(struct seps525_priv), +}; From 5337663e5beb47e6dfe757417452a9e5de8128a1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 15 Dec 2020 15:12:09 +0100 Subject: [PATCH 18/19] video: Call video_sync in video_clear() There is a need to call sync when anybody asking for clearing display. For example via cls command. Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- drivers/video/video-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index 938e7d3713..21452a1cda 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -143,7 +143,7 @@ int video_clear(struct udevice *dev) if (ret) return ret; - return 0; + return video_sync(dev, false); } void video_set_default_colors(struct udevice *dev, bool invert) From 0109db1cd1e63b35c1c84d6bc2ccaa26aa6b7ce3 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 4 Jan 2021 13:42:20 +0100 Subject: [PATCH 19/19] xilinx: Fill git repository for Xilinx boards All Xilinx SoCs have repository location filled already but boards are covered by different fragment which is missing this link. The patch is extending description with adding proper link to the same repository. Reported-by: Heinrich Schuchardt Signed-off-by: Michal Simek --- board/xilinx/microblaze-generic/MAINTAINERS | 1 + board/xilinx/versal/MAINTAINERS | 1 + board/xilinx/zynq/MAINTAINERS | 1 + board/xilinx/zynqmp/MAINTAINERS | 1 + 4 files changed, 4 insertions(+) diff --git a/board/xilinx/microblaze-generic/MAINTAINERS b/board/xilinx/microblaze-generic/MAINTAINERS index 6796d4d51a..9a42a8b740 100644 --- a/board/xilinx/microblaze-generic/MAINTAINERS +++ b/board/xilinx/microblaze-generic/MAINTAINERS @@ -1,6 +1,7 @@ MICROBLAZE-GENERIC BOARD M: Michal Simek S: Maintained +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: board/xilinx/microblaze-generic/ F: include/configs/microblaze-generic.h F: configs/microblaze-generic_defconfig diff --git a/board/xilinx/versal/MAINTAINERS b/board/xilinx/versal/MAINTAINERS index 2d2b808245..0d40196ade 100644 --- a/board/xilinx/versal/MAINTAINERS +++ b/board/xilinx/versal/MAINTAINERS @@ -1,6 +1,7 @@ XILINX_VERSAL BOARDS M: Michal Simek S: Maintained +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/dts/versal* F: board/xilinx/versal/ F: include/configs/xilinx_versal* diff --git a/board/xilinx/zynq/MAINTAINERS b/board/xilinx/zynq/MAINTAINERS index 78bcd84d30..ce760ab02c 100644 --- a/board/xilinx/zynq/MAINTAINERS +++ b/board/xilinx/zynq/MAINTAINERS @@ -1,6 +1,7 @@ ZYNQ BOARD M: Michal Simek S: Maintained +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/dts/zynq-* F: board/xilinx/zynq/ F: include/configs/zynq*.h diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS index 9cd4f3f53e..a631b380bd 100644 --- a/board/xilinx/zynqmp/MAINTAINERS +++ b/board/xilinx/zynqmp/MAINTAINERS @@ -1,6 +1,7 @@ XILINX_ZYNQMP BOARDS M: Michal Simek S: Maintained +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/dts/zynqmp-* F: arch/arm/dts/avnet-ultra96* F: board/xilinx/common/