mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
- sync Amlogic G12A DT with linux 5.3-rc1
- add support for 4GiB DRAM memory - add support for Amlogic G12B based Odroid-N2 - small duplicate logic fix for gxbb clock driver -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAl1BkXMACgkQd9zb2sjI SdGd+Q/+IdXgTvox69NbfvhyA8d7GwhTWVIKgrF3NvHpxYqvvxmC7gTx1Qdh5sAO vyKsuygim9R/Rt7X7bzE/a1gKju/DpkxFJ0hx148xDJXmtzeBSWmDO/oOnZpUZRM aRUjncjxvMOZ3axtsWAZSiKqDF5i/K9Y3v/6JaLCs3WmVzlLrgANUSWqdC/Qc1Ka HLjem/ug3HK+o/zg0pXS3VguOTOMEV63hlWHlo2jKnxLmBpxcp1O7kH8noKR90+P x/byo+GAzayYv6oS0yeUz8YEXIMDVdkEX0eFzkRfe7ykz5lwGONdpLcdjmIIk6nO Kef7HNsRTb5ku9QPlgVLHodHNeGsV3axvmPLJQDki6/sgQmZSBWsUWPNt0yZuUjT gU2o7XoNmIh49hxk8ShDttGkCAYmacJwhQZ0TMV2q8q0YkDmeTWpzY5JIWq5VRLj 0W9moxSO5SieM0FSwR/v7J2egPrz0ocOSs7XpQqH7ZNduBjq0jHwhS7Yu8wcbXTA baBta3tBKJhjYpfPrexrWOw1NW2fwW5kJJpnMY68nDG/ygTb++syVvTjjiqTfemI kIs6aBZ0AEo7WMrehdtHRFmW9SQC6h5h0Ji7bR20TigSGLe+5f0R8tASDD+0FXLB KID+sigdyHxM9B6uACR1pOqCjEb+IyyFXJno38v7DjaW/IoyC3k= =Q5fc -----END PGP SIGNATURE----- Merge tag 'u-boot-amlogic-20190731' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - sync Amlogic G12A DT with linux 5.3-rc1 - add support for 4GiB DRAM memory - add support for Amlogic G12B based Odroid-N2 - small duplicate logic fix for gxbb clock driver
This commit is contained in:
Tom Rini
commit
bbaf56eda0
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@ -135,7 +135,8 @@ dtb-$(CONFIG_ARCH_MESON) += \
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meson-gxl-s905x-khadas-vim.dtb \
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meson-gxm-khadas-vim2.dtb \
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meson-axg-s400.dtb \
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meson-g12a-u200.dtb
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meson-g12a-u200.dtb \
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meson-g12b-odroid-n2.dtb
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dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
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tegra20-medcom-wide.dtb \
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tegra20-paz00.dtb \
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@ -1,216 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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/ {
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soc {
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ethmac: ethernet@ff3f0000 {
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compatible = "amlogic,meson-axg-dwmac", "snps,dwmac-3.710",
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"snps,dwmac";
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reg = <0x0 0xff3f0000 0x0 0x10000
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0x0 0xff634540 0x0 0x8>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clocks = <&clkc CLKID_ETH>,
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<&clkc CLKID_FCLK_DIV2>,
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<&clkc CLKID_MPLL2>;
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clock-names = "stmmaceth", "clkin0", "clkin1";
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status = "disabled";
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mdio0: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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};
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};
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sd_emmc_a: sd@ffe03000 {
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compatible = "amlogic,meson-axg-mmc";
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reg = <0x0 0xffe03000 0x0 0x800>;
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interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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clocks = <&clkc CLKID_SD_EMMC_A>,
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<&clkc CLKID_SD_EMMC_A_CLK0>,
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<&clkc CLKID_FCLK_DIV2>;
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clock-names = "core", "clkin0", "clkin1";
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resets = <&reset RESET_SD_EMMC_A>;
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};
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sd_emmc_b: sd@ffe05000 {
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compatible = "amlogic,meson-axg-mmc";
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reg = <0x0 0xffe05000 0x0 0x800>;
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interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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clocks = <&clkc CLKID_SD_EMMC_B>,
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<&clkc CLKID_SD_EMMC_B_CLK0>,
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<&clkc CLKID_FCLK_DIV2>;
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clock-names = "core", "clkin0", "clkin1";
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resets = <&reset RESET_SD_EMMC_B>;
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};
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sd_emmc_c: mmc@ffe07000 {
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compatible = "amlogic,meson-axg-mmc";
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reg = <0x0 0xffe07000 0x0 0x800>;
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interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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clocks = <&clkc CLKID_SD_EMMC_C>,
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<&clkc CLKID_SD_EMMC_C_CLK0>,
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<&clkc CLKID_FCLK_DIV2>;
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clock-names = "core", "clkin0", "clkin1";
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resets = <&reset RESET_SD_EMMC_C>;
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};
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};
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};
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&periphs_pinctrl {
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emmc_pins: emmc {
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mux {
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groups = "emmc_nand_d0",
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"emmc_nand_d1",
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"emmc_nand_d2",
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"emmc_nand_d3",
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"emmc_nand_d4",
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"emmc_nand_d5",
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"emmc_nand_d6",
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"emmc_nand_d7",
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"emmc_clk",
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"emmc_cmd";
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function = "emmc";
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bias-pull-up;
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};
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};
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emmc_ds_pins: emmc-ds {
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mux {
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groups = "emmc_nand_ds";
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function = "emmc";
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bias-pull-down;
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};
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};
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emmc_clk_gate_pins: emmc_clk_gate {
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mux {
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groups = "BOOT_8";
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function = "gpio_periphs";
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bias-pull-down;
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};
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};
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eth_leds_pins: eth-leds {
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mux {
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groups = "eth_link_led",
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"eth_act_led";
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function = "eth";
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bias-disable;
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};
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};
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eth_rmii_pins: eth-rmii {
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mux {
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groups = "eth_mdio",
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"eth_mdc",
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"eth_rgmii_rx_clk",
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"eth_rx_dv",
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"eth_rxd0",
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"eth_rxd1",
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"eth_txen",
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"eth_txd0",
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"eth_txd1";
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function = "eth";
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bias-disable;
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};
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};
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eth_rgmii_pins: eth-rgmii {
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mux {
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groups = "eth_rxd2_rgmii",
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"eth_rxd3_rgmii",
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"eth_rgmii_tx_clk",
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"eth_txd2_rgmii",
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"eth_txd3_rgmii";
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function = "eth";
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bias-disable;
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};
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};
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sdcard_c_pins: sdcard_c {
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mux {
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groups = "sdcard_d0_c",
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"sdcard_d1_c",
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"sdcard_d2_c",
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"sdcard_d3_c",
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"sdcard_cmd_c",
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"sdcard_clk_c";
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function = "sdcard";
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bias-pull-up;
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};
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};
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sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
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mux {
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groups = "GPIOC_4";
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function = "gpio_periphs";
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bias-pull-down;
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};
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};
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sdcard_z_pins: sdcard_z {
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mux {
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groups = "sdcard_d0_z",
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"sdcard_d1_z",
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"sdcard_d2_z",
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"sdcard_d3_z",
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"sdcard_cmd_z",
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"sdcard_clk_z";
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function = "sdcard";
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bias-pull-up;
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};
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};
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sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
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mux {
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groups = "GPIOZ_6";
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function = "gpio_periphs";
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bias-pull-down;
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};
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};
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};
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&periphs {
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eth_phy: mdio-multiplexer@4c000 {
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compatible = "amlogic,g12a-mdio-mux";
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reg = <0x0 0x4c000 0x0 0xa4>;
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clocks = <&clkc CLKID_ETH_PHY>,
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<&xtal>,
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<&clkc CLKID_MPLL_5OM>;
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clock-names = "pclk", "clkin0", "clkin1";
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mdio-parent-bus = <&mdio0>;
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#address-cells = <1>;
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#size-cells = <0>;
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ext_mdio: mdio@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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int_mdio: mdio@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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internal_ephy: ethernet_phy@8 {
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compatible = "ethernet-phy-id0180.3300",
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"ethernet-phy-ieee802.3-c22";
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reg = <8>;
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max-speed = <100>;
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/* FIXME: Add irq support */
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};
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};
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};
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};
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@ -1,63 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include "meson-g12a-u-boot.dtsi"
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/ {
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aliases {
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ethernet0 = ðmac;
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};
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emmc_pwrseq: emmc-pwrseq {
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compatible = "mmc-pwrseq-emmc";
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reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
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};
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};
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ðmac {
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status = "okay";
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pinctrl-0 = <ð_leds_pins>;
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pinctrl-names = "default";
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phy-handle = <&internal_ephy>;
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phy-mode = "rmii";
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};
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/* SD card */
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&sd_emmc_b {
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status = "okay";
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pinctrl-0 = <&sdcard_c_pins>;
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pinctrl-1 = <&sdcard_clk_gate_c_pins>;
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pinctrl-names = "default", "clk-gate";
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bus-width = <4>;
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cap-sd-highspeed;
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max-frequency = <50000000>;
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disable-wp;
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cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
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vmmc-supply = <&vddao_3v3>;
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vqmmc-supply = <&vddao_3v3>;
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};
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/* eMMC */
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&sd_emmc_c {
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status = "okay";
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pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
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pinctrl-1 = <&emmc_clk_gate_pins>;
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pinctrl-names = "default", "clk-gate";
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bus-width = <8>;
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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max-frequency = <200000000>;
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disable-wp;
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mmc-pwrseq = <&emmc_pwrseq>;
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vmmc-supply = <&vcc_3v3>;
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vqmmc-supply = <&flash_1v8>;
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};
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@ -15,14 +15,12 @@
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aliases {
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serial0 = &uart_AO;
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ethernet0 = ðmac;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x40000000>;
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};
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cvbs-connector {
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compatible = "composite-video-connector";
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@ -34,13 +32,9 @@
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};
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};
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flash_1v8: regulator-flash_1v8 {
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compatible = "regulator-fixed";
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regulator-name = "FLASH_1V8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&vcc_3v3>;
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regulator-always-on;
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emmc_pwrseq: emmc-pwrseq {
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compatible = "mmc-pwrseq-emmc";
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reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
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};
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|
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hdmi-connector {
|
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@ -54,6 +48,20 @@
|
|||
};
|
||||
};
|
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|
||||
memory@0 {
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||||
device_type = "memory";
|
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reg = <0x0 0x0 0x0 0x40000000>;
|
||||
};
|
||||
|
||||
flash_1v8: regulator-flash_1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "FLASH_1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_3v3>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
main_12v: regulator-main_12v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "12V";
|
||||
|
|
@ -62,6 +70,17 @@
|
|||
regulator-always-on;
|
||||
};
|
||||
|
||||
usb_pwr_en: regulator-usb_pwr_en {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "USB_PWR_EN";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc_5v>;
|
||||
|
||||
gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vcc_1v8: regulator-vcc_1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_1V8";
|
||||
|
|
@ -92,17 +111,6 @@
|
|||
enable-active-high;
|
||||
};
|
||||
|
||||
usb_pwr_en: regulator-usb_pwr_en {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "USB_PWR_EN";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc_5v>;
|
||||
|
||||
gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vddao_1v8: regulator-vddao_1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDDAO_1V8";
|
||||
|
|
@ -143,6 +151,12 @@
|
|||
};
|
||||
};
|
||||
|
||||
ðmac {
|
||||
status = "okay";
|
||||
phy-handle = <&internal_ephy>;
|
||||
phy-mode = "rmii";
|
||||
};
|
||||
|
||||
&hdmi_tx {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
|
||||
|
|
@ -156,6 +170,70 @@
|
|||
};
|
||||
};
|
||||
|
||||
&ir {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&remote_input_ao_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
/* i2c Touch */
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&i2c0_sda_z0_pins>, <&i2c0_sck_z1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
/* i2c CM */
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&i2c2_sda_z_pins>, <&i2c2_sck_z_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
/* i2c Audio */
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
/* SD card */
|
||||
&sd_emmc_b {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&sdcard_c_pins>;
|
||||
pinctrl-1 = <&sdcard_clk_gate_c_pins>;
|
||||
pinctrl-names = "default", "clk-gate";
|
||||
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
max-frequency = <50000000>;
|
||||
disable-wp;
|
||||
|
||||
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <&vddao_3v3>;
|
||||
vqmmc-supply = <&vddao_3v3>;
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&sd_emmc_c {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
|
||||
pinctrl-1 = <&emmc_clk_gate_pins>;
|
||||
pinctrl-names = "default", "clk-gate";
|
||||
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
disable-wp;
|
||||
|
||||
mmc-pwrseq = <&emmc_pwrseq>;
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
vqmmc-supply = <&flash_1v8>;
|
||||
};
|
||||
|
||||
&uart_AO {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&uart_ao_a_pins>;
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
386
arch/arm/dts/meson-g12b-odroid-n2.dts
Normal file
386
arch/arm/dts/meson-g12b-odroid-n2.dts
Normal file
|
|
@ -0,0 +1,386 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "meson-g12b.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/meson-g12a-gpio.h>
|
||||
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
|
||||
|
||||
/ {
|
||||
compatible = "hardkernel,odroid-n2", "amlogic,g12b";
|
||||
model = "Hardkernel ODROID-N2";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart_AO;
|
||||
ethernet0 = ðmac;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x40000000>;
|
||||
};
|
||||
|
||||
emmc_pwrseq: emmc-pwrseq {
|
||||
compatible = "mmc-pwrseq-emmc";
|
||||
reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
blue {
|
||||
label = "n2:blue";
|
||||
gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
tflash_vdd: regulator-tflash_vdd {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "TFLASH_VDD";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
tf_io: gpio-regulator-tf_io {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "TF_IO";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <0>;
|
||||
|
||||
states = <3300000 0
|
||||
1800000 1>;
|
||||
};
|
||||
|
||||
flash_1v8: regulator-flash_1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "FLASH_1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_3v3>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
main_12v: regulator-main_12v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "12V";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_5v: regulator-vcc_5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "5V";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <&main_12v>;
|
||||
};
|
||||
|
||||
vcc_1v8: regulator-vcc_1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_3v3>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_3v3: regulator-vcc_3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vddao_3v3>;
|
||||
regulator-always-on;
|
||||
/* FIXME: actually controlled by VDDCPU_B_EN */
|
||||
};
|
||||
|
||||
hub_5v: regulator-hub_5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "HUB_5V";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc_5v>;
|
||||
|
||||
/* Connected to the Hub CHIPENABLE, LOW sets low power state */
|
||||
gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
usb_pwr_en: regulator-usb_pwr_en {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "USB_PWR_EN";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc_5v>;
|
||||
|
||||
/* Connected to the microUSB port power enable */
|
||||
gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vddao_1v8: regulator-vddao_1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDDAO_1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vddao_3v3>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vddao_3v3: regulator-vddao_3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDDAO_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&main_12v>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
hdmi-connector {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_connector_in: endpoint {
|
||||
remote-endpoint = <&hdmi_tx_tmds_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "amlogic,axg-sound-card";
|
||||
model = "G12A-ODROIDN2";
|
||||
audio-aux-devs = <&tdmout_b>;
|
||||
audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
|
||||
"TDMOUT_B IN 1", "FRDDR_B OUT 1",
|
||||
"TDMOUT_B IN 2", "FRDDR_C OUT 1",
|
||||
"TDM_B Playback", "TDMOUT_B OUT";
|
||||
|
||||
assigned-clocks = <&clkc CLKID_MPLL2>,
|
||||
<&clkc CLKID_MPLL0>,
|
||||
<&clkc CLKID_MPLL1>;
|
||||
assigned-clock-parents = <0>, <0>, <0>;
|
||||
assigned-clock-rates = <294912000>,
|
||||
<270950400>,
|
||||
<393216000>;
|
||||
status = "okay";
|
||||
|
||||
dai-link-0 {
|
||||
sound-dai = <&frddr_a>;
|
||||
};
|
||||
|
||||
dai-link-1 {
|
||||
sound-dai = <&frddr_b>;
|
||||
};
|
||||
|
||||
dai-link-2 {
|
||||
sound-dai = <&frddr_c>;
|
||||
};
|
||||
|
||||
/* 8ch hdmi interface */
|
||||
dai-link-3 {
|
||||
sound-dai = <&tdmif_b>;
|
||||
dai-format = "i2s";
|
||||
dai-tdm-slot-tx-mask-0 = <1 1>;
|
||||
dai-tdm-slot-tx-mask-1 = <1 1>;
|
||||
dai-tdm-slot-tx-mask-2 = <1 1>;
|
||||
dai-tdm-slot-tx-mask-3 = <1 1>;
|
||||
mclk-fs = <256>;
|
||||
|
||||
codec {
|
||||
sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
|
||||
};
|
||||
};
|
||||
|
||||
/* hdmi glue */
|
||||
dai-link-4 {
|
||||
sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
|
||||
|
||||
codec {
|
||||
sound-dai = <&hdmi_tx>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&arb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cec_AO {
|
||||
pinctrl-0 = <&cec_ao_a_h_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
hdmi-phandle = <&hdmi_tx>;
|
||||
};
|
||||
|
||||
&cecb_AO {
|
||||
pinctrl-0 = <&cec_ao_b_h_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
hdmi-phandle = <&hdmi_tx>;
|
||||
};
|
||||
|
||||
&clkc_audio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ext_mdio {
|
||||
external_phy: ethernet-phy@0 {
|
||||
/* Realtek RTL8211F (0x001cc916) */
|
||||
reg = <0>;
|
||||
max-speed = <1000>;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
/* MAC_INTR on GPIOZ_14 */
|
||||
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
ðmac {
|
||||
pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&external_phy>;
|
||||
amlogic,tx-delay-ns = <2>;
|
||||
};
|
||||
|
||||
&frddr_a {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&frddr_b {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&frddr_c {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio {
|
||||
/*
|
||||
* WARNING: The USB Hub on the Odroid-N2 needs a reset signal
|
||||
* to be turned high in order to be detected by the USB Controller
|
||||
* This signal should be handled by a USB specific power sequence
|
||||
* in order to reset the Hub when USB bus is powered down.
|
||||
*/
|
||||
usb-hub {
|
||||
gpio-hog;
|
||||
gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "usb-hub-reset";
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_tx {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
|
||||
pinctrl-names = "default";
|
||||
hdmi-supply = <&vcc_5v>;
|
||||
};
|
||||
|
||||
&hdmi_tx_tmds_port {
|
||||
hdmi_tx_tmds_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&ir {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&remote_input_ao_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
/* SD card */
|
||||
&sd_emmc_b {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&sdcard_c_pins>;
|
||||
pinctrl-1 = <&sdcard_clk_gate_c_pins>;
|
||||
pinctrl-names = "default", "clk-gate";
|
||||
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
max-frequency = <50000000>;
|
||||
disable-wp;
|
||||
|
||||
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <&tflash_vdd>;
|
||||
vqmmc-supply = <&tf_io>;
|
||||
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&sd_emmc_c {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
|
||||
pinctrl-1 = <&emmc_clk_gate_pins>;
|
||||
pinctrl-names = "default", "clk-gate";
|
||||
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
max-frequency = <200000000>;
|
||||
disable-wp;
|
||||
|
||||
mmc-pwrseq = <&emmc_pwrseq>;
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
vqmmc-supply = <&flash_1v8>;
|
||||
};
|
||||
|
||||
&tdmif_b {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tdmout_b {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tohdmitx {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart_AO {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&uart_ao_a_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
vbus-supply = <&usb_pwr_en>;
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
phy-supply = <&vcc_5v>;
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
/* Enable the hub which is connected to this port */
|
||||
phy-supply = <&hub_5v>;
|
||||
};
|
||||
82
arch/arm/dts/meson-g12b.dtsi
Normal file
82
arch/arm/dts/meson-g12b.dtsi
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
#include "meson-g12a.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "amlogic,g12b";
|
||||
|
||||
cpus {
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&cpu100>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu101>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&cpu102>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&cpu103>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/delete-node/ cpu@2;
|
||||
/delete-node/ cpu@3;
|
||||
|
||||
cpu100: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a73";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
cpu101: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a73";
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
cpu102: cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a73";
|
||||
reg = <0x0 0x102>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
cpu103: cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a73";
|
||||
reg = <0x0 0x103>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&clkc {
|
||||
compatible = "amlogic,g12b-clkc";
|
||||
};
|
||||
|
|
@ -62,21 +62,21 @@ void meson_init_reserved_memory(void *fdt)
|
|||
phys_size_t get_effective_memsize(void)
|
||||
{
|
||||
/* Size is reported in MiB, convert it in bytes */
|
||||
return ((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK)
|
||||
>> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M;
|
||||
return min(((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK)
|
||||
>> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M, 0xf5000000);
|
||||
}
|
||||
|
||||
static struct mm_region g12a_mem_map[] = {
|
||||
{
|
||||
.virt = 0x0UL,
|
||||
.phys = 0x0UL,
|
||||
.size = 0x80000000UL,
|
||||
.size = 0xf5000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
}, {
|
||||
.virt = 0xf0000000UL,
|
||||
.phys = 0xf0000000UL,
|
||||
.size = 0x10000000UL,
|
||||
.virt = 0xf5000000UL,
|
||||
.phys = 0xf5000000UL,
|
||||
.size = 0x0b000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
|
|
@ -129,6 +129,7 @@ void meson_eth_init(phy_interface_t mode, unsigned int flags)
|
|||
G12A_ETH_REG_0_TX_RATIO(4) |
|
||||
G12A_ETH_REG_0_PHY_CLK_EN |
|
||||
G12A_ETH_REG_0_CLK_EN);
|
||||
g12a_enable_external_mdio();
|
||||
break;
|
||||
|
||||
case PHY_INTERFACE_MODE_RMII:
|
||||
|
|
|
|||
6
board/amlogic/w400/MAINTAINERS
Normal file
6
board/amlogic/w400/MAINTAINERS
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
W400
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
|
||||
S: Maintained
|
||||
L: u-boot-amlogic@groups.io
|
||||
F: board/amlogic/w400/
|
||||
F: configs/odroid-n2_defconfig
|
||||
6
board/amlogic/w400/Makefile
Normal file
6
board/amlogic/w400/Makefile
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2019 BayLibre, SAS
|
||||
# Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
|
||||
obj-y := w400.o
|
||||
130
board/amlogic/w400/README.odroid-n2
Normal file
130
board/amlogic/w400/README.odroid-n2
Normal file
|
|
@ -0,0 +1,130 @@
|
|||
U-Boot for ODROID-N2
|
||||
====================
|
||||
|
||||
ODROID-N2 is a single board computer manufactured by Hardkernel
|
||||
Co. Ltd with the following specifications:
|
||||
|
||||
- Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
|
||||
- 4GB DDR4 SDRAM
|
||||
- Gigabit Ethernet
|
||||
- HDMI 2.1 4K/60Hz display
|
||||
- 40-pin GPIO header
|
||||
- 4 x USB 3.0 Host, 1 x USB OTG
|
||||
- eMMC, microSD
|
||||
- Infrared receiver
|
||||
|
||||
Schematics are available on the manufacturer website.
|
||||
|
||||
Currently the u-boot port supports the following devices:
|
||||
- serial
|
||||
- eMMC, microSD
|
||||
- Ethernet
|
||||
- I2C
|
||||
- Regulators
|
||||
- Reset controller
|
||||
- Clock controller
|
||||
- ADC
|
||||
|
||||
u-boot compilation
|
||||
==================
|
||||
|
||||
> export ARCH=arm
|
||||
> export CROSS_COMPILE=aarch64-none-elf-
|
||||
> make odroid-n2_defconfig
|
||||
> make
|
||||
|
||||
Image creation
|
||||
==============
|
||||
|
||||
Amlogic doesn't provide sources for the firmware and for tools needed
|
||||
to create the bootloader image, so it is necessary to obtain them from
|
||||
the git tree published by the board vendor:
|
||||
|
||||
> wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
|
||||
> wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
|
||||
> tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
|
||||
> tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
|
||||
> export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
|
||||
|
||||
> DIR=odroid-n2
|
||||
> git clone --depth 1 \
|
||||
https://github.com/hardkernel/u-boot.git -b odroidn2-v2015.01 \
|
||||
$DIR
|
||||
|
||||
> cd odroid-n2
|
||||
> make odroidn2_defconfig
|
||||
> make
|
||||
> export UBOOTDIR=$PWD
|
||||
|
||||
Go back to mainline U-Boot source tree then :
|
||||
> mkdir fip
|
||||
|
||||
> wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
|
||||
> cp $UBOOTDIR/build/scp_task/bl301.bin fip/
|
||||
> cp $UBOOTDIR/build/board/hardkernel/odroidn2/firmware/acs.bin fip/
|
||||
> cp $UBOOTDIR/fip/g12b/bl2.bin fip/
|
||||
> cp $UBOOTDIR/fip/g12b/bl30.bin fip/
|
||||
> cp $UBOOTDIR/fip/g12b/bl31.img fip/
|
||||
> cp $UBOOTDIR/fip/g12b/ddr3_1d.fw fip/
|
||||
> cp $UBOOTDIR/fip/g12b/ddr4_1d.fw fip/
|
||||
> cp $UBOOTDIR/fip/g12b/ddr4_2d.fw fip/
|
||||
> cp $UBOOTDIR/fip/g12b/diag_lpddr4.fw fip/
|
||||
> cp $UBOOTDIR/fip/g12b/lpddr4_1d.fw fip/
|
||||
> cp $UBOOTDIR/fip/g12b/lpddr4_2d.fw fip/
|
||||
> cp $UBOOTDIR/fip/g12b/piei.fw fip/
|
||||
> cp $UBOOTDIR/fip/g12b/aml_ddr.fw fip/
|
||||
> cp u-boot.bin fip/bl33.bin
|
||||
|
||||
> sh fip/blx_fix.sh \
|
||||
fip/bl30.bin \
|
||||
fip/zero_tmp \
|
||||
fip/bl30_zero.bin \
|
||||
fip/bl301.bin \
|
||||
fip/bl301_zero.bin \
|
||||
fip/bl30_new.bin \
|
||||
bl30
|
||||
|
||||
> sh fip/blx_fix.sh \
|
||||
fip/bl2.bin \
|
||||
fip/zero_tmp \
|
||||
fip/bl2_zero.bin \
|
||||
fip/acs.bin \
|
||||
fip/bl21_zero.bin \
|
||||
fip/bl2_new.bin \
|
||||
bl2
|
||||
|
||||
> $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
|
||||
--output fip/bl30_new.bin.g12a.enc \
|
||||
--level v3
|
||||
> $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
|
||||
--output fip/bl30_new.bin.enc \
|
||||
--level v3 --type bl30
|
||||
> $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
|
||||
--output fip/bl31.img.enc \
|
||||
--level v3 --type bl31
|
||||
> $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
|
||||
--output fip/bl33.bin.enc \
|
||||
--level v3 --type bl33 --compress lz4
|
||||
> $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
|
||||
--output fip/bl2.n.bin.sig
|
||||
> $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \
|
||||
--output fip/u-boot.bin \
|
||||
--bl2 fip/bl2.n.bin.sig \
|
||||
--bl30 fip/bl30_new.bin.enc \
|
||||
--bl31 fip/bl31.img.enc \
|
||||
--bl33 fip/bl33.bin.enc \
|
||||
--ddrfw1 fip/ddr4_1d.fw \
|
||||
--ddrfw2 fip/ddr4_2d.fw \
|
||||
--ddrfw3 fip/ddr3_1d.fw \
|
||||
--ddrfw4 fip/piei.fw \
|
||||
--ddrfw5 fip/lpddr4_1d.fw \
|
||||
--ddrfw6 fip/lpddr4_2d.fw \
|
||||
--ddrfw7 fip/diag_lpddr4.fw \
|
||||
--ddrfw8 fip/aml_ddr.fw \
|
||||
--level v3
|
||||
|
||||
and then write the image to SD with:
|
||||
|
||||
> DEV=/dev/your_sd_device
|
||||
> dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
|
||||
> dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
|
||||
130
board/amlogic/w400/README.w400
Normal file
130
board/amlogic/w400/README.w400
Normal file
|
|
@ -0,0 +1,130 @@
|
|||
U-Boot for Amlogic W400
|
||||
=======================
|
||||
|
||||
U200 is a reference board manufactured by Amlogic with the following
|
||||
specifications:
|
||||
|
||||
- Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
|
||||
- 2GB DDR4 SDRAM
|
||||
- 10/100 Ethernet (Internal PHY)
|
||||
- 1 x USB 3.0 Host
|
||||
- eMMC
|
||||
- SDcard
|
||||
- Infrared receiver
|
||||
- SDIO WiFi Module
|
||||
- MIPI DSI Connector
|
||||
- Audio HAT Connector
|
||||
- PCI-E M.2 Connector
|
||||
|
||||
Schematics are available from Amlogic on demand.
|
||||
|
||||
Currently the u-boot port supports the following devices:
|
||||
- serial
|
||||
- Ethernet
|
||||
- Regulators
|
||||
- Clock controller
|
||||
|
||||
u-boot compilation
|
||||
==================
|
||||
|
||||
> export ARCH=arm
|
||||
> export CROSS_COMPILE=aarch64-none-elf-
|
||||
> make w400_defconfig
|
||||
> make
|
||||
|
||||
Image creation
|
||||
==============
|
||||
|
||||
Amlogic doesn't provide sources for the firmware and for tools needed
|
||||
to create the bootloader image, so it is necessary to obtain them from
|
||||
the git tree published by the board vendor:
|
||||
|
||||
> wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
|
||||
> wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
|
||||
> tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
|
||||
> tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
|
||||
> export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
|
||||
> git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot
|
||||
> cd amlogic-u-boot
|
||||
> make g12b_w400_v1_defconfig
|
||||
> make
|
||||
> export UBOOTDIR=$PWD
|
||||
|
||||
Download the latest Amlogic Buildroot package, and extract it :
|
||||
> wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz
|
||||
> tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader
|
||||
> export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
|
||||
> export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
|
||||
|
||||
Go back to mainline U-Boot source tree then :
|
||||
> mkdir fip
|
||||
|
||||
> wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
|
||||
> cp $UBOOTDIR/build/scp_task/bl301.bin fip/
|
||||
> cp $UBOOTDIR/build/board/amlogic/g12b_w400_v1/firmware/acs.bin fip/
|
||||
> cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12b/bl2.bin fip/
|
||||
> cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12b/bl30.bin fip/
|
||||
> cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12b/bl31.img fip/
|
||||
> cp $FIPDIR/g12b/ddr3_1d.fw fip/
|
||||
> cp $FIPDIR/g12b/ddr4_1d.fw fip/
|
||||
> cp $FIPDIR/g12b/ddr4_2d.fw fip/
|
||||
> cp $FIPDIR/g12b/diag_lpddr4.fw fip/
|
||||
> cp $FIPDIR/g12b/lpddr4_1d.fw fip/
|
||||
> cp $FIPDIR/g12b/lpddr4_2d.fw fip/
|
||||
> cp $FIPDIR/g12b/piei.fw fip/
|
||||
> cp $FIPDIR/g12b/aml_ddr.fw fip/
|
||||
> cp u-boot.bin fip/bl33.bin
|
||||
|
||||
> sh fip/blx_fix.sh \
|
||||
fip/bl30.bin \
|
||||
fip/zero_tmp \
|
||||
fip/bl30_zero.bin \
|
||||
fip/bl301.bin \
|
||||
fip/bl301_zero.bin \
|
||||
fip/bl30_new.bin \
|
||||
bl30
|
||||
|
||||
> sh fip/blx_fix.sh \
|
||||
fip/bl2.bin \
|
||||
fip/zero_tmp \
|
||||
fip/bl2_zero.bin \
|
||||
fip/acs.bin \
|
||||
fip/bl21_zero.bin \
|
||||
fip/bl2_new.bin \
|
||||
bl2
|
||||
|
||||
> $FIPDIR/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
|
||||
--output fip/bl30_new.bin.g12a.enc \
|
||||
--level v3
|
||||
> $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
|
||||
--output fip/bl30_new.bin.enc \
|
||||
--level v3 --type bl30
|
||||
> $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
|
||||
--output fip/bl31.img.enc \
|
||||
--level v3 --type bl31
|
||||
> $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
|
||||
--output fip/bl33.bin.enc \
|
||||
--level v3 --type bl33
|
||||
> $FIPDIR/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
|
||||
--output fip/bl2.n.bin.sig
|
||||
> $FIPDIR/g12b/aml_encrypt_g12b --bootmk \
|
||||
--output fip/u-boot.bin \
|
||||
--bl2 fip/bl2.n.bin.sig \
|
||||
--bl30 fip/bl30_new.bin.enc \
|
||||
--bl31 fip/bl31.img.enc \
|
||||
--bl33 fip/bl33.bin.enc \
|
||||
--ddrfw1 fip/ddr4_1d.fw \
|
||||
--ddrfw2 fip/ddr4_2d.fw \
|
||||
--ddrfw3 fip/ddr3_1d.fw \
|
||||
--ddrfw4 fip/piei.fw \
|
||||
--ddrfw5 fip/lpddr4_1d.fw \
|
||||
--ddrfw6 fip/lpddr4_2d.fw \
|
||||
--ddrfw7 fip/diag_lpddr4.fw \
|
||||
--ddrfw8 fip/aml_ddr.fw \
|
||||
--level v3
|
||||
|
||||
and then write the image to SD with:
|
||||
|
||||
> DEV=/dev/your_sd_device
|
||||
> dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
|
||||
> dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
|
||||
18
board/amlogic/w400/w400.c
Normal file
18
board/amlogic/w400/w400.c
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2016 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <environment.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/eth.h>
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
56
configs/odroid-n2_defconfig
Normal file
56
configs/odroid-n2_defconfig
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MESON=y
|
||||
CONFIG_SYS_TEXT_BASE=0x01000000
|
||||
CONFIG_MESON_G12A=y
|
||||
CONFIG_SYS_BOARD="w400"
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_DEBUG_UART_BASE=0xff803000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_IDENT_STRING=" odroid-n2"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_MISC_INIT_R=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
# CONFIG_CMD_BDI is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-odroid-n2"
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_MESON_GX=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_MESON_G12A=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_DEBUG_UART_MESON=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_DEBUG_UART_SKIP_INIT=y
|
||||
CONFIG_MESON_SERIAL=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_HOST=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_PHY=y
|
||||
CONFIG_MESON_G12A_USB_PHY=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_GADGET_DWC2_OTG=y
|
||||
CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_MESON_G12A=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
|
||||
|
|
@ -823,10 +823,7 @@ static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
|
|||
case CLKID_MPLL1:
|
||||
case CLKID_MPLL2:
|
||||
case CLKID_CLK81:
|
||||
if (current_rate != rate)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
return -EINVAL;
|
||||
case CLKID_VPU:
|
||||
return meson_clk_set_rate_by_id(clk,
|
||||
meson_mux_get_parent(clk, CLKID_VPU), rate,
|
||||
|
|
|
|||
|
|
@ -21,6 +21,11 @@
|
|||
#define CLKID_AO_SAR_ADC_SEL 8
|
||||
#define CLKID_AO_SAR_ADC_DIV 9
|
||||
#define CLKID_AO_SAR_ADC_CLK 10
|
||||
#define CLKID_AO_ALT_XTAL 11
|
||||
#define CLKID_AO_CTS_OSCIN 11
|
||||
#define CLKID_AO_32K_PRE 12
|
||||
#define CLKID_AO_32K_DIV 13
|
||||
#define CLKID_AO_32K_SEL 14
|
||||
#define CLKID_AO_32K 15
|
||||
#define CLKID_AO_CTS_RTC_OSCIN 16
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -7,26 +7,6 @@
|
|||
#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
|
||||
#define __AXG_AUDIO_CLKC_BINDINGS_H
|
||||
|
||||
#define AUD_CLKID_SLV_SCLK0 9
|
||||
#define AUD_CLKID_SLV_SCLK1 10
|
||||
#define AUD_CLKID_SLV_SCLK2 11
|
||||
#define AUD_CLKID_SLV_SCLK3 12
|
||||
#define AUD_CLKID_SLV_SCLK4 13
|
||||
#define AUD_CLKID_SLV_SCLK5 14
|
||||
#define AUD_CLKID_SLV_SCLK6 15
|
||||
#define AUD_CLKID_SLV_SCLK7 16
|
||||
#define AUD_CLKID_SLV_SCLK8 17
|
||||
#define AUD_CLKID_SLV_SCLK9 18
|
||||
#define AUD_CLKID_SLV_LRCLK0 19
|
||||
#define AUD_CLKID_SLV_LRCLK1 20
|
||||
#define AUD_CLKID_SLV_LRCLK2 21
|
||||
#define AUD_CLKID_SLV_LRCLK3 22
|
||||
#define AUD_CLKID_SLV_LRCLK4 23
|
||||
#define AUD_CLKID_SLV_LRCLK5 24
|
||||
#define AUD_CLKID_SLV_LRCLK6 25
|
||||
#define AUD_CLKID_SLV_LRCLK7 26
|
||||
#define AUD_CLKID_SLV_LRCLK8 27
|
||||
#define AUD_CLKID_SLV_LRCLK9 28
|
||||
#define AUD_CLKID_DDR_ARB 29
|
||||
#define AUD_CLKID_PDM 30
|
||||
#define AUD_CLKID_TDMIN_A 31
|
||||
|
|
@ -90,5 +70,15 @@
|
|||
#define AUD_CLKID_TDMOUT_A_LRCLK 134
|
||||
#define AUD_CLKID_TDMOUT_B_LRCLK 135
|
||||
#define AUD_CLKID_TDMOUT_C_LRCLK 136
|
||||
#define AUD_CLKID_SPDIFOUT_B 151
|
||||
#define AUD_CLKID_SPDIFOUT_B_CLK 152
|
||||
#define AUD_CLKID_TDM_MCLK_PAD0 155
|
||||
#define AUD_CLKID_TDM_MCLK_PAD1 156
|
||||
#define AUD_CLKID_TDM_LRCLK_PAD0 157
|
||||
#define AUD_CLKID_TDM_LRCLK_PAD1 158
|
||||
#define AUD_CLKID_TDM_LRCLK_PAD2 159
|
||||
#define AUD_CLKID_TDM_SCLK_PAD0 160
|
||||
#define AUD_CLKID_TDM_SCLK_PAD1 161
|
||||
#define AUD_CLKID_TDM_SCLK_PAD2 162
|
||||
|
||||
#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
|
||||
|
|
|
|||
|
|
@ -130,11 +130,12 @@
|
|||
#define CLKID_MALI_1_SEL 172
|
||||
#define CLKID_MALI_1 174
|
||||
#define CLKID_MALI 175
|
||||
#define CLKID_MPLL_5OM 177
|
||||
#define CLKID_MPLL_50M 177
|
||||
#define CLKID_CPU_CLK 187
|
||||
#define CLKID_PCIE_PLL 201
|
||||
#define CLKID_VDEC_1 204
|
||||
#define CLKID_VDEC_HEVC 207
|
||||
#define CLKID_VDEC_HEVCF 210
|
||||
#define CLKID_TS 212
|
||||
|
||||
#endif /* __G12A_CLKC_H */
|
||||
|
|
|
|||
13
include/dt-bindings/sound/meson-g12a-tohdmitx.h
Normal file
13
include/dt-bindings/sound/meson-g12a-tohdmitx.h
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __DT_MESON_G12A_TOHDMITX_H
|
||||
#define __DT_MESON_G12A_TOHDMITX_H
|
||||
|
||||
#define TOHDMITX_I2S_IN_A 0
|
||||
#define TOHDMITX_I2S_IN_B 1
|
||||
#define TOHDMITX_I2S_IN_C 2
|
||||
#define TOHDMITX_I2S_OUT 3
|
||||
#define TOHDMITX_SPDIF_IN_A 4
|
||||
#define TOHDMITX_SPDIF_IN_B 5
|
||||
#define TOHDMITX_SPDIF_OUT 6
|
||||
|
||||
#endif /* __DT_MESON_G12A_TOHDMITX_H */
|
||||
Loading…
Reference in New Issue
Block a user