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dm: arm64: ls1046a: add i2c DM support 

This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1046A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Biwen Li 2020-02-05 22:02:17 +08:00 committed by Priyanka Jain
parent fefac937fb
commit bb1165f900
27 changed files with 148 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@ -107,11 +107,11 @@ config ARCH_LS1046A
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
select SYS_I2C_MXC_I2C1
select SYS_I2C_MXC_I2C2
select SYS_I2C_MXC_I2C3
select SYS_I2C_MXC_I2C4
select SYS_I2C_MXC if !DM_I2C
select SYS_I2C_MXC_I2C1 if !DM_I2C
select SYS_I2C_MXC_I2C2 if !DM_I2C
select SYS_I2C_MXC_I2C3 if !DM_I2C
select SYS_I2C_MXC_I2C4 if !DM_I2C
imply SCSI
imply SCSI_AHCI

3
arch/arm/dts/fsl-ls1046a-frwy.dts
View File

@ -32,3 +32,6 @@
};
&i2c0 {
status = "okay";
};

4
arch/arm/dts/fsl-ls1046a-qds.dtsi
View File

@ -80,3 +80,7 @@
&sata {
status = "okay";
};
&i2c0 {
status = "okay";
};

8
arch/arm/dts/fsl-ls1046a-rdb.dts
View File

@ -43,3 +43,11 @@
&sata {
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c3 {
status = "okay";
};

2
arch/arm/include/asm/gpio.h
View File

@ -5,7 +5,7 @@
!defined(CONFIG_ARCH_LS1028A) && !defined(CONFIG_ARCH_LS2080A) && \
!defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \
!defined(CONFIG_ARCH_LS1012A) && !defined(CONFIG_ARCH_LS1043A) && \
!defined(CONFIG_ARCH_U8500) && \
!defined(CONFIG_ARCH_LS1046A) && !defined(CONFIG_ARCH_U8500) && \
!defined(CONFIG_CORTINA_PLATFORM)
#include <asm/arch/gpio.h>
#endif

17
board/freescale/ls1046afrwy/ls1046afrwy.c
View File

@ -36,11 +36,24 @@
DECLARE_GLOBAL_DATA_PTR;
int select_i2c_ch_pca9547(u8 ch)
int select_i2c_ch_pca9547(u8 ch, int bus_num)
{
int ret;
#ifdef CONFIG_DM_I2C
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return ret;
}
ret = dm_i2c_write(dev, 0, &ch, 1);
#else
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@ -149,7 +162,7 @@ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
sec_init();
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
return 0;
}

25
board/freescale/ls1046aqds/ls1046aqds.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
*/
#include <common.h>
@ -269,11 +270,23 @@ u32 get_lpuart_clk(void)
}
#endif
int select_i2c_ch_pca9547(u8 ch)
int select_i2c_ch_pca9547(u8 ch, int bus_num)
{
int ret;
#ifdef CONFIG_DM_I2C
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return ret;
}
ret = dm_i2c_write(dev, 0, &ch, 1);
#else
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@ -288,8 +301,10 @@ int dram_init(void)
* When resuming from deep sleep, the I2C channel may not be
* in the default channel. So, switch to the default channel
* before accessing DDR SPD.
*
* PCA9547 mount on I2C1 bus
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
fsl_initdram();
#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
defined(CONFIG_SPL_BUILD)
@ -302,7 +317,7 @@ int dram_init(void)
int i2c_multiplexer_select_vid_channel(u8 channel)
{
return select_i2c_ch_pca9547(channel);
return select_i2c_ch_pca9547(channel, 0);
}
int board_early_init_f(void)
@ -315,8 +330,10 @@ int board_early_init_f(void)
u8 uart;
#endif
#ifdef CONFIG_SYS_I2C
#ifdef CONFIG_SYS_I2C_EARLY_INIT
i2c_early_init_f();
#endif
#endif
fsl_lsch2_early_init_f();
@ -394,7 +411,7 @@ int misc_init_r(void)
int board_init(void)
{
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
#ifdef CONFIG_SYS_FSL_SERDES
config_serdes_mux();

2
configs/ls1046afrwy_tfa_defconfig
View File

@ -62,3 +62,5 @@ CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y

2
configs/ls1046aqds_SECURE_BOOT_defconfig
View File

@ -60,3 +60,5 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y

2
configs/ls1046aqds_defconfig
View File

@ -62,3 +62,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y

2
configs/ls1046aqds_lpuart_defconfig
View File

@ -64,3 +64,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y

2
configs/ls1046aqds_nand_defconfig
View File

@ -70,3 +70,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y

2
configs/ls1046aqds_qspi_defconfig
View File

@ -58,3 +58,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y

2
configs/ls1046aqds_sdcard_ifc_defconfig
View File

@ -80,3 +80,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y

2
configs/ls1046aqds_sdcard_qspi_defconfig
View File

@ -74,3 +74,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y

2
configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
View File

@ -61,3 +61,5 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y

2
configs/ls1046aqds_tfa_defconfig
View File

@ -71,3 +71,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y

2
configs/ls1046ardb_emmc_defconfig
View File

@ -73,3 +73,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y

2
configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
View File

@ -55,3 +55,5 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y

2
configs/ls1046ardb_qspi_defconfig
View File

@ -57,3 +57,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y

2
configs/ls1046ardb_qspi_spl_defconfig
View File

@ -77,3 +77,5 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_SPL_GZIP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y

2
configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
View File

@ -70,3 +70,5 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y

2
configs/ls1046ardb_sdcard_defconfig
View File

@ -72,3 +72,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y

2
configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
View File

@ -54,3 +54,5 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y

2
configs/ls1046ardb_tfa_defconfig
View File

@ -58,3 +58,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y

46
drivers/power/power_i2c.c
View File

@ -7,6 +7,7 @@
* Stefano Babic, DENX Software Engineering, sbabic@denx.de
*
* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
* (C) Copyright 2019 NXP
*/
#include <common.h>
@ -21,8 +22,20 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
if (check_reg(p, reg))
return -EINVAL;
#if defined(CONFIG_DM_I2C)
struct udevice *dev;
int ret;
ret = i2c_get_chip_for_busnum(p->bus, pmic_i2c_addr,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
p->bus);
return -ENXIO;
}
#else /* Non DM I2C support - will be removed */
I2C_SET_BUS(p->bus);
#endif
switch (pmic_i2c_tx_num) {
case 3:
@ -53,7 +66,11 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
return -EINVAL;
}
#if defined(CONFIG_DM_I2C)
return dm_i2c_write(dev, reg, buf, pmic_i2c_tx_num);
#else
return i2c_write(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num);
#endif
}
int pmic_reg_read(struct pmic *p, u32 reg, u32 *val)
@ -65,9 +82,21 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val)
if (check_reg(p, reg))
return -EINVAL;
I2C_SET_BUS(p->bus);
#if defined(CONFIG_DM_I2C)
struct udevice *dev;
ret = i2c_get_chip_for_busnum(p->bus, pmic_i2c_addr,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
p->bus);
return -ENXIO;
}
ret = dm_i2c_read(dev, reg, buf, pmic_i2c_tx_num);
#else /* Non DM I2C support - will be removed */
I2C_SET_BUS(p->bus);
ret = i2c_read(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num);
#endif
if (ret)
return ret;
@ -100,12 +129,25 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val)
int pmic_probe(struct pmic *p)
{
i2c_set_bus_num(p->bus);
debug("Bus: %d PMIC:%s probed!\n", p->bus, p->name);
#if defined(CONFIG_DM_I2C)
struct udevice *dev;
int ret;
ret = i2c_get_chip_for_busnum(p->bus, pmic_i2c_addr,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
p->bus);
return -ENXIO;
}
#else /* Non DM I2C support - will be removed */
i2c_set_bus_num(p->bus);
if (i2c_probe(pmic_i2c_addr)) {
printf("Can't find PMIC:%s\n", p->name);
return -ENODEV;
}
#endif
return 0;
}

11
include/configs/ls1046a_common.h
View File

@ -16,6 +16,7 @@
#define SPL_NO_QSPI
#define SPL_NO_USB
#define SPL_NO_SATA
#undef CONFIG_DM_I2C
#endif
#if defined(CONFIG_SPL_BUILD) && \
(defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
@ -126,7 +127,17 @@
#endif
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
#else
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
#endif
/* PCIe */
#define CONFIG_PCIE1 /* PCIE controller 1 */