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ppc4xx: Fix compilation warnings and coding style issues in HCU4/HCU5

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Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2008-01-17 14:29:04 +01:00
parent 055606bd25
commit ba52be3d0e
5 changed files with 16 additions and 19 deletions
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4
board/netstal/hcu4/Makefile
View File

@ -27,11 +27,11 @@ vpath hcu_flash.c ../common
vpath nm_bsp.c ../common
# NOBJS : Netstal common objects
NOBJS = fixed_sdram.o hcu_flash.o nm_bsp.o
NOBJS = ../common/fixed_sdram.o ../common/hcu_flash.o ../common/nm_bsp.o
COBJS = $(BOARD).o
SOBJS =
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ../common/$(NOBJS:.o=.c)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(NOBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
NOBJS := $(addprefix $(obj),$(NOBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))

1
board/netstal/hcu4/hcu4.c
View File

@ -37,6 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
#if defined(DEBUG)
void show_sdram_registers(void);
#endif
long int fixed_hcu4_sdram (unsigned int dram_size);
/*
* This function is run very early, out of flash, and before devices are

4
board/netstal/hcu5/Makefile
View File

@ -26,11 +26,11 @@ vpath hcu_flash.c ../common
vpath nm_bsp.c ../common
# NOBJS : Netstal common objects
NOBJS = hcu_flash.o nm_bsp.o
NOBJS = ../common/hcu_flash.o ../common/nm_bsp.o
COBJS = $(BOARD).o sdram.o
SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ../common/$(NOBJS:.o=.c)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(NOBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
NOBJS := $(addprefix $(obj),$(NOBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))

3
board/netstal/hcu5/hcu5.c
View File

@ -497,9 +497,6 @@ int post_hotkeys_pressed(void)
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
u32 val[4];
int rc;
ft_cpu_setup(blob, bd);
}

23
board/netstal/hcu5/sdram.c
View File

@ -62,6 +62,11 @@ void dflush(void);
#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */
#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define ECC_RAM 0x03267F0B
#define NO_ECC_RAM 0x00267F0B
#define HCU_HW_SDRAM_CONFIG_MASK 0x7
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
/* disable caching on DDR2 */
@ -71,6 +76,7 @@ void board_add_ram_info(int use_default)
{
PPC4xx_SYS_INFO board_cfg;
u32 val;
mfsdram(DDR0_22, val);
val &= DDR0_22_CTRL_RAW_MASK;
switch (val) {
@ -163,18 +169,17 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes)
/* Check whether vxWorks is using EDR logging, if yes zero */
/* also PostMortem and user reserved memory */
magic= in_be32(start_address + num_bytes -
(CONFIG_PRAM*1024) + sizeof(u32));
magic = (u32 *)in_be32((u32 *)(start_address + num_bytes -
(CONFIG_PRAM*1024) + sizeof(u32)));
debug("\n%s: CONFIG_PRAM %d kB magic 0x%x 0x%p -> 0x%x\n", __FUNCTION__,
CONFIG_PRAM,
start_address + num_bytes - (CONFIG_PRAM*1024) + sizeof(u32),
start_address + num_bytes - (CONFIG_PRAM*1024) + sizeof(u32),
magic, in_be32(magic));
if (in_be32(magic) == 0xbeefbabe)
num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM;
num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM;
#endif
sync();
eieio();
@ -204,7 +209,6 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes)
return;
}
#endif
@ -215,9 +219,6 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes)
************************************************************************/
long int initdram (int board_type)
{
#define HCU_HW_SDRAM_CONFIG_MASK 0x7
#define INVALID_HW_CONFIG "Invalid HW-Config"
u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
unsigned int dram_size = 0;
mtsdram(DDR0_02, 0x00000000);
@ -228,7 +229,7 @@ long int initdram (int board_type)
mtsdram(DDR0_03, 0x02030602);
mtsdram(DDR0_04, 0x0A020200);
mtsdram(DDR0_05, 0x02020307);
switch (*hwVersReg & HCU_HW_SDRAM_CONFIG_MASK) {
switch (in_be16((u16 *)HCU_HW_VERSION_REGISTER) & HCU_HW_SDRAM_CONFIG_MASK) {
case 1:
dram_size = 256 * 1024 * 1024 ;
mtsdram(DDR0_06, 0x0102C812); /* 256MB RAM */
@ -259,8 +260,6 @@ long int initdram (int board_type)
mtsdram(DDR0_19, 0x1D1D1D1D);
mtsdram(DDR0_20, 0x0B0B0B0B);
mtsdram(DDR0_21, 0x0B0B0B0B);
#define ECC_RAM 0x03267F0B
#define NO_ECC_RAM 0x00267F0B
#ifdef CONFIG_DDR_ECC
mtsdram(DDR0_22, ECC_RAM);
#else