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https://github.com/brain-hackers/u-boot-brain
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MX31: Add support to update FPGA bitstream
The patch adds the possibility to update the QONG FPGA (a Lattice XP2-5E) with u-boot using some GPIOs to drive the JTAG interface. Signed-off-by: Stefano Babic <sbabic@denx.de>
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@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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LIB = $(obj)lib$(BOARD).a
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COBJS := qong.o
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COBJS := qong.o fpga.o
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SOBJS := lowlevel_init.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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95
board/davedenx/qong/fpga.c
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95
board/davedenx/qong/fpga.c
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@ -0,0 +1,95 @@
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/*
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* (C) Copyright 2010
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <asm/arch/mx31.h>
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#include <asm/arch/mx31-regs.h>
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#include <mxc_gpio.h>
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#include <fpga.h>
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#include <lattice.h>
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#include "qong_fpga.h"
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_FPGA)
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static void qong_jtag_init(void)
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{
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return;
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}
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static void qong_fpga_jtag_set_tdi(int value)
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{
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mxc_gpio_set(QONG_FPGA_TDI_PIN, value);
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}
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static void qong_fpga_jtag_set_tms(int value)
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{
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mxc_gpio_set(QONG_FPGA_TMS_PIN, value);
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}
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static void qong_fpga_jtag_set_tck(int value)
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{
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mxc_gpio_set(QONG_FPGA_TCK_PIN, value);
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}
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static int qong_fpga_jtag_get_tdo(void)
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{
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return mxc_gpio_get(QONG_FPGA_TDO_PIN);
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}
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lattice_board_specific_func qong_fpga_fns = {
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qong_jtag_init,
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qong_fpga_jtag_set_tdi,
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qong_fpga_jtag_set_tms,
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qong_fpga_jtag_set_tck,
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qong_fpga_jtag_get_tdo
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};
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Lattice_desc qong_fpga[CONFIG_FPGA_COUNT] = {
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{
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Lattice_XP2,
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lattice_jtag_mode,
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356519,
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(void *) &qong_fpga_fns,
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NULL,
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0,
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"lfxp2_5e_ftbga256"
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},
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};
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int qong_fpga_init(void)
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{
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int i;
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fpga_init();
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for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
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fpga_add(fpga_lattice, &qong_fpga[i]);
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}
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return 0;
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}
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#endif
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@ -73,6 +73,15 @@ int board_early_init_f (void)
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/* set interrupt pin as input */
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/* set interrupt pin as input */
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mxc_gpio_direction(QONG_FPGA_IRQ_PIN, MXC_GPIO_DIRECTION_IN);
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mxc_gpio_direction(QONG_FPGA_IRQ_PIN, MXC_GPIO_DIRECTION_IN);
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/* FPGA JTAG Interface */
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
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mxc_gpio_direction(QONG_FPGA_TCK_PIN, MXC_GPIO_DIRECTION_OUT);
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mxc_gpio_direction(QONG_FPGA_TMS_PIN, MXC_GPIO_DIRECTION_OUT);
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mxc_gpio_direction(QONG_FPGA_TDI_PIN, MXC_GPIO_DIRECTION_OUT);
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mxc_gpio_direction(QONG_FPGA_TDO_PIN, MXC_GPIO_DIRECTION_IN);
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#endif
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#endif
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/* setup pins for UART1 */
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/* setup pins for UART1 */
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@ -146,6 +155,8 @@ int board_init (void)
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gd->bd->bi_arch_number = MACH_TYPE_QONG;
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gd->bd->bi_arch_number = MACH_TYPE_QONG;
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gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
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gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
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qong_fpga_init();
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return 0;
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return 0;
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}
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}
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@ -24,7 +24,6 @@
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#ifndef QONG_FPGA_H
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#ifndef QONG_FPGA_H
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#define QONG_FPGA_H
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#define QONG_FPGA_H
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#ifdef CONFIG_QONG_FPGA
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#define QONG_FPGA_CTRL_BASE CONFIG_FPGA_BASE
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#define QONG_FPGA_CTRL_BASE CONFIG_FPGA_BASE
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#define QONG_FPGA_CTRL_VERSION (QONG_FPGA_CTRL_BASE + 0x00000000)
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#define QONG_FPGA_CTRL_VERSION (QONG_FPGA_CTRL_BASE + 0x00000000)
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#define QONG_FPGA_PERIPH_SIZE (1 << 24)
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#define QONG_FPGA_PERIPH_SIZE (1 << 24)
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@ -35,6 +34,6 @@
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#define QONG_FPGA_TDO_PIN 7
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#define QONG_FPGA_TDO_PIN 7
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#define QONG_FPGA_RST_PIN 48
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#define QONG_FPGA_RST_PIN 48
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#define QONG_FPGA_IRQ_PIN 40
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#define QONG_FPGA_IRQ_PIN 40
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#endif
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int qong_fpga_init(void);
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#endif /* QONG_FPGA_H */
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#endif /* QONG_FPGA_H */
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@ -66,8 +66,11 @@
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#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
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#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
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/* FPGA */
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/* FPGA */
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#define CONFIG_FPGA
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#define CONFIG_QONG_FPGA 1
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#define CONFIG_QONG_FPGA 1
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#define CONFIG_FPGA_BASE (CS1_BASE)
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#define CONFIG_FPGA_BASE (CS1_BASE)
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#define CONFIG_FPGA_LATTICE
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#define CONFIG_FPGA_COUNT 1
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#ifdef CONFIG_QONG_FPGA
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#ifdef CONFIG_QONG_FPGA
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/* Ethernet */
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/* Ethernet */
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