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socfpga: correctly increment freeze_controller_base address
Correctly increment the base address of the freeze controller. And since SYSMGR_FRZCTRL_VIOCTRL_SHIFT is not needed, remove it from the include file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Wolfgang Denk <wd@denx.de>
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@ -38,8 +38,7 @@ void sys_mgr_frzctrl_freeze_req(void)
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/* Freeze channel 0 to 2 */
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/* Freeze channel 0 to 2 */
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for (channel_id = 0; channel_id <= 2; channel_id++) {
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for (channel_id = 0; channel_id <= 2; channel_id++) {
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ioctrl_reg_offset = (u32)(
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ioctrl_reg_offset = (u32)(
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&freeze_controller_base->vioctrl +
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&freeze_controller_base->vioctrl + channel_id);
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(channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
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/*
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/*
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* Assert active low enrnsl, plniotri
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* Assert active low enrnsl, plniotri
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@ -120,8 +119,7 @@ void sys_mgr_frzctrl_thaw_req(void)
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/* Thaw channel 0 to 2 */
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/* Thaw channel 0 to 2 */
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for (channel_id = 0; channel_id <= 2; channel_id++) {
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for (channel_id = 0; channel_id <= 2; channel_id++) {
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ioctrl_reg_offset
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ioctrl_reg_offset
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= (u32)(&freeze_controller_base->vioctrl
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= (u32)(&freeze_controller_base->vioctrl + channel_id);
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+ (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
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/*
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/*
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* Assert active low bhniotri signal and
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* Assert active low bhniotri signal and
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@ -42,7 +42,6 @@ typedef enum {
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#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001
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#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001
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#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2
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#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2
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#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1
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#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1
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#define SYSMGR_FRZCTRL_VIOCTRL_SHIFT 0x2
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void sys_mgr_frzctrl_freeze_req(void);
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void sys_mgr_frzctrl_freeze_req(void);
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void sys_mgr_frzctrl_thaw_req(void);
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void sys_mgr_frzctrl_thaw_req(void);
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