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ARM: tegra: translate __asm_flush_l3_cache to assembly

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When performing a cache disable function, code must not access DRAM.
That is because when the cache is disabled, it will be bypassed and all
loads and stores will be serviced by RAM. This prevents accessing any
dirty data in the cache. In turn, this means the stack cannot be
used, since that is in RAM. To guarantee that code doesn't use RAM (and
in particular the stack) __asm_flush_l3_cache() must be manually
implemented in assembly, rather than implemented in C since the compiler
won't know not to touch RAM.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Stephen Warren 2016-10-19 15:18:45 -06:00 committed by Tom Warren
parent 6db8e17892
commit b9ae6415b6
2 changed files with 25 additions and 23 deletions
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25
arch/arm/mach-tegra/tegra186/cache.S Normal file
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/*
* Copyright (c) 2016, NVIDIA CORPORATION.
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <config.h>
#include <linux/linkage.h>
#define SMC_SIP_INVOKE_MCE 0x82FFFF00
#define MCE_SMC_ROC_FLUSH_CACHE (SMC_SIP_INVOKE_MCE | 11)
ENTRY(__asm_flush_l3_cache)
mov x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff)
movk x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16
mov x1, #0
mov x2, #0
mov x3, #0
mov x4, #0
mov x5, #0
mov x6, #0
smc #0
mov x0, #0
ret
ENDPROC(__asm_flush_l3_cache)

23
arch/arm/mach-tegra/tegra186/cache.c
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@ -1,23 +0,0 @@
/*
* Copyright (c) 2016, NVIDIA CORPORATION.
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <asm/system.h>
#define SMC_SIP_INVOKE_MCE 0x82FFFF00
#define MCE_SMC_ROC_FLUSH_CACHE 11
int __asm_flush_l3_cache(void)
{
struct pt_regs regs = {0};
isb();
regs.regs[0] = SMC_SIP_INVOKE_MCE | MCE_SMC_ROC_FLUSH_CACHE;
smc_call(&regs);
return 0;
}