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mpc85xx: Add support for ATUM8548 (updated)
Add support for Instituto Atlantico's ATUM8548 board Signed-off-by: robert lazarski <robertlazarski@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
robert lazarski
Andrew Fleming-AFLEMING
parent
7bd6104b71
commit
b964e9368f
56
board/atum8548/Makefile
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56
board/atum8548/Makefile
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@ -0,0 +1,56 @@
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#
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# Copyright 2004 Freescale Semiconductor.
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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ifneq ($(OBJTREE),$(SRCTREE))
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$(shell mkdir -p $(obj)../common)
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endif
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o
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SOBJS := init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(OBJS) $(SOBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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420
board/atum8548/atum8548.c
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420
board/atum8548/atum8548.c
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@ -0,0 +1,420 @@
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/*
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* Copyright 2007
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* Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
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*
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* Copyright 2007 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <asm/immap_fsl_pci.h>
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#include <asm/io.h>
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#include <spd.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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extern long int spd_sdram(void);
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long int fixed_sdram(void);
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int board_early_init_f (void)
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{
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return 0;
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}
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int checkboard (void)
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{
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volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
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volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
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volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
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if ((uint)&gur->porpllsr != 0xe00e0000) {
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printf("immap size error %x\n",&gur->porpllsr);
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}
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printf ("Board: ATUM8548\n");
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lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
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lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
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ecm->eedr = 0xffffffff; /* Clear ecm errors */
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ecm->eeer = 0xffffffff; /* Enable ecm errors */
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return 0;
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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long int fixed_sdram (void)
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{
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volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
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ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
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ddr->cs0_config = CFG_DDR_CS0_CONFIG;
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ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
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ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
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ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
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ddr->sdram_mode = CFG_DDR_MODE;
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ddr->sdram_interval = CFG_DDR_INTERVAL;
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#if defined (CONFIG_DDR_ECC)
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ddr->err_disable = 0x0000000D;
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ddr->err_sbe = 0x00ff0000;
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#endif
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asm("sync;isync;msync");
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udelay(500);
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#if defined (CONFIG_DDR_ECC)
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/* Enable ECC checking */
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ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
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#else
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ddr->sdram_cfg = CFG_DDR_CONTROL;
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#endif
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asm("sync; isync; msync");
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udelay(500);
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return CFG_SDRAM_SIZE * 1024 * 1024;
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}
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#endif /* !defined(CONFIG_SPD_EEPROM) */
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long int
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initdram(int board_type)
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{
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long dram_size = 0;
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puts("Initializing\n");
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#if defined(CONFIG_SPD_EEPROM)
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puts("spd_sdram\n");
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dram_size = spd_sdram ();
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#else
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puts("fixed_sdram\n");
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dram_size = fixed_sdram ();
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#endif
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize and enable DDR ECC.
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*/
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ddr_enable_ecc(dram_size);
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#endif
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puts(" DDR: ");
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return dram_size;
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}
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#if defined(CFG_DRAM_TEST)
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int
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testdram(void)
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{
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uint *pstart = (uint *) CFG_MEMTEST_START;
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uint *pend = (uint *) CFG_MEMTEST_END;
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uint *p;
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printf("Testing DRAM from 0x%08x to 0x%08x\n",
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CFG_MEMTEST_START,
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CFG_MEMTEST_END);
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printf("DRAM test phase 1:\n");
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for (p = pstart; p < pend; p++) {
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printf ("DRAM test attempting to write 0xaaaaaaaa at: %08x\n", (uint) p);
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*p = 0xaaaaaaaa;
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}
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("DRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("DRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("DRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("DRAM test passed.\n");
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return 0;
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}
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#endif
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#ifdef CONFIG_PCI1
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static struct pci_controller pci1_hose;
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#endif
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#ifdef CONFIG_PCI2
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static struct pci_controller pci2_hose;
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#endif
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif
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int first_free_busno=0;
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void
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pci_init_board(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
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uint devdisr = gur->devdisr;
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uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
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uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
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debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
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devdisr, io_sel, host_agent);
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/* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */
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gur->clkocr |= MPC85xx_ATUM_CLKOCR;
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if (io_sel & 1) {
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
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printf (" eTSEC1 is in sgmii mode.\n");
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
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printf (" eTSEC2 is in sgmii mode.\n");
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
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printf (" eTSEC3 is in sgmii mode.\n");
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
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printf (" eTSEC4 is in sgmii mode.\n");
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}
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#ifdef CONFIG_PCIE1
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pcie1_hose;
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int pcie_ep = (host_agent == 5);
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int pcie_configured = io_sel & 6;
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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printf ("\n PCIE1 connected to slot as %s (base address %x)",
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pcie_ep ? "End Point" : "Root Complex",
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(uint)pci);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
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}
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printf ("\n");
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/* inbound */
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pci_set_region(hose->regions + 0,
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CFG_PCI_MEMORY_BUS,
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CFG_PCI_MEMORY_PHYS,
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CFG_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* outbound memory */
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pci_set_region(hose->regions + 1,
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CFG_PCIE1_MEM_BASE,
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CFG_PCIE1_MEM_PHYS,
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CFG_PCIE1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(hose->regions + 2,
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CFG_PCIE1_IO_BASE,
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CFG_PCIE1_IO_PHYS,
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CFG_PCIE1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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#ifdef CFG_PCIE1_MEM_BASE2
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/* outbound memory */
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pci_set_region(hose->regions + 3,
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CFG_PCIE1_MEM_BASE2,
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CFG_PCIE1_MEM_PHYS2,
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CFG_PCIE1_MEM_SIZE2,
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PCI_REGION_MEM);
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hose->region_count++;
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#endif
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno=hose->last_busno+1;
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printf(" PCIE1 on bus %02x - %02x\n",
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hose->first_busno,hose->last_busno);
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} else {
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printf (" PCIE1: disabled\n");
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}
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
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#endif
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#ifdef CONFIG_PCI1
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pci1_hose;
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uint pci_agent = (host_agent == 6);
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uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */
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uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
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uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
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uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
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printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
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(pci_32) ? 32 : 64,
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(pci_speed == 33333000) ? "33" :
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(pci_speed == 66666000) ? "66" : "unknown",
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pci_clk_sel ? "sync" : "async",
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pci_agent ? "agent" : "host",
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pci_arb ? "arbiter" : "external-arbiter",
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(uint)pci
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);
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/* inbound */
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pci_set_region(hose->regions + 0,
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CFG_PCI_MEMORY_BUS,
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CFG_PCI_MEMORY_PHYS,
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CFG_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* outbound memory */
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pci_set_region(hose->regions + 1,
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CFG_PCI1_MEM_BASE,
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CFG_PCI1_MEM_PHYS,
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CFG_PCI1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(hose->regions + 2,
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CFG_PCI1_IO_BASE,
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CFG_PCI1_IO_PHYS,
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CFG_PCI1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno=hose->last_busno+1;
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printf ("PCI1 on bus %02x - %02x\n",
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hose->first_busno,hose->last_busno);
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} else {
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printf (" PCI1: disabled\n");
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}
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
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#endif
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#ifdef CONFIG_PCI2
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pci2_hose;
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if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
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pci_set_region(hose->regions + 0,
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CFG_PCI_MEMORY_BUS,
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CFG_PCI_MEMORY_PHYS,
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CFG_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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pci_set_region(hose->regions + 1,
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CFG_PCI2_MEM_BASE,
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CFG_PCI2_MEM_PHYS,
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CFG_PCI2_MEM_SIZE,
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PCI_REGION_MEM);
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pci_set_region(hose->regions + 2,
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CFG_PCI2_IO_BASE,
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CFG_PCI2_IO_PHYS,
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CFG_PCI2_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno=hose->last_busno+1;
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printf ("PCI2 on bus %02x - %02x\n",
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hose->first_busno,hose->last_busno);
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} else {
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printf (" PCI2: disabled\n");
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}
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCI2;
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#endif
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}
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int last_stage_init(void)
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{
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int ic = icache_status ();
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printf ("icache_status: %d\n", ic);
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return 0;
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}
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|
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#if defined(CONFIG_OF_BOARD_SETUP)
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void
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ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int node, tmp[2];
|
||||
const char *path;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
node = fdt_path_offset(blob, "/aliases");
|
||||
tmp[0] = 0;
|
||||
if (node >= 0) {
|
||||
#ifdef CONFIG_PCI1
|
||||
path = fdt_getprop(blob, node, "pci0", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_PCI2
|
||||
path = fdt_getprop(blob, node, "pci1", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE1
|
||||
path = fdt_getprop(blob, node, "pci2", NULL);
|
||||
if (path) {
|
||||
tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
|
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
33
board/atum8548/config.mk
Normal file
33
board/atum8548/config.mk
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
#
|
||||
# Copyright 2004, 2007 Freescale Semiconductor.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# atum8548 board
|
||||
# TEXT_BASE = 0xfff80000
|
||||
# TEXT_BASE = 0xfffff000
|
||||
ifndef TEXT_BASE
|
||||
TEXT_BASE = 0xfff80000
|
||||
endif
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
|
||||
235
board/atum8548/init.S
Normal file
235
board/atum8548/init.S
Normal file
|
|
@ -0,0 +1,235 @@
|
|||
/*
|
||||
* Copyright 2007
|
||||
* Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
|
||||
* Copyright 2004, 2007 Freescale Semiconductor.
|
||||
* Copyright 2002,2003, Motorola Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <ppc_defs.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <config.h>
|
||||
#include <mpc85xx.h>
|
||||
|
||||
#define LAWAR_TRGT_PCI1 0x00000000
|
||||
#define LAWAR_TRGT_PCI2 0x00100000
|
||||
#define LAWAR_TRGT_PCIE 0x00200000
|
||||
#define LAWAR_TRGT_DDR 0x00f00000
|
||||
|
||||
/*
|
||||
* TLB0 and TLB1 Entries
|
||||
*
|
||||
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
|
||||
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after
|
||||
* these TLB entries are established.
|
||||
*
|
||||
* The TLB entries for DDR are dynamically setup in spd_sdram()
|
||||
* and use TLB1 Entries 8 through 15 as needed according to the
|
||||
* size of DDR memory.
|
||||
*
|
||||
* MAS0: tlbsel, esel, nv
|
||||
* MAS1: valid, iprot, tid, ts, tsize
|
||||
* MAS2: epn, x0, x1, w, i, m, g, e
|
||||
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
|
||||
*/
|
||||
|
||||
#define entry_start \
|
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \
|
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
|
||||
.section .bootpg, "ax"
|
||||
.globl tlb1_entry
|
||||
tlb1_entry:
|
||||
entry_start
|
||||
|
||||
/*
|
||||
* Number of TLB0 and TLB1 entries in the following table
|
||||
*/
|
||||
.long (2f-1f)/16
|
||||
|
||||
1:
|
||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
|
||||
/*
|
||||
* TLB0 4K Non-cacheable, guarded
|
||||
* 0xff700000 4K Initial CCSRBAR mapping
|
||||
*
|
||||
* This ends up at a TLB0 Index==0 entry, and must not collide
|
||||
* with other TLB0 Entries.
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
|
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
#else
|
||||
#error("Update the number of table entries in tlb1_entry")
|
||||
#endif
|
||||
|
||||
/*
|
||||
* TLB0 16K Cacheable, guarded
|
||||
* Temporary Global data for initialization
|
||||
*
|
||||
* Use four 4K TLB0 entries. These entries must be cacheable
|
||||
* as they provide the bootstrap memory before the memory
|
||||
* controler and real memory have been configured.
|
||||
*
|
||||
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
|
||||
* and must not collide with other TLB0 entries.
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
|
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, MAS2_G)
|
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
|
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, MAS2_G)
|
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0,
|
||||
(MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
|
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, MAS2_G)
|
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0,
|
||||
(MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
|
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, MAS2_G)
|
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0,
|
||||
(MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
/* TLB 1 Initializations */
|
||||
/*
|
||||
* TLB 0, 1: 128M Non-cacheable, guarded
|
||||
* 0xf8000000 128M FLASH
|
||||
* Out of reset this entry is only 4K.
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(1, 0, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
|
||||
.long FSL_BOOKE_MAS2(CFG_FLASH_BASE + 0x4000000, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_FLASH_BASE + 0x4000000, 0,
|
||||
(MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
.long FSL_BOOKE_MAS0(1, 1, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
|
||||
.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
/*
|
||||
* TLB 2: 1G Non-cacheable, guarded
|
||||
* 0x80000000 1G PCI1/PCIE 8,9,a,b
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(1, 2, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
|
||||
.long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
/*
|
||||
* TLB 3, 4: 512M Non-cacheable, guarded
|
||||
* 0xc0000000 1G PCI2
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(1, 3, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
|
||||
.long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
.long FSL_BOOKE_MAS0(1, 4, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
|
||||
.long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0,
|
||||
(MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
/*
|
||||
* TLB 5: 64M Non-cacheable, guarded
|
||||
* 0xe000_0000 1M CCSRBAR
|
||||
* 0xe200_0000 1M PCI1 IO
|
||||
* 0xe210_0000 1M PCI2 IO
|
||||
* 0xe300_0000 1M PCIe IO
|
||||
*/
|
||||
.long FSL_BOOKE_MAS0(1, 5, 0)
|
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
|
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
|
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
|
||||
|
||||
2:
|
||||
entry_end
|
||||
|
||||
/*
|
||||
* LAW(Local Access Window) configuration:
|
||||
*
|
||||
* 0x0000_0000 0x7fff_ffff DDR 2G
|
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
|
||||
* 0xa000_0000 0xbfff_ffff PCIe MEM 512M
|
||||
* 0xc000_0000 0xdfff_ffff PCI2 MEM 512M
|
||||
* 0xe000_0000 0xe000_ffff CCSR 1M
|
||||
* 0xe200_0000 0xe10f_ffff PCI1 IO 1M
|
||||
* 0xe280_0000 0xe20f_ffff PCI2 IO 1M
|
||||
* 0xe300_0000 0xe30f_ffff PCIe IO 1M
|
||||
* 0xf800_0000 0xffff_ffff FLASH (boot bank) 128M
|
||||
*
|
||||
* Notes:
|
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
|
||||
* If flash is 8M at default position (last 8M), no LAW needed.
|
||||
*
|
||||
* LAW 0 is reserved for boot mapping
|
||||
*/
|
||||
|
||||
.section .bootpg, "ax"
|
||||
.globl law_entry
|
||||
law_entry:
|
||||
entry_start
|
||||
|
||||
.long (4f-3f)/8
|
||||
3:
|
||||
.long 0
|
||||
.long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_1G)) & ~LAWAR_EN
|
||||
|
||||
.long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
|
||||
.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
|
||||
|
||||
.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
|
||||
.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
|
||||
|
||||
.long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff
|
||||
.long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
|
||||
|
||||
.long (CFG_PCI2_IO_PHYS>>12) & 0xfffff
|
||||
.long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
|
||||
|
||||
.long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
|
||||
.long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M)
|
||||
|
||||
.long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
|
||||
.long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M)
|
||||
|
||||
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
|
||||
.long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
|
||||
.long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
|
||||
|
||||
4:
|
||||
entry_end
|
||||
Loading…
Reference in New Issue
Block a user