mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-27 23:20:26 +09:00
85xx: add ability to upload QE firmware
Define the layout of a binary blob that contains a QE firmware and instructions on how to upload it. Add function qe_upload_firmware() to parse the blob and perform the actual upload. Add command-line command "qe fw" to take a firmware blob in memory and upload it. Update ft_cpu_setup() on 85xx to create the 'firmware' device tree node if U-Boot has uploaded a firmware. Fully define 'struct rsp' in immap_qe.h to include the actual RISC Special Registers. Signed-off-by: Timur Tabi <timur@freescale.com>
This commit is contained in:
parent
b009f3eca9
commit
b8ec238503
@ -30,6 +30,9 @@
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#include <fdt_support.h>
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#include <exports.h>
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#ifdef CONFIG_QE
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#include "../drivers/qe/qe.h"
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#endif
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/*
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* Global data (for the gd->bd)
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*/
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@ -614,4 +617,49 @@ void fdt_fixup_ethernet(void *fdt, bd_t *bd)
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#endif
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}
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}
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#ifdef CONFIG_QE
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/*
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* If a QE firmware has been uploaded, then add the 'firmware' node under
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* the 'qe' node.
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*/
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void fdt_fixup_qe_firmware(void *fdt)
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{
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struct qe_firmware_info *qe_fw_info;
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int node, ret;
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qe_fw_info = qe_get_firmware_info();
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if (!qe_fw_info)
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return;
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node = fdt_path_offset(fdt, "/qe");
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if (node < 0)
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return;
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/* We assume the node doesn't exist yet */
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node = fdt_add_subnode(fdt, node, "firmware");
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if (node < 0)
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return;
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ret = fdt_setprop(fdt, node, "extended-modes",
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&qe_fw_info->extended_modes, sizeof(u64));
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if (ret < 0)
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goto error;
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ret = fdt_setprop_string(fdt, node, "id", qe_fw_info->id);
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if (ret < 0)
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goto error;
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ret = fdt_setprop(fdt, node, "virtual-traps", qe_fw_info->vtraps,
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sizeof(qe_fw_info->vtraps));
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if (ret < 0)
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goto error;
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return;
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error:
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fdt_del_node(fdt, node);
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}
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#endif
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#endif
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@ -45,6 +45,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
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#ifdef CONFIG_QE
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do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
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"bus-frequency", bd->bi_busfreq, 1);
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fdt_fixup_qe_firmware(blob);
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#endif
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#ifdef CFG_NS16550
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219
drivers/qe/qe.c
219
drivers/qe/qe.c
@ -21,6 +21,7 @@
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*/
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#include "common.h"
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#include <command.h>
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#include "asm/errno.h"
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#include "asm/io.h"
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#include "asm/immap_qe.h"
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@ -248,4 +249,222 @@ int qe_set_mii_clk_src(int ucc_num)
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return 0;
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}
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/* The maximum number of RISCs we support */
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#define MAX_QE_RISC 2
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/* Firmware information stored here for qe_get_firmware_info() */
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static struct qe_firmware_info qe_firmware_info;
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/*
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* Set to 1 if QE firmware has been uploaded, and therefore
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* qe_firmware_info contains valid data.
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*/
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static int qe_firmware_uploaded;
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/*
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* Upload a QE microcode
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*
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* This function is a worker function for qe_upload_firmware(). It does
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* the actual uploading of the microcode.
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*/
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static void qe_upload_microcode(const void *base,
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const struct qe_microcode *ucode)
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{
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const u32 *code = base + be32_to_cpu(ucode->code_offset);
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unsigned int i;
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if (ucode->major || ucode->minor || ucode->revision)
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printf("QE: uploading microcode '%s' version %u.%u.%u\n",
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ucode->id, ucode->major, ucode->minor, ucode->revision);
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else
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printf("QE: uploading microcode '%s'\n", ucode->id);
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/* Use auto-increment */
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out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
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QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
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for (i = 0; i < be32_to_cpu(ucode->count); i++)
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out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
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}
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/*
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* Upload a microcode to the I-RAM at a specific address.
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*
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* See docs/README.qe_firmware for information on QE microcode uploading.
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*
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* Currently, only version 1 is supported, so the 'version' field must be
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* set to 1.
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*
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* The SOC model and revision are not validated, they are only displayed for
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* informational purposes.
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*
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* 'calc_size' is the calculated size, in bytes, of the firmware structure and
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* all of the microcode structures, minus the CRC.
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*
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* 'length' is the size that the structure says it is, including the CRC.
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*/
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int qe_upload_firmware(const struct qe_firmware *firmware)
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{
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unsigned int i;
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unsigned int j;
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u32 crc;
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size_t calc_size = sizeof(struct qe_firmware);
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size_t length;
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const struct qe_header *hdr;
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if (!firmware) {
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printf("Invalid address\n");
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return -EINVAL;
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}
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hdr = &firmware->header;
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length = be32_to_cpu(hdr->length);
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/* Check the magic */
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if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
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(hdr->magic[2] != 'F')) {
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printf("Not a microcode\n");
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return -EPERM;
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}
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/* Check the version */
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if (hdr->version != 1) {
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printf("Unsupported version\n");
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return -EPERM;
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}
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/* Validate some of the fields */
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if ((firmware->count < 1) || (firmware->count >= MAX_QE_RISC)) {
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printf("Invalid data\n");
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return -EINVAL;
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}
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/* Validate the length and check if there's a CRC */
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calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
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for (i = 0; i < firmware->count; i++)
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/*
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* For situations where the second RISC uses the same microcode
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* as the first, the 'code_offset' and 'count' fields will be
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* zero, so it's okay to add those.
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*/
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calc_size += sizeof(u32) *
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be32_to_cpu(firmware->microcode[i].count);
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/* Validate the length */
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if (length != calc_size + sizeof(u32)) {
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printf("Invalid length\n");
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return -EPERM;
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}
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/*
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* Validate the CRC. We would normally call crc32_no_comp(), but that
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* function isn't available unless you turn on JFFS support.
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*/
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crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
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if (crc != (crc32(-1, (const void *) firmware, calc_size) ^ -1)) {
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printf("Firmware CRC is invalid\n");
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return -EIO;
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}
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/*
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* If the microcode calls for it, split the I-RAM.
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*/
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if (!firmware->split) {
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out_be16(&qe_immr->cp.cercr,
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in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
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}
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if (firmware->soc.model)
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printf("Firmware '%s' for %u V%u.%u\n",
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firmware->id, be16_to_cpu(firmware->soc.model),
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firmware->soc.major, firmware->soc.minor);
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else
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printf("Firmware '%s'\n", firmware->id);
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/*
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* The QE only supports one microcode per RISC, so clear out all the
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* saved microcode information and put in the new.
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*/
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memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
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strcpy(qe_firmware_info.id, firmware->id);
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qe_firmware_info.extended_modes = firmware->extended_modes;
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memcpy(qe_firmware_info.vtraps, firmware->vtraps,
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sizeof(firmware->vtraps));
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qe_firmware_uploaded = 1;
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/* Loop through each microcode. */
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for (i = 0; i < firmware->count; i++) {
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const struct qe_microcode *ucode = &firmware->microcode[i];
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/* Upload a microcode if it's present */
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if (ucode->code_offset)
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qe_upload_microcode(firmware, ucode);
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/* Program the traps for this processor */
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for (j = 0; j < 16; j++) {
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u32 trap = be32_to_cpu(ucode->traps[j]);
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if (trap)
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out_be32(&qe_immr->rsp[i].tibcr[j], trap);
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}
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/* Enable traps */
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out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
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}
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return 0;
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}
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struct qe_firmware_info *qe_get_firmware_info(void)
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{
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return qe_firmware_uploaded ? &qe_firmware_info : NULL;
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}
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static int qe_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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ulong addr;
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if (argc < 3) {
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printf ("Usage:\n%s\n", cmdtp->usage);
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return 1;
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}
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if (strcmp(argv[1], "fw") == 0) {
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addr = simple_strtoul(argv[2], NULL, 16);
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if (!addr) {
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printf("Invalid address\n");
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return -EINVAL;
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}
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/*
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* If a length was supplied, compare that with the 'length'
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* field.
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*/
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if (argc > 3) {
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ulong length = simple_strtoul(argv[3], NULL, 16);
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struct qe_firmware *firmware = (void *) addr;
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if (length != be32_to_cpu(firmware->header.length)) {
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printf("Length mismatch\n");
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return -EINVAL;
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}
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}
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return qe_upload_firmware((const struct qe_firmware *) addr);
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}
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printf ("Usage:\n%s\n", cmdtp->usage);
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return 1;
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}
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U_BOOT_CMD(
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qe, 4, 0, qe_cmd,
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"qe - QUICC Engine commands\n",
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"fw <addr> [<length>] - Upload firmware binary at address <addr> to "
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"the QE,\n\twith optional length <length> verification.\n"
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);
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#endif /* CONFIG_QE */
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@ -222,6 +222,60 @@ typedef enum qe_clock {
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#define QE_SDEBCR_BA_MASK 0x01FFFFFF
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/* Communication Processor */
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#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
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#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
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#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
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/* I-RAM */
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#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
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#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
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/* Structure that defines QE firmware binary files.
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*
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* See doc/README.qe_firmware for a description of these fields.
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*/
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struct qe_firmware {
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struct qe_header {
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u32 length; /* Length of the entire structure, in bytes */
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u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
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u8 version; /* Version of this layout. First ver is '1' */
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} header;
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u8 id[62]; /* Null-terminated identifier string */
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u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
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u8 count; /* Number of microcode[] structures */
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struct {
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u16 model; /* The SOC model */
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u8 major; /* The SOC revision major */
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u8 minor; /* The SOC revision minor */
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} __attribute__ ((packed)) soc;
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u8 padding[4]; /* Reserved, for alignment */
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u64 extended_modes; /* Extended modes */
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u32 vtraps[8]; /* Virtual trap addresses */
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u8 reserved[4]; /* Reserved, for future expansion */
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struct qe_microcode {
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u8 id[32]; /* Null-terminated identifier */
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u32 traps[16]; /* Trap addresses, 0 == ignore */
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u32 eccr; /* The value for the ECCR register */
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u32 iram_offset; /* Offset into I-RAM for the code */
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u32 count; /* Number of 32-bit words of the code */
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u32 code_offset; /* Offset of the actual microcode */
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u8 major; /* The microcode version major */
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u8 minor; /* The microcode version minor */
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u8 revision; /* The microcode version revision */
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u8 padding; /* Reserved, for alignment */
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u8 reserved[4]; /* Reserved, for future expansion */
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} __attribute__ ((packed)) microcode[1];
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/* All microcode binaries should be located here */
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/* CRC32 should be located here, after the microcode binaries */
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} __attribute__ ((packed));
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struct qe_firmware_info {
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char id[64]; /* Firmware name */
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u32 vtraps[8]; /* Virtual trap addresses */
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u64 extended_modes; /* Extended modes */
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};
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void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign);
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void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data);
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uint qe_muram_alloc(uint size, uint align);
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@ -233,5 +287,7 @@ void qe_reset(void);
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void qe_assign_page(uint snum, uint para_ram_base);
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int qe_set_brg(uint brg, uint rate);
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int qe_set_mii_clk_src(int ucc_num);
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int qe_upload_firmware(const struct qe_firmware *firmware);
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struct qe_firmware_info *qe_get_firmware_info(void);
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#endif /* __QE_H__ */
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@ -513,10 +513,39 @@ typedef struct dbg {
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u8 res2[0x48];
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} __attribute__ ((packed)) dbg_t;
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/* RISC Special Registers (Trap and Breakpoint)
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/*
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* RISC Special Registers (Trap and Breakpoint). These are described in
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* the QE Developer's Handbook.
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*/
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typedef struct rsp {
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u8 fixme[0x100];
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u32 tibcr[16]; /* Trap/instruction breakpoint control regs */
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u8 res0[64];
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u32 ibcr0;
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u32 ibs0;
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u32 ibcnr0;
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u8 res1[4];
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u32 ibcr1;
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u32 ibs1;
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u32 ibcnr1;
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u32 npcr;
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u32 dbcr;
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u32 dbar;
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u32 dbamr;
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u32 dbsr;
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u32 dbcnr;
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u8 res2[12];
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u32 dbdr_h;
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u32 dbdr_l;
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u32 dbdmr_h;
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u32 dbdmr_l;
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u32 bsr;
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u32 bor;
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u32 bior;
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u8 res3[4];
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u32 iatr[4];
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u32 eccr; /* Exception control configuration register */
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u32 eicr;
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u8 res4[0x100-0xf8];
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} __attribute__ ((packed)) rsp_t;
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typedef struct qe_immap {
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@ -48,6 +48,7 @@ int fdt_fixup_memory(void *blob, u64 start, u64 size);
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void fdt_fixup_ethernet(void *fdt, bd_t *bd);
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int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
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const void *val, int len, int create);
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void fdt_fixup_qe_firmware(void *fdt);
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#ifdef CONFIG_OF_HAS_UBOOT_ENV
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int fdt_env(void *fdt);
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