arm: dts: add missing vexpress device trees
Add the device trees for * vexpress_ca5x2_defconfig * vexpress_ca9x4_defconfig * vexpress_ca15_tc2_defconfig as available in Linux 5.1 rc5. We are using the vexpress_ca15_tc2_defconfig and vexpress_ca9x4_defconfig for Travis testing via QEMU. The UEFI base Embedded Base Boot Requirements Specification (EBBR) requires that an embedded board either provides a device tree or an ACPI table. All block devices are meant to be moved to the driver model. On ARM this requires a device tree. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This commit is contained in:
Heinrich Schuchardt
Tom Rini
parent
50fd31fd77
commit
b85d155199
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@ -724,6 +724,10 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
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dtb-$(CONFIG_TARGET_GE_BX50V3) += imx6q-bx50v3.dtb
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dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
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dtb-$(CONFIG_TARGET_VEXPRESS_CA5X2) += vexpress-v2p-ca5s.dtb
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dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb
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dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb
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targets += $(dtb-y)
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# Add any required device tree compiler flags here
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@ -0,0 +1,437 @@
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/*
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* ARM Ltd. Versatile Express
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*
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* Motherboard Express uATX
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* V2M-P1
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*
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* HBI-0190D
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*
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* RS1 memory map ("ARM Cortex-A Series memory map" in the board's
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* Technical Reference Manual)
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*
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* WARNING! The hardware described in this file is independent from the
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* original variant (vexpress-v2m.dtsi), but there is a strong
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* correspondence between the two configurations.
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*
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* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
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* CHANGES TO vexpress-v2m.dtsi!
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*/
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/ {
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smb@8000000 {
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motherboard {
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model = "V2M-P1";
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arm,hbi = <0x190>;
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arm,vexpress,site = <0>;
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arm,v2m-memory-map = "rs1";
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compatible = "arm,vexpress,v2m-p1", "simple-bus";
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#address-cells = <2>; /* SMB chipselect number and offset */
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#size-cells = <1>;
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#interrupt-cells = <1>;
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ranges;
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flash@0,00000000 {
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compatible = "arm,vexpress-flash", "cfi-flash";
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reg = <0 0x00000000 0x04000000>,
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<4 0x00000000 0x04000000>;
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bank-width = <4>;
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};
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psram@1,00000000 {
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compatible = "arm,vexpress-psram", "mtd-ram";
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reg = <1 0x00000000 0x02000000>;
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bank-width = <4>;
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};
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ethernet@2,02000000 {
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compatible = "smsc,lan9118", "smsc,lan9115";
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reg = <2 0x02000000 0x10000>;
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interrupts = <15>;
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phy-mode = "mii";
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reg-io-width = <4>;
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smsc,irq-active-high;
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smsc,irq-push-pull;
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vdd33a-supply = <&v2m_fixed_3v3>;
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vddvario-supply = <&v2m_fixed_3v3>;
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};
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usb@2,03000000 {
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compatible = "nxp,usb-isp1761";
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reg = <2 0x03000000 0x20000>;
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interrupts = <16>;
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port1-otg;
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};
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iofpga@3,00000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 3 0 0x200000>;
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v2m_sysreg: sysreg@10000 {
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compatible = "arm,vexpress-sysreg";
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reg = <0x010000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x10000 0x1000>;
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v2m_led_gpios: gpio@8 {
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compatible = "arm,vexpress-sysreg,sys_led";
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reg = <0x008 4>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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v2m_mmc_gpios: gpio@48 {
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compatible = "arm,vexpress-sysreg,sys_mci";
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reg = <0x048 4>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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v2m_flash_gpios: gpio@4c {
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compatible = "arm,vexpress-sysreg,sys_flash";
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reg = <0x04c 4>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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v2m_sysctl: sysctl@20000 {
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compatible = "arm,sp810", "arm,primecell";
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reg = <0x020000 0x1000>;
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clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
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clock-names = "refclk", "timclk", "apb_pclk";
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#clock-cells = <1>;
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clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
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assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
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assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
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};
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/* PCI-E I2C bus */
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v2m_i2c_pcie: i2c@30000 {
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compatible = "arm,versatile-i2c";
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reg = <0x030000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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pcie-switch@60 {
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compatible = "idt,89hpes32h8";
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reg = <0x60>;
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};
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};
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aaci@40000 {
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compatible = "arm,pl041", "arm,primecell";
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reg = <0x040000 0x1000>;
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interrupts = <11>;
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clocks = <&smbclk>;
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clock-names = "apb_pclk";
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};
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mmci@50000 {
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compatible = "arm,pl180", "arm,primecell";
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reg = <0x050000 0x1000>;
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interrupts = <9>, <10>;
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cd-gpios = <&v2m_mmc_gpios 0 0>;
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wp-gpios = <&v2m_mmc_gpios 1 0>;
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max-frequency = <12000000>;
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vmmc-supply = <&v2m_fixed_3v3>;
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clocks = <&v2m_clk24mhz>, <&smbclk>;
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clock-names = "mclk", "apb_pclk";
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};
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kmi@60000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x060000 0x1000>;
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interrupts = <12>;
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clocks = <&v2m_clk24mhz>, <&smbclk>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi@70000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x070000 0x1000>;
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interrupts = <13>;
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clocks = <&v2m_clk24mhz>, <&smbclk>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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v2m_serial0: uart@90000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x090000 0x1000>;
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interrupts = <5>;
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clocks = <&v2m_oscclk2>, <&smbclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial1: uart@a0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0a0000 0x1000>;
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interrupts = <6>;
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clocks = <&v2m_oscclk2>, <&smbclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial2: uart@b0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0b0000 0x1000>;
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interrupts = <7>;
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clocks = <&v2m_oscclk2>, <&smbclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial3: uart@c0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0c0000 0x1000>;
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interrupts = <8>;
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clocks = <&v2m_oscclk2>, <&smbclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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wdt@f0000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x0f0000 0x1000>;
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interrupts = <0>;
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clocks = <&v2m_refclk32khz>, <&smbclk>;
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clock-names = "wdogclk", "apb_pclk";
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};
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v2m_timer01: timer@110000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x110000 0x1000>;
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interrupts = <2>;
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clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
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clock-names = "timclken1", "timclken2", "apb_pclk";
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};
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v2m_timer23: timer@120000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x120000 0x1000>;
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interrupts = <3>;
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clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
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clock-names = "timclken1", "timclken2", "apb_pclk";
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};
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/* DVI I2C bus */
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v2m_i2c_dvi: i2c@160000 {
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compatible = "arm,versatile-i2c";
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reg = <0x160000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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dvi-transmitter@39 {
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compatible = "sil,sii9022-tpi", "sil,sii9022";
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reg = <0x39>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dvi_bridge_in: endpoint {
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remote-endpoint = <&clcd_pads>;
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};
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};
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};
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};
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dvi-transmitter@60 {
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compatible = "sil,sii9022-cpi", "sil,sii9022";
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reg = <0x60>;
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};
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};
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rtc@170000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x170000 0x1000>;
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interrupts = <4>;
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clocks = <&smbclk>;
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clock-names = "apb_pclk";
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};
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compact-flash@1a0000 {
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compatible = "arm,vexpress-cf", "ata-generic";
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reg = <0x1a0000 0x100
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0x1a0100 0xf00>;
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reg-shift = <2>;
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};
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clcd@1f0000 {
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compatible = "arm,pl111", "arm,primecell";
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reg = <0x1f0000 0x1000>;
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interrupt-names = "combined";
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interrupts = <14>;
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clocks = <&v2m_oscclk1>, <&smbclk>;
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clock-names = "clcdclk", "apb_pclk";
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/* 800x600 16bpp @36MHz works fine */
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max-memory-bandwidth = <54000000>;
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memory-region = <&vram>;
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port {
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clcd_pads: endpoint {
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remote-endpoint = <&dvi_bridge_in>;
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arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
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};
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};
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};
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};
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v2m_fixed_3v3: fixed-regulator-0 {
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compatible = "regulator-fixed";
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regulator-name = "3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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v2m_clk24mhz: clk24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "v2m:clk24mhz";
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};
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v2m_refclk1mhz: refclk1mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000>;
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clock-output-names = "v2m:refclk1mhz";
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};
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v2m_refclk32khz: refclk32khz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "v2m:refclk32khz";
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};
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leds {
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compatible = "gpio-leds";
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user1 {
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label = "v2m:green:user1";
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gpios = <&v2m_led_gpios 0 0>;
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linux,default-trigger = "heartbeat";
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};
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user2 {
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label = "v2m:green:user2";
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gpios = <&v2m_led_gpios 1 0>;
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linux,default-trigger = "mmc0";
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};
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user3 {
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label = "v2m:green:user3";
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gpios = <&v2m_led_gpios 2 0>;
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linux,default-trigger = "cpu0";
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};
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user4 {
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label = "v2m:green:user4";
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gpios = <&v2m_led_gpios 3 0>;
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linux,default-trigger = "cpu1";
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};
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user5 {
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label = "v2m:green:user5";
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gpios = <&v2m_led_gpios 4 0>;
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linux,default-trigger = "cpu2";
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};
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user6 {
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label = "v2m:green:user6";
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gpios = <&v2m_led_gpios 5 0>;
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linux,default-trigger = "cpu3";
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};
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user7 {
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label = "v2m:green:user7";
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gpios = <&v2m_led_gpios 6 0>;
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linux,default-trigger = "cpu4";
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};
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user8 {
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label = "v2m:green:user8";
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gpios = <&v2m_led_gpios 7 0>;
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linux,default-trigger = "cpu5";
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};
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};
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mcc {
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compatible = "arm,vexpress,config-bus";
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arm,vexpress,config-bridge = <&v2m_sysreg>;
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oscclk0 {
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/* MCC static memory clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 0>;
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freq-range = <25000000 60000000>;
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#clock-cells = <0>;
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clock-output-names = "v2m:oscclk0";
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};
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v2m_oscclk1: oscclk1 {
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/* CLCD clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 1>;
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freq-range = <23750000 65000000>;
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#clock-cells = <0>;
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clock-output-names = "v2m:oscclk1";
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};
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v2m_oscclk2: oscclk2 {
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/* IO FPGA peripheral clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 2>;
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freq-range = <24000000 24000000>;
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#clock-cells = <0>;
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clock-output-names = "v2m:oscclk2";
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};
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volt-vio {
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/* Logic level voltage */
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compatible = "arm,vexpress-volt";
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arm,vexpress-sysreg,func = <2 0>;
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regulator-name = "VIO";
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regulator-always-on;
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label = "VIO";
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};
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temp-mcc {
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/* MCC internal operating temperature */
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compatible = "arm,vexpress-temp";
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arm,vexpress-sysreg,func = <4 0>;
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label = "MCC";
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};
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reset {
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compatible = "arm,vexpress-reset";
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arm,vexpress-sysreg,func = <5 0>;
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};
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muxfpga {
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compatible = "arm,vexpress-muxfpga";
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arm,vexpress-sysreg,func = <7 0>;
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};
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shutdown {
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compatible = "arm,vexpress-shutdown";
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arm,vexpress-sysreg,func = <8 0>;
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};
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reboot {
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compatible = "arm,vexpress-reboot";
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arm,vexpress-sysreg,func = <9 0>;
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};
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dvimode {
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compatible = "arm,vexpress-dvimode";
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arm,vexpress-sysreg,func = <11 0>;
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};
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};
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};
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};
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};
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@ -0,0 +1,451 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* ARM Ltd. Versatile Express
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*
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* Motherboard Express uATX
|
||||
* V2M-P1
|
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*
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* HBI-0190D
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*
|
||||
* Original memory map ("Legacy memory map" in the board's
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* Technical Reference Manual)
|
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*
|
||||
* WARNING! The hardware described in this file is independent from the
|
||||
* RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
|
||||
* correspondence between the two configurations.
|
||||
*
|
||||
* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
|
||||
* CHANGES TO vexpress-v2m-rs1.dtsi!
|
||||
*/
|
||||
|
||||
/ {
|
||||
smb@4000000 {
|
||||
motherboard {
|
||||
model = "V2M-P1";
|
||||
arm,hbi = <0x190>;
|
||||
arm,vexpress,site = <0>;
|
||||
compatible = "arm,vexpress,v2m-p1", "simple-bus";
|
||||
#address-cells = <2>; /* SMB chipselect number and offset */
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
|
||||
flash@0,00000000 {
|
||||
compatible = "arm,vexpress-flash", "cfi-flash";
|
||||
reg = <0 0x00000000 0x04000000>,
|
||||
<1 0x00000000 0x04000000>;
|
||||
bank-width = <4>;
|
||||
};
|
||||
|
||||
psram@2,00000000 {
|
||||
compatible = "arm,vexpress-psram", "mtd-ram";
|
||||
reg = <2 0x00000000 0x02000000>;
|
||||
bank-width = <4>;
|
||||
};
|
||||
|
||||
ethernet@3,02000000 {
|
||||
compatible = "smsc,lan9118", "smsc,lan9115";
|
||||
reg = <3 0x02000000 0x10000>;
|
||||
interrupts = <15>;
|
||||
phy-mode = "mii";
|
||||
reg-io-width = <4>;
|
||||
smsc,irq-active-high;
|
||||
smsc,irq-push-pull;
|
||||
vdd33a-supply = <&v2m_fixed_3v3>;
|
||||
vddvario-supply = <&v2m_fixed_3v3>;
|
||||
};
|
||||
|
||||
usb@3,03000000 {
|
||||
compatible = "nxp,usb-isp1761";
|
||||
reg = <3 0x03000000 0x20000>;
|
||||
interrupts = <16>;
|
||||
port1-otg;
|
||||
};
|
||||
|
||||
iofpga@7,00000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 7 0 0x20000>;
|
||||
|
||||
v2m_sysreg: sysreg@0 {
|
||||
compatible = "arm,vexpress-sysreg";
|
||||
reg = <0x00000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x1000>;
|
||||
|
||||
v2m_led_gpios: gpio@8 {
|
||||
compatible = "arm,vexpress-sysreg,sys_led";
|
||||
reg = <0x008 4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
v2m_mmc_gpios: gpio@48 {
|
||||
compatible = "arm,vexpress-sysreg,sys_mci";
|
||||
reg = <0x048 4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
v2m_flash_gpios: gpio@4c {
|
||||
compatible = "arm,vexpress-sysreg,sys_flash";
|
||||
reg = <0x04c 4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
v2m_sysctl: sysctl@1000 {
|
||||
compatible = "arm,sp810", "arm,primecell";
|
||||
reg = <0x01000 0x1000>;
|
||||
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
|
||||
clock-names = "refclk", "timclk", "apb_pclk";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
|
||||
assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
|
||||
assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
|
||||
};
|
||||
|
||||
/* PCI-E I2C bus */
|
||||
v2m_i2c_pcie: i2c@2000 {
|
||||
compatible = "arm,versatile-i2c";
|
||||
reg = <0x02000 0x1000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pcie-switch@60 {
|
||||
compatible = "idt,89hpes32h8";
|
||||
reg = <0x60>;
|
||||
};
|
||||
};
|
||||
|
||||
aaci@4000 {
|
||||
compatible = "arm,pl041", "arm,primecell";
|
||||
reg = <0x04000 0x1000>;
|
||||
interrupts = <11>;
|
||||
clocks = <&smbclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
mmci@5000 {
|
||||
compatible = "arm,pl180", "arm,primecell";
|
||||
reg = <0x05000 0x1000>;
|
||||
interrupts = <9>, <10>;
|
||||
cd-gpios = <&v2m_mmc_gpios 0 0>;
|
||||
wp-gpios = <&v2m_mmc_gpios 1 0>;
|
||||
max-frequency = <12000000>;
|
||||
vmmc-supply = <&v2m_fixed_3v3>;
|
||||
clocks = <&v2m_clk24mhz>, <&smbclk>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi@6000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x06000 0x1000>;
|
||||
interrupts = <12>;
|
||||
clocks = <&v2m_clk24mhz>, <&smbclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi@7000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x07000 0x1000>;
|
||||
interrupts = <13>;
|
||||
clocks = <&v2m_clk24mhz>, <&smbclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial0: uart@9000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x09000 0x1000>;
|
||||
interrupts = <5>;
|
||||
clocks = <&v2m_oscclk2>, <&smbclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial1: uart@a000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0a000 0x1000>;
|
||||
interrupts = <6>;
|
||||
clocks = <&v2m_oscclk2>, <&smbclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial2: uart@b000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0b000 0x1000>;
|
||||
interrupts = <7>;
|
||||
clocks = <&v2m_oscclk2>, <&smbclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_serial3: uart@c000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0c000 0x1000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&v2m_oscclk2>, <&smbclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
wdt@f000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x0f000 0x1000>;
|
||||
interrupts = <0>;
|
||||
clocks = <&v2m_refclk32khz>, <&smbclk>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_timer01: timer@11000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x11000 0x1000>;
|
||||
interrupts = <2>;
|
||||
clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
|
||||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_timer23: timer@12000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x12000 0x1000>;
|
||||
interrupts = <3>;
|
||||
clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
|
||||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
/* DVI I2C bus */
|
||||
v2m_i2c_dvi: i2c@16000 {
|
||||
compatible = "arm,versatile-i2c";
|
||||
reg = <0x16000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dvi-transmitter@39 {
|
||||
compatible = "sil,sii9022-tpi", "sil,sii9022";
|
||||
reg = <0x39>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/*
|
||||
* Both the core tile and the motherboard routes their output
|
||||
* pads to this transmitter. The motherboard system controller
|
||||
* can select one of them as input using a mux register in
|
||||
* "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is
|
||||
* the only platform with this specific set-up.
|
||||
*/
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dvi_bridge_in_ct: endpoint {
|
||||
remote-endpoint = <&clcd_pads_ct>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dvi_bridge_in_mb: endpoint {
|
||||
remote-endpoint = <&clcd_pads_mb>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dvi-transmitter@60 {
|
||||
compatible = "sil,sii9022-cpi", "sil,sii9022";
|
||||
reg = <0x60>;
|
||||
};
|
||||
};
|
||||
|
||||
rtc@17000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0x17000 0x1000>;
|
||||
interrupts = <4>;
|
||||
clocks = <&smbclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
compact-flash@1a000 {
|
||||
compatible = "arm,vexpress-cf", "ata-generic";
|
||||
reg = <0x1a000 0x100
|
||||
0x1a100 0xf00>;
|
||||
reg-shift = <2>;
|
||||
};
|
||||
|
||||
|
||||
clcd@1f000 {
|
||||
compatible = "arm,pl111", "arm,primecell";
|
||||
reg = <0x1f000 0x1000>;
|
||||
interrupt-names = "combined";
|
||||
interrupts = <14>;
|
||||
clocks = <&v2m_oscclk1>, <&smbclk>;
|
||||
clock-names = "clcdclk", "apb_pclk";
|
||||
/* 800x600 16bpp @36MHz works fine */
|
||||
max-memory-bandwidth = <54000000>;
|
||||
memory-region = <&vram>;
|
||||
|
||||
port {
|
||||
clcd_pads_mb: endpoint {
|
||||
remote-endpoint = <&dvi_bridge_in_mb>;
|
||||
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
v2m_fixed_3v3: fixed-regulator-0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
v2m_clk24mhz: clk24mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "v2m:clk24mhz";
|
||||
};
|
||||
|
||||
v2m_refclk1mhz: refclk1mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
clock-output-names = "v2m:refclk1mhz";
|
||||
};
|
||||
|
||||
v2m_refclk32khz: refclk32khz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "v2m:refclk32khz";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
user1 {
|
||||
label = "v2m:green:user1";
|
||||
gpios = <&v2m_led_gpios 0 0>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
user2 {
|
||||
label = "v2m:green:user2";
|
||||
gpios = <&v2m_led_gpios 1 0>;
|
||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
|
||||
user3 {
|
||||
label = "v2m:green:user3";
|
||||
gpios = <&v2m_led_gpios 2 0>;
|
||||
linux,default-trigger = "cpu0";
|
||||
};
|
||||
|
||||
user4 {
|
||||
label = "v2m:green:user4";
|
||||
gpios = <&v2m_led_gpios 3 0>;
|
||||
linux,default-trigger = "cpu1";
|
||||
};
|
||||
|
||||
user5 {
|
||||
label = "v2m:green:user5";
|
||||
gpios = <&v2m_led_gpios 4 0>;
|
||||
linux,default-trigger = "cpu2";
|
||||
};
|
||||
|
||||
user6 {
|
||||
label = "v2m:green:user6";
|
||||
gpios = <&v2m_led_gpios 5 0>;
|
||||
linux,default-trigger = "cpu3";
|
||||
};
|
||||
|
||||
user7 {
|
||||
label = "v2m:green:user7";
|
||||
gpios = <&v2m_led_gpios 6 0>;
|
||||
linux,default-trigger = "cpu4";
|
||||
};
|
||||
|
||||
user8 {
|
||||
label = "v2m:green:user8";
|
||||
gpios = <&v2m_led_gpios 7 0>;
|
||||
linux,default-trigger = "cpu5";
|
||||
};
|
||||
};
|
||||
|
||||
mcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
oscclk0 {
|
||||
/* MCC static memory clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 0>;
|
||||
freq-range = <25000000 60000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk0";
|
||||
};
|
||||
|
||||
v2m_oscclk1: oscclk1 {
|
||||
/* CLCD clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <23750000 65000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk1";
|
||||
};
|
||||
|
||||
v2m_oscclk2: oscclk2 {
|
||||
/* IO FPGA peripheral clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 2>;
|
||||
freq-range = <24000000 24000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "v2m:oscclk2";
|
||||
};
|
||||
|
||||
volt-vio {
|
||||
/* Logic level voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 0>;
|
||||
regulator-name = "VIO";
|
||||
regulator-always-on;
|
||||
label = "VIO";
|
||||
};
|
||||
|
||||
temp-mcc {
|
||||
/* MCC internal operating temperature */
|
||||
compatible = "arm,vexpress-temp";
|
||||
arm,vexpress-sysreg,func = <4 0>;
|
||||
label = "MCC";
|
||||
};
|
||||
|
||||
reset {
|
||||
compatible = "arm,vexpress-reset";
|
||||
arm,vexpress-sysreg,func = <5 0>;
|
||||
};
|
||||
|
||||
muxfpga {
|
||||
compatible = "arm,vexpress-muxfpga";
|
||||
arm,vexpress-sysreg,func = <7 0>;
|
||||
};
|
||||
|
||||
shutdown {
|
||||
compatible = "arm,vexpress-shutdown";
|
||||
arm,vexpress-sysreg,func = <8 0>;
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible = "arm,vexpress-reboot";
|
||||
arm,vexpress-sysreg,func = <9 0>;
|
||||
};
|
||||
|
||||
dvimode {
|
||||
compatible = "arm,vexpress-dvimode";
|
||||
arm,vexpress-sysreg,func = <11 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,682 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* ARM Ltd. Versatile Express
|
||||
*
|
||||
* CoreTile Express A15x2 A7x3
|
||||
* Cortex-A15_A7 MPCore (V2P-CA15_A7)
|
||||
*
|
||||
* HBI-0249A
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "vexpress-v2m-rs1.dtsi"
|
||||
|
||||
/ {
|
||||
model = "V2P-CA15_CA7";
|
||||
arm,hbi = <0x249>;
|
||||
arm,vexpress,site = <0xf>;
|
||||
compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
chosen { };
|
||||
|
||||
aliases {
|
||||
serial0 = &v2m_serial0;
|
||||
serial1 = &v2m_serial1;
|
||||
serial2 = &v2m_serial2;
|
||||
serial3 = &v2m_serial3;
|
||||
i2c0 = &v2m_i2c_dvi;
|
||||
i2c1 = &v2m_i2c_pcie;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <990>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <1>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <990>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x100>;
|
||||
cci-control-port = <&cci_control2>;
|
||||
cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
|
||||
capacity-dmips-mhz = <516>;
|
||||
dynamic-power-coefficient = <133>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x101>;
|
||||
cci-control-port = <&cci_control2>;
|
||||
cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
|
||||
capacity-dmips-mhz = <516>;
|
||||
dynamic-power-coefficient = <133>;
|
||||
};
|
||||
|
||||
cpu4: cpu@4 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x102>;
|
||||
cci-control-port = <&cci_control2>;
|
||||
cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
|
||||
capacity-dmips-mhz = <516>;
|
||||
dynamic-power-coefficient = <133>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
CLUSTER_SLEEP_BIG: cluster-sleep-big {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
entry-latency-us = <1000>;
|
||||
exit-latency-us = <700>;
|
||||
min-residency-us = <2000>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
entry-latency-us = <1000>;
|
||||
exit-latency-us = <500>;
|
||||
min-residency-us = <2500>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x80000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* Chipselect 2 is physically at 0x18000000 */
|
||||
vram: vram@18000000 {
|
||||
/* 8 MB of designated video RAM */
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0x18000000 0 0x00800000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
wdt@2a490000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0 0x2a490000 0 0x1000>;
|
||||
interrupts = <0 98 4>;
|
||||
clocks = <&oscclk6a>, <&oscclk6a>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
};
|
||||
|
||||
hdlcd@2b000000 {
|
||||
compatible = "arm,hdlcd";
|
||||
reg = <0 0x2b000000 0 0x1000>;
|
||||
interrupts = <0 85 4>;
|
||||
clocks = <&hdlcd_clk>;
|
||||
clock-names = "pxlclk";
|
||||
};
|
||||
|
||||
memory-controller@2b0a0000 {
|
||||
compatible = "arm,pl341", "arm,primecell";
|
||||
reg = <0 0x2b0a0000 0 0x1000>;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@2c001000 {
|
||||
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0 0x2c001000 0 0x1000>,
|
||||
<0 0x2c002000 0 0x2000>,
|
||||
<0 0x2c004000 0 0x2000>,
|
||||
<0 0x2c006000 0 0x2000>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
};
|
||||
|
||||
cci@2c090000 {
|
||||
compatible = "arm,cci-400";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0 0x2c090000 0 0x1000>;
|
||||
ranges = <0x0 0x0 0x2c090000 0x10000>;
|
||||
|
||||
cci_control1: slave-if@4000 {
|
||||
compatible = "arm,cci-400-ctrl-if";
|
||||
interface-type = "ace";
|
||||
reg = <0x4000 0x1000>;
|
||||
};
|
||||
|
||||
cci_control2: slave-if@5000 {
|
||||
compatible = "arm,cci-400-ctrl-if";
|
||||
interface-type = "ace";
|
||||
reg = <0x5000 0x1000>;
|
||||
};
|
||||
|
||||
pmu@9000 {
|
||||
compatible = "arm,cci-400-pmu,r0";
|
||||
reg = <0x9000 0x5000>;
|
||||
interrupts = <0 105 4>,
|
||||
<0 101 4>,
|
||||
<0 102 4>,
|
||||
<0 103 4>,
|
||||
<0 104 4>;
|
||||
};
|
||||
};
|
||||
|
||||
memory-controller@7ffd0000 {
|
||||
compatible = "arm,pl354", "arm,primecell";
|
||||
reg = <0 0x7ffd0000 0 0x1000>;
|
||||
interrupts = <0 86 4>,
|
||||
<0 87 4>;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
dma@7ff00000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0 0x7ff00000 0 0x1000>;
|
||||
interrupts = <0 92 4>,
|
||||
<0 88 4>,
|
||||
<0 89 4>,
|
||||
<0 90 4>,
|
||||
<0 91 4>;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
scc@7fff0000 {
|
||||
compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
|
||||
reg = <0 0x7fff0000 0 0x1000>;
|
||||
interrupts = <0 95 4>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 13 0xf08>,
|
||||
<1 14 0xf08>,
|
||||
<1 11 0xf08>,
|
||||
<1 10 0xf08>;
|
||||
};
|
||||
|
||||
pmu-a15 {
|
||||
compatible = "arm,cortex-a15-pmu";
|
||||
interrupts = <0 68 4>,
|
||||
<0 69 4>;
|
||||
interrupt-affinity = <&cpu0>,
|
||||
<&cpu1>;
|
||||
};
|
||||
|
||||
pmu-a7 {
|
||||
compatible = "arm,cortex-a7-pmu";
|
||||
interrupts = <0 128 4>,
|
||||
<0 129 4>,
|
||||
<0 130 4>;
|
||||
interrupt-affinity = <&cpu2>,
|
||||
<&cpu3>,
|
||||
<&cpu4>;
|
||||
};
|
||||
|
||||
oscclk6a: oscclk6a {
|
||||
/* Reference 24MHz clock */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "oscclk6a";
|
||||
};
|
||||
|
||||
dcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
oscclk0 {
|
||||
/* A15 PLL 0 reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 0>;
|
||||
freq-range = <17000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk0";
|
||||
};
|
||||
|
||||
oscclk1 {
|
||||
/* A15 PLL 1 reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <17000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk1";
|
||||
};
|
||||
|
||||
oscclk2 {
|
||||
/* A7 PLL 0 reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 2>;
|
||||
freq-range = <17000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk2";
|
||||
};
|
||||
|
||||
oscclk3 {
|
||||
/* A7 PLL 1 reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 3>;
|
||||
freq-range = <17000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk3";
|
||||
};
|
||||
|
||||
oscclk4 {
|
||||
/* External AXI master clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 4>;
|
||||
freq-range = <20000000 40000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk4";
|
||||
};
|
||||
|
||||
hdlcd_clk: oscclk5 {
|
||||
/* HDLCD PLL reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 5>;
|
||||
freq-range = <23750000 165000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk5";
|
||||
};
|
||||
|
||||
smbclk: oscclk6 {
|
||||
/* Static memory controller clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 6>;
|
||||
freq-range = <20000000 40000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk6";
|
||||
};
|
||||
|
||||
oscclk7 {
|
||||
/* SYS PLL reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 7>;
|
||||
freq-range = <17000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk7";
|
||||
};
|
||||
|
||||
oscclk8 {
|
||||
/* DDR2 PLL reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 8>;
|
||||
freq-range = <20000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk8";
|
||||
};
|
||||
|
||||
volt-a15 {
|
||||
/* A15 CPU core voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 0>;
|
||||
regulator-name = "A15 Vcore";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-always-on;
|
||||
label = "A15 Vcore";
|
||||
};
|
||||
|
||||
volt-a7 {
|
||||
/* A7 CPU core voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 1>;
|
||||
regulator-name = "A7 Vcore";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-always-on;
|
||||
label = "A7 Vcore";
|
||||
};
|
||||
|
||||
amp-a15 {
|
||||
/* Total current for the two A15 cores */
|
||||
compatible = "arm,vexpress-amp";
|
||||
arm,vexpress-sysreg,func = <3 0>;
|
||||
label = "A15 Icore";
|
||||
};
|
||||
|
||||
amp-a7 {
|
||||
/* Total current for the three A7 cores */
|
||||
compatible = "arm,vexpress-amp";
|
||||
arm,vexpress-sysreg,func = <3 1>;
|
||||
label = "A7 Icore";
|
||||
};
|
||||
|
||||
temp-dcc {
|
||||
/* DCC internal temperature */
|
||||
compatible = "arm,vexpress-temp";
|
||||
arm,vexpress-sysreg,func = <4 0>;
|
||||
label = "DCC";
|
||||
};
|
||||
|
||||
power-a15 {
|
||||
/* Total power for the two A15 cores */
|
||||
compatible = "arm,vexpress-power";
|
||||
arm,vexpress-sysreg,func = <12 0>;
|
||||
label = "A15 Pcore";
|
||||
};
|
||||
|
||||
power-a7 {
|
||||
/* Total power for the three A7 cores */
|
||||
compatible = "arm,vexpress-power";
|
||||
arm,vexpress-sysreg,func = <12 1>;
|
||||
label = "A7 Pcore";
|
||||
};
|
||||
|
||||
energy-a15 {
|
||||
/* Total energy for the two A15 cores */
|
||||
compatible = "arm,vexpress-energy";
|
||||
arm,vexpress-sysreg,func = <13 0>, <13 1>;
|
||||
label = "A15 Jcore";
|
||||
};
|
||||
|
||||
energy-a7 {
|
||||
/* Total energy for the three A7 cores */
|
||||
compatible = "arm,vexpress-energy";
|
||||
arm,vexpress-sysreg,func = <13 2>, <13 3>;
|
||||
label = "A7 Jcore";
|
||||
};
|
||||
};
|
||||
|
||||
etb@20010000 {
|
||||
compatible = "arm,coresight-etb10", "arm,primecell";
|
||||
reg = <0 0x20010000 0 0x1000>;
|
||||
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
in-ports {
|
||||
port {
|
||||
etb_in_port: endpoint {
|
||||
remote-endpoint = <&replicator_out_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tpiu@20030000 {
|
||||
compatible = "arm,coresight-tpiu", "arm,primecell";
|
||||
reg = <0 0x20030000 0 0x1000>;
|
||||
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
in-ports {
|
||||
port {
|
||||
tpiu_in_port: endpoint {
|
||||
remote-endpoint = <&replicator_out_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
replicator {
|
||||
/* non-configurable replicators don't show up on the
|
||||
* AMBA bus. As such no need to add "arm,primecell".
|
||||
*/
|
||||
compatible = "arm,coresight-replicator";
|
||||
|
||||
out-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
replicator_out_port0: endpoint {
|
||||
remote-endpoint = <&etb_in_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
replicator_out_port1: endpoint {
|
||||
remote-endpoint = <&tpiu_in_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
replicator_in_port0: endpoint {
|
||||
remote-endpoint = <&funnel_out_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@20040000 {
|
||||
compatible = "arm,coresight-funnel", "arm,primecell";
|
||||
reg = <0 0x20040000 0 0x1000>;
|
||||
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
out-ports {
|
||||
port {
|
||||
funnel_out_port0: endpoint {
|
||||
remote-endpoint =
|
||||
<&replicator_in_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
funnel_in_port0: endpoint {
|
||||
remote-endpoint = <&ptm0_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
funnel_in_port1: endpoint {
|
||||
remote-endpoint = <&ptm1_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
funnel_in_port2: endpoint {
|
||||
remote-endpoint = <&etm0_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Input port #3 is for ITM, not supported here */
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
funnel_in_port4: endpoint {
|
||||
remote-endpoint = <&etm1_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
funnel_in_port5: endpoint {
|
||||
remote-endpoint = <&etm2_out_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ptm@2201c000 {
|
||||
compatible = "arm,coresight-etm3x", "arm,primecell";
|
||||
reg = <0 0x2201c000 0 0x1000>;
|
||||
|
||||
cpu = <&cpu0>;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
out-ports {
|
||||
port {
|
||||
ptm0_out_port: endpoint {
|
||||
remote-endpoint = <&funnel_in_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ptm@2201d000 {
|
||||
compatible = "arm,coresight-etm3x", "arm,primecell";
|
||||
reg = <0 0x2201d000 0 0x1000>;
|
||||
|
||||
cpu = <&cpu1>;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
out-ports {
|
||||
port {
|
||||
ptm1_out_port: endpoint {
|
||||
remote-endpoint = <&funnel_in_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@2203c000 {
|
||||
compatible = "arm,coresight-etm3x", "arm,primecell";
|
||||
reg = <0 0x2203c000 0 0x1000>;
|
||||
|
||||
cpu = <&cpu2>;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
out-ports {
|
||||
port {
|
||||
etm0_out_port: endpoint {
|
||||
remote-endpoint = <&funnel_in_port2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@2203d000 {
|
||||
compatible = "arm,coresight-etm3x", "arm,primecell";
|
||||
reg = <0 0x2203d000 0 0x1000>;
|
||||
|
||||
cpu = <&cpu3>;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
out-ports {
|
||||
port {
|
||||
etm1_out_port: endpoint {
|
||||
remote-endpoint = <&funnel_in_port4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@2203e000 {
|
||||
compatible = "arm,coresight-etm3x", "arm,primecell";
|
||||
reg = <0 0x2203e000 0 0x1000>;
|
||||
|
||||
cpu = <&cpu4>;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
out-ports {
|
||||
port {
|
||||
etm2_out_port: endpoint {
|
||||
remote-endpoint = <&funnel_in_port5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
smb: smb@8000000 {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0x08000000 0x04000000>,
|
||||
<1 0 0 0x14000000 0x04000000>,
|
||||
<2 0 0 0x18000000 0x04000000>,
|
||||
<3 0 0 0x1c000000 0x04000000>,
|
||||
<4 0 0 0x0c000000 0x04000000>,
|
||||
<5 0 0 0x10000000 0x04000000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 4>,
|
||||
<0 0 1 &gic 0 1 4>,
|
||||
<0 0 2 &gic 0 2 4>,
|
||||
<0 0 3 &gic 0 3 4>,
|
||||
<0 0 4 &gic 0 4 4>,
|
||||
<0 0 5 &gic 0 5 4>,
|
||||
<0 0 6 &gic 0 6 4>,
|
||||
<0 0 7 &gic 0 7 4>,
|
||||
<0 0 8 &gic 0 8 4>,
|
||||
<0 0 9 &gic 0 9 4>,
|
||||
<0 0 10 &gic 0 10 4>,
|
||||
<0 0 11 &gic 0 11 4>,
|
||||
<0 0 12 &gic 0 12 4>,
|
||||
<0 0 13 &gic 0 13 4>,
|
||||
<0 0 14 &gic 0 14 4>,
|
||||
<0 0 15 &gic 0 15 4>,
|
||||
<0 0 16 &gic 0 16 4>,
|
||||
<0 0 17 &gic 0 17 4>,
|
||||
<0 0 18 &gic 0 18 4>,
|
||||
<0 0 19 &gic 0 19 4>,
|
||||
<0 0 20 &gic 0 20 4>,
|
||||
<0 0 21 &gic 0 21 4>,
|
||||
<0 0 22 &gic 0 22 4>,
|
||||
<0 0 23 &gic 0 23 4>,
|
||||
<0 0 24 &gic 0 24 4>,
|
||||
<0 0 25 &gic 0 25 4>,
|
||||
<0 0 26 &gic 0 26 4>,
|
||||
<0 0 27 &gic 0 27 4>,
|
||||
<0 0 28 &gic 0 28 4>,
|
||||
<0 0 29 &gic 0 29 4>,
|
||||
<0 0 30 &gic 0 30 4>,
|
||||
<0 0 31 &gic 0 31 4>,
|
||||
<0 0 32 &gic 0 32 4>,
|
||||
<0 0 33 &gic 0 33 4>,
|
||||
<0 0 34 &gic 0 34 4>,
|
||||
<0 0 35 &gic 0 35 4>,
|
||||
<0 0 36 &gic 0 36 4>,
|
||||
<0 0 37 &gic 0 37 4>,
|
||||
<0 0 38 &gic 0 38 4>,
|
||||
<0 0 39 &gic 0 39 4>,
|
||||
<0 0 40 &gic 0 40 4>,
|
||||
<0 0 41 &gic 0 41 4>,
|
||||
<0 0 42 &gic 0 42 4>;
|
||||
};
|
||||
|
||||
site2: hsb@40000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x40000000 0x3fef0000>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 3>;
|
||||
interrupt-map = <0 0 &gic 0 36 4>,
|
||||
<0 1 &gic 0 37 4>,
|
||||
<0 2 &gic 0 38 4>,
|
||||
<0 3 &gic 0 39 4>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,280 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* ARM Ltd. Versatile Express
|
||||
*
|
||||
* CoreTile Express A5x2
|
||||
* Cortex-A5 MPCore (V2P-CA5s)
|
||||
*
|
||||
* HBI-0225B
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "vexpress-v2m-rs1.dtsi"
|
||||
|
||||
/ {
|
||||
model = "V2P-CA5s";
|
||||
arm,hbi = <0x225>;
|
||||
arm,vexpress,site = <0xf>;
|
||||
compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
chosen { };
|
||||
|
||||
aliases {
|
||||
serial0 = &v2m_serial0;
|
||||
serial1 = &v2m_serial1;
|
||||
serial2 = &v2m_serial2;
|
||||
serial3 = &v2m_serial3;
|
||||
i2c0 = &v2m_i2c_dvi;
|
||||
i2c1 = &v2m_i2c_pcie;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a5";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a5";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x40000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
/* Chipselect 2 is physically at 0x18000000 */
|
||||
vram: vram@18000000 {
|
||||
/* 8 MB of designated video RAM */
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x18000000 0x00800000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
hdlcd@2a110000 {
|
||||
compatible = "arm,hdlcd";
|
||||
reg = <0x2a110000 0x1000>;
|
||||
interrupts = <0 85 4>;
|
||||
clocks = <&hdlcd_clk>;
|
||||
clock-names = "pxlclk";
|
||||
};
|
||||
|
||||
memory-controller@2a150000 {
|
||||
compatible = "arm,pl341", "arm,primecell";
|
||||
reg = <0x2a150000 0x1000>;
|
||||
clocks = <&axi_clk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
memory-controller@2a190000 {
|
||||
compatible = "arm,pl354", "arm,primecell";
|
||||
reg = <0x2a190000 0x1000>;
|
||||
interrupts = <0 86 4>,
|
||||
<0 87 4>;
|
||||
clocks = <&axi_clk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
scu@2c000000 {
|
||||
compatible = "arm,cortex-a5-scu";
|
||||
reg = <0x2c000000 0x58>;
|
||||
};
|
||||
|
||||
timer@2c000600 {
|
||||
compatible = "arm,cortex-a5-twd-timer";
|
||||
reg = <0x2c000600 0x20>;
|
||||
interrupts = <1 13 0x304>;
|
||||
};
|
||||
|
||||
timer@2c000200 {
|
||||
compatible = "arm,cortex-a5-global-timer",
|
||||
"arm,cortex-a9-global-timer";
|
||||
reg = <0x2c000200 0x20>;
|
||||
interrupts = <1 11 0x304>;
|
||||
clocks = <&cpu_clk>;
|
||||
};
|
||||
|
||||
watchdog@2c000620 {
|
||||
compatible = "arm,cortex-a5-twd-wdt";
|
||||
reg = <0x2c000620 0x20>;
|
||||
interrupts = <1 14 0x304>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@2c001000 {
|
||||
compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x2c001000 0x1000>,
|
||||
<0x2c000100 0x100>;
|
||||
};
|
||||
|
||||
L2: cache-controller@2c0f0000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x2c0f0000 0x1000>;
|
||||
interrupts = <0 84 4>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a5-pmu";
|
||||
interrupts = <0 68 4>,
|
||||
<0 69 4>;
|
||||
};
|
||||
|
||||
dcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
cpu_clk: oscclk0 {
|
||||
/* CPU and internal AXI reference clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 0>;
|
||||
freq-range = <50000000 100000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk0";
|
||||
};
|
||||
|
||||
axi_clk: oscclk1 {
|
||||
/* Multiplexed AXI master clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <5000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk1";
|
||||
};
|
||||
|
||||
oscclk2 {
|
||||
/* DDR2 */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 2>;
|
||||
freq-range = <80000000 120000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk2";
|
||||
};
|
||||
|
||||
hdlcd_clk: oscclk3 {
|
||||
/* HDLCD */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 3>;
|
||||
freq-range = <23750000 165000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk3";
|
||||
};
|
||||
|
||||
oscclk4 {
|
||||
/* Test chip gate configuration */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 4>;
|
||||
freq-range = <80000000 80000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk4";
|
||||
};
|
||||
|
||||
smbclk: oscclk5 {
|
||||
/* SMB clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 5>;
|
||||
freq-range = <25000000 60000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk5";
|
||||
};
|
||||
|
||||
temp-dcc {
|
||||
/* DCC internal operating temperature */
|
||||
compatible = "arm,vexpress-temp";
|
||||
arm,vexpress-sysreg,func = <4 0>;
|
||||
label = "DCC";
|
||||
};
|
||||
};
|
||||
|
||||
smb: smb@8000000 {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x08000000 0x04000000>,
|
||||
<1 0 0x14000000 0x04000000>,
|
||||
<2 0 0x18000000 0x04000000>,
|
||||
<3 0 0x1c000000 0x04000000>,
|
||||
<4 0 0x0c000000 0x04000000>,
|
||||
<5 0 0x10000000 0x04000000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 4>,
|
||||
<0 0 1 &gic 0 1 4>,
|
||||
<0 0 2 &gic 0 2 4>,
|
||||
<0 0 3 &gic 0 3 4>,
|
||||
<0 0 4 &gic 0 4 4>,
|
||||
<0 0 5 &gic 0 5 4>,
|
||||
<0 0 6 &gic 0 6 4>,
|
||||
<0 0 7 &gic 0 7 4>,
|
||||
<0 0 8 &gic 0 8 4>,
|
||||
<0 0 9 &gic 0 9 4>,
|
||||
<0 0 10 &gic 0 10 4>,
|
||||
<0 0 11 &gic 0 11 4>,
|
||||
<0 0 12 &gic 0 12 4>,
|
||||
<0 0 13 &gic 0 13 4>,
|
||||
<0 0 14 &gic 0 14 4>,
|
||||
<0 0 15 &gic 0 15 4>,
|
||||
<0 0 16 &gic 0 16 4>,
|
||||
<0 0 17 &gic 0 17 4>,
|
||||
<0 0 18 &gic 0 18 4>,
|
||||
<0 0 19 &gic 0 19 4>,
|
||||
<0 0 20 &gic 0 20 4>,
|
||||
<0 0 21 &gic 0 21 4>,
|
||||
<0 0 22 &gic 0 22 4>,
|
||||
<0 0 23 &gic 0 23 4>,
|
||||
<0 0 24 &gic 0 24 4>,
|
||||
<0 0 25 &gic 0 25 4>,
|
||||
<0 0 26 &gic 0 26 4>,
|
||||
<0 0 27 &gic 0 27 4>,
|
||||
<0 0 28 &gic 0 28 4>,
|
||||
<0 0 29 &gic 0 29 4>,
|
||||
<0 0 30 &gic 0 30 4>,
|
||||
<0 0 31 &gic 0 31 4>,
|
||||
<0 0 32 &gic 0 32 4>,
|
||||
<0 0 33 &gic 0 33 4>,
|
||||
<0 0 34 &gic 0 34 4>,
|
||||
<0 0 35 &gic 0 35 4>,
|
||||
<0 0 36 &gic 0 36 4>,
|
||||
<0 0 37 &gic 0 37 4>,
|
||||
<0 0 38 &gic 0 38 4>,
|
||||
<0 0 39 &gic 0 39 4>,
|
||||
<0 0 40 &gic 0 40 4>,
|
||||
<0 0 41 &gic 0 41 4>,
|
||||
<0 0 42 &gic 0 42 4>;
|
||||
};
|
||||
|
||||
site2: hsb@40000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x40000000 0x40000000>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 3>;
|
||||
interrupt-map = <0 0 &gic 0 36 4>,
|
||||
<0 1 &gic 0 37 4>,
|
||||
<0 2 &gic 0 38 4>,
|
||||
<0 3 &gic 0 39 4>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,368 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* ARM Ltd. Versatile Express
|
||||
*
|
||||
* CoreTile Express A9x4
|
||||
* Cortex-A9 MPCore (V2P-CA9)
|
||||
*
|
||||
* HBI-0191B
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "vexpress-v2m.dtsi"
|
||||
|
||||
/ {
|
||||
model = "V2P-CA9";
|
||||
arm,hbi = <0x191>;
|
||||
arm,vexpress,site = <0xf>;
|
||||
compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
chosen { };
|
||||
|
||||
aliases {
|
||||
serial0 = &v2m_serial0;
|
||||
serial1 = &v2m_serial1;
|
||||
serial2 = &v2m_serial2;
|
||||
serial3 = &v2m_serial3;
|
||||
i2c0 = &v2m_i2c_dvi;
|
||||
i2c1 = &v2m_i2c_pcie;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
A9_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
A9_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
A9_2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <2>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
A9_3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <3>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@60000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x60000000 0x40000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
/* Chipselect 3 is physically at 0x4c000000 */
|
||||
vram: vram@4c000000 {
|
||||
/* 8 MB of designated video RAM */
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x4c000000 0x00800000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
clcd@10020000 {
|
||||
compatible = "arm,pl111", "arm,primecell";
|
||||
reg = <0x10020000 0x1000>;
|
||||
interrupt-names = "combined";
|
||||
interrupts = <0 44 4>;
|
||||
clocks = <&oscclk1>, <&oscclk2>;
|
||||
clock-names = "clcdclk", "apb_pclk";
|
||||
/* 1024x768 16bpp @65MHz */
|
||||
max-memory-bandwidth = <95000000>;
|
||||
|
||||
port {
|
||||
clcd_pads_ct: endpoint {
|
||||
remote-endpoint = <&dvi_bridge_in_ct>;
|
||||
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
memory-controller@100e0000 {
|
||||
compatible = "arm,pl341", "arm,primecell";
|
||||
reg = <0x100e0000 0x1000>;
|
||||
clocks = <&oscclk2>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
memory-controller@100e1000 {
|
||||
compatible = "arm,pl354", "arm,primecell";
|
||||
reg = <0x100e1000 0x1000>;
|
||||
interrupts = <0 45 4>,
|
||||
<0 46 4>;
|
||||
clocks = <&oscclk2>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
timer@100e4000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x100e4000 0x1000>;
|
||||
interrupts = <0 48 4>,
|
||||
<0 49 4>;
|
||||
clocks = <&oscclk2>, <&oscclk2>;
|
||||
clock-names = "timclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog@100e5000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x100e5000 0x1000>;
|
||||
interrupts = <0 51 4>;
|
||||
clocks = <&oscclk2>, <&oscclk2>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
};
|
||||
|
||||
scu@1e000000 {
|
||||
compatible = "arm,cortex-a9-scu";
|
||||
reg = <0x1e000000 0x58>;
|
||||
};
|
||||
|
||||
timer@1e000600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x1e000600 0x20>;
|
||||
interrupts = <1 13 0xf04>;
|
||||
};
|
||||
|
||||
watchdog@1e000620 {
|
||||
compatible = "arm,cortex-a9-twd-wdt";
|
||||
reg = <0x1e000620 0x20>;
|
||||
interrupts = <1 14 0xf04>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@1e001000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x1e001000 0x1000>,
|
||||
<0x1e000100 0x100>;
|
||||
};
|
||||
|
||||
L2: cache-controller@1e00a000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x1e00a000 0x1000>;
|
||||
interrupts = <0 43 4>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
arm,data-latency = <1 1 1>;
|
||||
arm,tag-latency = <1 1 1>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <0 60 4>,
|
||||
<0 61 4>,
|
||||
<0 62 4>,
|
||||
<0 63 4>;
|
||||
interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;
|
||||
|
||||
};
|
||||
|
||||
dcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
oscclk0: extsaxiclk {
|
||||
/* ACLK clock to the AXI master port on the test chip */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 0>;
|
||||
freq-range = <30000000 50000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "extsaxiclk";
|
||||
};
|
||||
|
||||
oscclk1: clcdclk {
|
||||
/* Reference clock for the CLCD */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 1>;
|
||||
freq-range = <10000000 80000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "clcdclk";
|
||||
};
|
||||
|
||||
smbclk: oscclk2: tcrefclk {
|
||||
/* Reference clock for the test chip internal PLLs */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 2>;
|
||||
freq-range = <33000000 100000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "tcrefclk";
|
||||
};
|
||||
|
||||
volt-vd10 {
|
||||
/* Test Chip internal logic voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 0>;
|
||||
regulator-name = "VD10";
|
||||
regulator-always-on;
|
||||
label = "VD10";
|
||||
};
|
||||
|
||||
volt-vd10-s2 {
|
||||
/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 1>;
|
||||
regulator-name = "VD10_S2";
|
||||
regulator-always-on;
|
||||
label = "VD10_S2";
|
||||
};
|
||||
|
||||
volt-vd10-s3 {
|
||||
/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 2>;
|
||||
regulator-name = "VD10_S3";
|
||||
regulator-always-on;
|
||||
label = "VD10_S3";
|
||||
};
|
||||
|
||||
volt-vcc1v8 {
|
||||
/* DDR2 SDRAM and Test Chip DDR2 I/O supply */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 3>;
|
||||
regulator-name = "VCC1V8";
|
||||
regulator-always-on;
|
||||
label = "VCC1V8";
|
||||
};
|
||||
|
||||
volt-ddr2vtt {
|
||||
/* DDR2 SDRAM VTT termination voltage */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 4>;
|
||||
regulator-name = "DDR2VTT";
|
||||
regulator-always-on;
|
||||
label = "DDR2VTT";
|
||||
};
|
||||
|
||||
volt-vcc3v3 {
|
||||
/* Local board supply for miscellaneous logic external to the Test Chip */
|
||||
arm,vexpress-sysreg,func = <2 5>;
|
||||
compatible = "arm,vexpress-volt";
|
||||
regulator-name = "VCC3V3";
|
||||
regulator-always-on;
|
||||
label = "VCC3V3";
|
||||
};
|
||||
|
||||
amp-vd10-s2 {
|
||||
/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
|
||||
compatible = "arm,vexpress-amp";
|
||||
arm,vexpress-sysreg,func = <3 0>;
|
||||
label = "VD10_S2";
|
||||
};
|
||||
|
||||
amp-vd10-s3 {
|
||||
/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
|
||||
compatible = "arm,vexpress-amp";
|
||||
arm,vexpress-sysreg,func = <3 1>;
|
||||
label = "VD10_S3";
|
||||
};
|
||||
|
||||
power-vd10-s2 {
|
||||
/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
|
||||
compatible = "arm,vexpress-power";
|
||||
arm,vexpress-sysreg,func = <12 0>;
|
||||
label = "PVD10_S2";
|
||||
};
|
||||
|
||||
power-vd10-s3 {
|
||||
/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
|
||||
compatible = "arm,vexpress-power";
|
||||
arm,vexpress-sysreg,func = <12 1>;
|
||||
label = "PVD10_S3";
|
||||
};
|
||||
};
|
||||
|
||||
smb: smb@4000000 {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x40000000 0x04000000>,
|
||||
<1 0 0x44000000 0x04000000>,
|
||||
<2 0 0x48000000 0x04000000>,
|
||||
<3 0 0x4c000000 0x04000000>,
|
||||
<7 0 0x10000000 0x00020000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 4>,
|
||||
<0 0 1 &gic 0 1 4>,
|
||||
<0 0 2 &gic 0 2 4>,
|
||||
<0 0 3 &gic 0 3 4>,
|
||||
<0 0 4 &gic 0 4 4>,
|
||||
<0 0 5 &gic 0 5 4>,
|
||||
<0 0 6 &gic 0 6 4>,
|
||||
<0 0 7 &gic 0 7 4>,
|
||||
<0 0 8 &gic 0 8 4>,
|
||||
<0 0 9 &gic 0 9 4>,
|
||||
<0 0 10 &gic 0 10 4>,
|
||||
<0 0 11 &gic 0 11 4>,
|
||||
<0 0 12 &gic 0 12 4>,
|
||||
<0 0 13 &gic 0 13 4>,
|
||||
<0 0 14 &gic 0 14 4>,
|
||||
<0 0 15 &gic 0 15 4>,
|
||||
<0 0 16 &gic 0 16 4>,
|
||||
<0 0 17 &gic 0 17 4>,
|
||||
<0 0 18 &gic 0 18 4>,
|
||||
<0 0 19 &gic 0 19 4>,
|
||||
<0 0 20 &gic 0 20 4>,
|
||||
<0 0 21 &gic 0 21 4>,
|
||||
<0 0 22 &gic 0 22 4>,
|
||||
<0 0 23 &gic 0 23 4>,
|
||||
<0 0 24 &gic 0 24 4>,
|
||||
<0 0 25 &gic 0 25 4>,
|
||||
<0 0 26 &gic 0 26 4>,
|
||||
<0 0 27 &gic 0 27 4>,
|
||||
<0 0 28 &gic 0 28 4>,
|
||||
<0 0 29 &gic 0 29 4>,
|
||||
<0 0 30 &gic 0 30 4>,
|
||||
<0 0 31 &gic 0 31 4>,
|
||||
<0 0 32 &gic 0 32 4>,
|
||||
<0 0 33 &gic 0 33 4>,
|
||||
<0 0 34 &gic 0 34 4>,
|
||||
<0 0 35 &gic 0 35 4>,
|
||||
<0 0 36 &gic 0 36 4>,
|
||||
<0 0 37 &gic 0 37 4>,
|
||||
<0 0 38 &gic 0 38 4>,
|
||||
<0 0 39 &gic 0 39 4>,
|
||||
<0 0 40 &gic 0 40 4>,
|
||||
<0 0 41 &gic 0 41 4>,
|
||||
<0 0 42 &gic 0 42 4>;
|
||||
};
|
||||
|
||||
site2: hsb@e0000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xe0000000 0x20000000>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 3>;
|
||||
interrupt-map = <0 0 &gic 0 36 4>,
|
||||
<0 1 &gic 0 37 4>,
|
||||
<0 2 &gic 0 38 4>,
|
||||
<0 3 &gic 0 39 4>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue