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da8xx: add support for multiple PLL controllers

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Modify clk_get() function in cpu file to work for
multiple PLL controllers.

Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Sudhakar Rajashekhara 2011-09-03 22:18:04 -04:00 committed by Albert ARIBAUD
parent bd65d006a6
commit b7e6843f97
2 changed files with 22 additions and 12 deletions
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30
arch/arm/cpu/arm926ejs/davinci/cpu.c
View File

@ -37,6 +37,7 @@
#define PLLC_PLLDIV4 0x160 #define PLLC_PLLDIV4 0x160
#define PLLC_PLLDIV5 0x164 #define PLLC_PLLDIV5 0x164
#define PLLC_PLLDIV6 0x168 #define PLLC_PLLDIV6 0x168
#define PLLC_PLLDIV7 0x16c
#define PLLC_PLLDIV8 0x170 #define PLLC_PLLDIV8 0x170
#define PLLC_PLLDIV9 0x174 #define PLLC_PLLDIV9 0x174
@ -61,11 +62,9 @@
#endif #endif
#ifdef CONFIG_SOC_DA8XX #ifdef CONFIG_SOC_DA8XX
const dv_reg * const sysdiv[7] = { unsigned int sysdiv[9] = {
&davinci_pllc_regs->plldiv1, &davinci_pllc_regs->plldiv2, PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
&davinci_pllc_regs->plldiv3, &davinci_pllc_regs->plldiv4, PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
&davinci_pllc_regs->plldiv5, &davinci_pllc_regs->plldiv6,
&davinci_pllc_regs->plldiv7
}; };
int clk_get(enum davinci_clk_ids id) int clk_get(enum davinci_clk_ids id)
@ -74,19 +73,27 @@ int clk_get(enum davinci_clk_ids id)
int pllm; int pllm;
int post_div; int post_div;
int pll_out; int pll_out;
unsigned int pll_base;
pll_out = CONFIG_SYS_OSCIN_FREQ; pll_out = CONFIG_SYS_OSCIN_FREQ;
if (id == DAVINCI_AUXCLK_CLKID) if (id == DAVINCI_AUXCLK_CLKID)
goto out; goto out;
if ((id >> 16) == 1)
pll_base = (unsigned int)davinci_pllc1_regs;
else
pll_base = (unsigned int)davinci_pllc0_regs;
id &= 0xFFFF;
/* /*
* Lets keep this simple. Combining operations can result in * Lets keep this simple. Combining operations can result in
* unexpected approximations * unexpected approximations
*/ */
pre_div = (readl(&davinci_pllc_regs->prediv) & pre_div = (readl(pll_base + PLLC_PREDIV) &
DAVINCI_PLLC_DIV_MASK) + 1; DAVINCI_PLLC_DIV_MASK) + 1;
pllm = readl(&davinci_pllc_regs->pllm) + 1; pllm = readl(pll_base + PLLC_PLLM) + 1;
pll_out /= pre_div; pll_out /= pre_div;
pll_out *= pllm; pll_out *= pllm;
@ -94,15 +101,16 @@ int clk_get(enum davinci_clk_ids id)
if (id == DAVINCI_PLLM_CLKID) if (id == DAVINCI_PLLM_CLKID)
goto out; goto out;
post_div = (readl(&davinci_pllc_regs->postdiv) & post_div = (readl(pll_base + PLLC_POSTDIV) &
DAVINCI_PLLC_DIV_MASK) + 1; DAVINCI_PLLC_DIV_MASK) + 1;
pll_out /= post_div; pll_out /= post_div;
if (id == DAVINCI_PLLC_CLKID) if (id == DAVINCI_PLLC_CLKID)
goto out; goto out;
pll_out /= (readl(sysdiv[id - 1]) & DAVINCI_PLLC_DIV_MASK) + 1; pll_out /= (readl(pll_base + sysdiv[id - 1]) &
DAVINCI_PLLC_DIV_MASK) + 1;
out: out:
return pll_out; return pll_out;

4
arch/arm/include/asm/arch-davinci/hardware.h
View File

@ -129,6 +129,7 @@ typedef volatile unsigned int * dv_reg_p;
#define DAVINCI_TIMER1_BASE 0x01c21000 #define DAVINCI_TIMER1_BASE 0x01c21000
#define DAVINCI_WDOG_BASE 0x01c21000 #define DAVINCI_WDOG_BASE 0x01c21000
#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000 #define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
#define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000
#define DAVINCI_PSC0_BASE 0x01c10000 #define DAVINCI_PSC0_BASE 0x01c10000
#define DAVINCI_PSC1_BASE 0x01e27000 #define DAVINCI_PSC1_BASE 0x01e27000
#define DAVINCI_SPI0_BASE 0x01c41000 #define DAVINCI_SPI0_BASE 0x01c41000
@ -387,7 +388,8 @@ struct davinci_pllc_regs {
dv_reg emucnt1; dv_reg emucnt1;
}; };
#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE) #define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
#define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
#define DAVINCI_PLLC_DIV_MASK 0x1f #define DAVINCI_PLLC_DIV_MASK 0x1f
#define ASYNC3 get_async3_src() #define ASYNC3 get_async3_src()