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https://github.com/brain-hackers/u-boot-brain
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da8xx: add support for multiple PLL controllers
Modify clk_get() function in cpu file to work for multiple PLL controllers. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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@ -37,6 +37,7 @@
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#define PLLC_PLLDIV4 0x160
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#define PLLC_PLLDIV4 0x160
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#define PLLC_PLLDIV5 0x164
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#define PLLC_PLLDIV5 0x164
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#define PLLC_PLLDIV6 0x168
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#define PLLC_PLLDIV6 0x168
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#define PLLC_PLLDIV7 0x16c
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#define PLLC_PLLDIV8 0x170
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#define PLLC_PLLDIV8 0x170
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#define PLLC_PLLDIV9 0x174
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#define PLLC_PLLDIV9 0x174
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@ -61,11 +62,9 @@
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#endif
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#endif
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#ifdef CONFIG_SOC_DA8XX
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#ifdef CONFIG_SOC_DA8XX
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const dv_reg * const sysdiv[7] = {
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unsigned int sysdiv[9] = {
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&davinci_pllc_regs->plldiv1, &davinci_pllc_regs->plldiv2,
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PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
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&davinci_pllc_regs->plldiv3, &davinci_pllc_regs->plldiv4,
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PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
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&davinci_pllc_regs->plldiv5, &davinci_pllc_regs->plldiv6,
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&davinci_pllc_regs->plldiv7
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};
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};
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int clk_get(enum davinci_clk_ids id)
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int clk_get(enum davinci_clk_ids id)
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@ -74,19 +73,27 @@ int clk_get(enum davinci_clk_ids id)
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int pllm;
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int pllm;
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int post_div;
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int post_div;
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int pll_out;
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int pll_out;
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unsigned int pll_base;
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pll_out = CONFIG_SYS_OSCIN_FREQ;
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pll_out = CONFIG_SYS_OSCIN_FREQ;
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if (id == DAVINCI_AUXCLK_CLKID)
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if (id == DAVINCI_AUXCLK_CLKID)
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goto out;
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goto out;
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if ((id >> 16) == 1)
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pll_base = (unsigned int)davinci_pllc1_regs;
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else
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pll_base = (unsigned int)davinci_pllc0_regs;
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id &= 0xFFFF;
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/*
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/*
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* Lets keep this simple. Combining operations can result in
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* Lets keep this simple. Combining operations can result in
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* unexpected approximations
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* unexpected approximations
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*/
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*/
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pre_div = (readl(&davinci_pllc_regs->prediv) &
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pre_div = (readl(pll_base + PLLC_PREDIV) &
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DAVINCI_PLLC_DIV_MASK) + 1;
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DAVINCI_PLLC_DIV_MASK) + 1;
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pllm = readl(&davinci_pllc_regs->pllm) + 1;
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pllm = readl(pll_base + PLLC_PLLM) + 1;
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pll_out /= pre_div;
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pll_out /= pre_div;
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pll_out *= pllm;
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pll_out *= pllm;
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@ -94,15 +101,16 @@ int clk_get(enum davinci_clk_ids id)
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if (id == DAVINCI_PLLM_CLKID)
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if (id == DAVINCI_PLLM_CLKID)
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goto out;
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goto out;
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post_div = (readl(&davinci_pllc_regs->postdiv) &
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post_div = (readl(pll_base + PLLC_POSTDIV) &
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DAVINCI_PLLC_DIV_MASK) + 1;
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DAVINCI_PLLC_DIV_MASK) + 1;
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pll_out /= post_div;
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pll_out /= post_div;
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if (id == DAVINCI_PLLC_CLKID)
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if (id == DAVINCI_PLLC_CLKID)
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goto out;
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goto out;
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pll_out /= (readl(sysdiv[id - 1]) & DAVINCI_PLLC_DIV_MASK) + 1;
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pll_out /= (readl(pll_base + sysdiv[id - 1]) &
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DAVINCI_PLLC_DIV_MASK) + 1;
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out:
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out:
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return pll_out;
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return pll_out;
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@ -129,6 +129,7 @@ typedef volatile unsigned int * dv_reg_p;
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#define DAVINCI_TIMER1_BASE 0x01c21000
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#define DAVINCI_TIMER1_BASE 0x01c21000
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#define DAVINCI_WDOG_BASE 0x01c21000
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#define DAVINCI_WDOG_BASE 0x01c21000
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#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
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#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
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#define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000
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#define DAVINCI_PSC0_BASE 0x01c10000
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#define DAVINCI_PSC0_BASE 0x01c10000
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#define DAVINCI_PSC1_BASE 0x01e27000
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#define DAVINCI_PSC1_BASE 0x01e27000
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#define DAVINCI_SPI0_BASE 0x01c41000
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#define DAVINCI_SPI0_BASE 0x01c41000
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@ -387,7 +388,8 @@ struct davinci_pllc_regs {
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dv_reg emucnt1;
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dv_reg emucnt1;
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};
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};
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#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
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#define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
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#define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
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#define DAVINCI_PLLC_DIV_MASK 0x1f
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#define DAVINCI_PLLC_DIV_MASK 0x1f
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#define ASYNC3 get_async3_src()
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#define ASYNC3 get_async3_src()
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