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https://github.com/brain-hackers/u-boot-brain
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net: ks8851: Pass around driver private data
Introduce a private data structure for this driver with embedded struct eth_device and pass it around. This prepares the driver to work with both DM and non-DM systems. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Marek Vasut
parent
8ec27b01bc
commit
b7c6ae2e82
@ -21,42 +21,46 @@
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/*
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* struct ks_net - KS8851 driver private data
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* @dev : legacy non-DM ethernet device structure
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* @iobase : register base
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* @bus_width : i/o bus width.
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* @sharedbus : Multipex(addr and data bus) mode indicator.
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* @extra_byte : number of extra byte prepended rx pkt.
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*/
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struct ks_net {
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struct eth_device dev;
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phys_addr_t iobase;
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int bus_width;
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u16 sharedbus;
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u8 extra_byte;
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} ks_str, *ks;
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};
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#define BE3 0x8000 /* Byte Enable 3 */
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#define BE2 0x4000 /* Byte Enable 2 */
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#define BE1 0x2000 /* Byte Enable 1 */
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#define BE0 0x1000 /* Byte Enable 0 */
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static u8 ks_rdreg8(struct eth_device *dev, u16 offset)
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static u8 ks_rdreg8(struct ks_net *ks, u16 offset)
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{
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u8 shift_bit = offset & 0x03;
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u8 shift_data = (offset & 1) << 3;
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writew(offset | (BE0 << shift_bit), dev->iobase + 2);
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writew(offset | (BE0 << shift_bit), ks->iobase + 2);
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return (u8)(readw(dev->iobase) >> shift_data);
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return (u8)(readw(ks->iobase) >> shift_data);
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}
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static u16 ks_rdreg16(struct eth_device *dev, u16 offset)
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static u16 ks_rdreg16(struct ks_net *ks, u16 offset)
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{
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writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2);
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writew(offset | ((BE1 | BE0) << (offset & 0x02)), ks->iobase + 2);
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return readw(dev->iobase);
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return readw(ks->iobase);
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}
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static void ks_wrreg16(struct eth_device *dev, u16 offset, u16 val)
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static void ks_wrreg16(struct ks_net *ks, u16 offset, u16 val)
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{
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writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2);
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writew(val, dev->iobase);
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writew(offset | ((BE1 | BE0) << (offset & 0x02)), ks->iobase + 2);
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writew(val, ks->iobase);
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}
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/*
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@ -66,12 +70,12 @@ static void ks_wrreg16(struct eth_device *dev, u16 offset, u16 val)
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* @wptr: buffer address to save data
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* @len: length in byte to read
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*/
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static inline void ks_inblk(struct eth_device *dev, u16 *wptr, u32 len)
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static inline void ks_inblk(struct ks_net *ks, u16 *wptr, u32 len)
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{
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len >>= 1;
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while (len--)
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*wptr++ = readw(dev->iobase);
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*wptr++ = readw(ks->iobase);
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}
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/*
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@ -80,42 +84,42 @@ static inline void ks_inblk(struct eth_device *dev, u16 *wptr, u32 len)
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* @wptr: buffer address
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* @len: length in byte to write
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*/
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static inline void ks_outblk(struct eth_device *dev, u16 *wptr, u32 len)
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static inline void ks_outblk(struct ks_net *ks, u16 *wptr, u32 len)
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{
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len >>= 1;
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while (len--)
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writew(*wptr++, dev->iobase);
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writew(*wptr++, ks->iobase);
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}
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static void ks_enable_int(struct eth_device *dev)
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static void ks_enable_int(struct ks_net *ks)
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{
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ks_wrreg16(dev, KS_IER, IRQ_LCI | IRQ_TXI | IRQ_RXI);
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ks_wrreg16(ks, KS_IER, IRQ_LCI | IRQ_TXI | IRQ_RXI);
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}
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static void ks_set_powermode(struct eth_device *dev, unsigned int pwrmode)
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static void ks_set_powermode(struct ks_net *ks, unsigned int pwrmode)
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{
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unsigned int pmecr;
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ks_rdreg16(dev, KS_GRR);
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pmecr = ks_rdreg16(dev, KS_PMECR);
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ks_rdreg16(ks, KS_GRR);
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pmecr = ks_rdreg16(ks, KS_PMECR);
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pmecr &= ~PMECR_PM_MASK;
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pmecr |= pwrmode;
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ks_wrreg16(dev, KS_PMECR, pmecr);
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ks_wrreg16(ks, KS_PMECR, pmecr);
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}
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/*
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* ks_read_config - read chip configuration of bus width.
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* @ks: The chip information
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*/
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static void ks_read_config(struct eth_device *dev)
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static void ks_read_config(struct ks_net *ks)
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{
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u16 reg_data = 0;
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/* Regardless of bus width, 8 bit read should always work. */
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reg_data = ks_rdreg8(dev, KS_CCR) & 0x00FF;
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reg_data |= ks_rdreg8(dev, KS_CCR + 1) << 8;
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reg_data = ks_rdreg8(ks, KS_CCR) & 0x00FF;
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reg_data |= ks_rdreg8(ks, KS_CCR + 1) << 8;
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/* addr/data bus are multiplexed */
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ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED;
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@ -149,58 +153,58 @@ static void ks_read_config(struct eth_device *dev)
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* not currently specify the exact sequence, we have chosen something
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* that seems to work with our device.
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*/
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static void ks_soft_reset(struct eth_device *dev, unsigned int op)
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static void ks_soft_reset(struct ks_net *ks, unsigned int op)
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{
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/* Disable interrupt first */
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ks_wrreg16(dev, KS_IER, 0x0000);
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ks_wrreg16(dev, KS_GRR, op);
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ks_wrreg16(ks, KS_IER, 0x0000);
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ks_wrreg16(ks, KS_GRR, op);
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mdelay(10); /* wait a short time to effect reset */
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ks_wrreg16(dev, KS_GRR, 0);
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ks_wrreg16(ks, KS_GRR, 0);
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mdelay(1); /* wait for condition to clear */
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}
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void ks_enable_qmu(struct eth_device *dev)
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void ks_enable_qmu(struct ks_net *ks)
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{
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u16 w;
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w = ks_rdreg16(dev, KS_TXCR);
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w = ks_rdreg16(ks, KS_TXCR);
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/* Enables QMU Transmit (TXCR). */
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ks_wrreg16(dev, KS_TXCR, w | TXCR_TXE);
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ks_wrreg16(ks, KS_TXCR, w | TXCR_TXE);
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/* Enable RX Frame Count Threshold and Auto-Dequeue RXQ Frame */
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w = ks_rdreg16(dev, KS_RXQCR);
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ks_wrreg16(dev, KS_RXQCR, w | RXQCR_RXFCTE);
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w = ks_rdreg16(ks, KS_RXQCR);
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ks_wrreg16(ks, KS_RXQCR, w | RXQCR_RXFCTE);
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/* Enables QMU Receive (RXCR1). */
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w = ks_rdreg16(dev, KS_RXCR1);
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ks_wrreg16(dev, KS_RXCR1, w | RXCR1_RXE);
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w = ks_rdreg16(ks, KS_RXCR1);
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ks_wrreg16(ks, KS_RXCR1, w | RXCR1_RXE);
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}
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static void ks_disable_qmu(struct eth_device *dev)
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static void ks_disable_qmu(struct ks_net *ks)
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{
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u16 w;
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w = ks_rdreg16(dev, KS_TXCR);
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w = ks_rdreg16(ks, KS_TXCR);
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/* Disables QMU Transmit (TXCR). */
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w &= ~TXCR_TXE;
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ks_wrreg16(dev, KS_TXCR, w);
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ks_wrreg16(ks, KS_TXCR, w);
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/* Disables QMU Receive (RXCR1). */
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w = ks_rdreg16(dev, KS_RXCR1);
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w = ks_rdreg16(ks, KS_RXCR1);
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w &= ~RXCR1_RXE;
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ks_wrreg16(dev, KS_RXCR1, w);
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ks_wrreg16(ks, KS_RXCR1, w);
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}
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static inline void ks_read_qmu(struct eth_device *dev, u16 *buf, u32 len)
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static inline void ks_read_qmu(struct ks_net *ks, u16 *buf, u32 len)
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{
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u32 r = ks->extra_byte & 0x1;
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u32 w = ks->extra_byte - r;
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/* 1. set sudo DMA mode */
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ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI);
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ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
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ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
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ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
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/*
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* 2. read prepend data
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@ -210,41 +214,41 @@ static inline void ks_read_qmu(struct eth_device *dev, u16 *buf, u32 len)
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*/
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if (r)
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ks_rdreg8(dev, 0);
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ks_rdreg8(ks, 0);
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ks_inblk(dev, buf, w + 2 + 2);
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ks_inblk(ks, buf, w + 2 + 2);
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/* 3. read pkt data */
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ks_inblk(dev, buf, ALIGN(len, 4));
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ks_inblk(ks, buf, ALIGN(len, 4));
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/* 4. reset sudo DMA Mode */
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ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL);
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ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL);
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}
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static void ks_rcv(struct eth_device *dev, uchar **pv_data)
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static void ks_rcv(struct ks_net *ks, uchar **pv_data)
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{
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unsigned int frame_cnt;
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u16 sts, len;
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int i;
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frame_cnt = ks_rdreg16(dev, KS_RXFCTR) >> 8;
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frame_cnt = ks_rdreg16(ks, KS_RXFCTR) >> 8;
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/* read all header information */
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for (i = 0; i < frame_cnt; i++) {
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/* Checking Received packet status */
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sts = ks_rdreg16(dev, KS_RXFHSR);
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sts = ks_rdreg16(ks, KS_RXFHSR);
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/* Get packet len from hardware */
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len = ks_rdreg16(dev, KS_RXFHBCR);
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len = ks_rdreg16(ks, KS_RXFHBCR);
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if ((sts & RXFSHR_RXFV) && len && (len < RX_BUF_SIZE)) {
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/* read data block including CRC 4 bytes */
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ks_read_qmu(dev, (u16 *)(*pv_data), len);
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ks_read_qmu(ks, (u16 *)(*pv_data), len);
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/* net_rx_packets buffer size is ok (*pv_data) */
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net_process_received_packet(*pv_data, len);
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pv_data++;
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} else {
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ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_RRXEF);
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ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_RRXEF);
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printf(DRIVERNAME ": bad packet\n");
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}
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}
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@ -256,13 +260,13 @@ static void ks_rcv(struct eth_device *dev, uchar **pv_data)
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*
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* Read and check the TX/RX memory selftest information.
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*/
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static int ks_read_selftest(struct eth_device *dev)
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static int ks_read_selftest(struct ks_net *ks)
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{
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u16 both_done = MBIR_TXMBF | MBIR_RXMBF;
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u16 mbir;
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int ret = 0;
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mbir = ks_rdreg16(dev, KS_MBIR);
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mbir = ks_rdreg16(ks, KS_MBIR);
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if ((mbir & both_done) != both_done) {
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printf(DRIVERNAME ": Memory selftest not finished\n");
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@ -284,55 +288,55 @@ static int ks_read_selftest(struct eth_device *dev)
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return ret;
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}
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static void ks_setup(struct eth_device *dev)
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static void ks_setup(struct ks_net *ks)
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{
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u16 w;
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/* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */
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ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI);
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ks_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI);
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/* Setup Receive Frame Data Pointer Auto-Increment */
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ks_wrreg16(dev, KS_RXFDPR, RXFDPR_RXFPAI);
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ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
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/* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
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ks_wrreg16(dev, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
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ks_wrreg16(ks, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
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/* Setup RxQ Command Control (RXQCR) */
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ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL);
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ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL);
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/*
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* set the force mode to half duplex, default is full duplex
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* because if the auto-negotiation fails, most switch uses
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* half-duplex.
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*/
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w = ks_rdreg16(dev, KS_P1MBCR);
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w = ks_rdreg16(ks, KS_P1MBCR);
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w &= ~P1MBCR_FORCE_FDX;
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ks_wrreg16(dev, KS_P1MBCR, w);
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ks_wrreg16(ks, KS_P1MBCR, w);
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w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP;
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ks_wrreg16(dev, KS_TXCR, w);
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ks_wrreg16(ks, KS_TXCR, w);
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w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC;
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/* Normal mode */
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w |= RXCR1_RXPAFMA;
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ks_wrreg16(dev, KS_RXCR1, w);
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ks_wrreg16(ks, KS_RXCR1, w);
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}
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static void ks_setup_int(struct eth_device *dev)
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static void ks_setup_int(struct ks_net *ks)
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{
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/* Clear the interrupts status of the hardware. */
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ks_wrreg16(dev, KS_ISR, 0xffff);
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ks_wrreg16(ks, KS_ISR, 0xffff);
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}
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static int ks8851_mll_detect_chip(struct eth_device *dev)
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static int ks8851_mll_detect_chip(struct ks_net *ks)
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{
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unsigned short val;
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ks_read_config(dev);
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ks_read_config(ks);
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val = ks_rdreg16(dev, KS_CIDER);
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val = ks_rdreg16(ks, KS_CIDER);
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if (val == 0xffff) {
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/* Special case -- no chip present */
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@ -353,63 +357,65 @@ static int ks8851_mll_detect_chip(struct eth_device *dev)
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return 0;
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}
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static void ks8851_mll_reset(struct eth_device *dev)
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static void ks8851_mll_reset(struct ks_net *ks)
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{
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/* wake up powermode to normal mode */
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ks_set_powermode(dev, PMECR_PM_NORMAL);
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ks_set_powermode(ks, PMECR_PM_NORMAL);
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mdelay(1); /* wait for normal mode to take effect */
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/* Disable interrupt and reset */
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ks_soft_reset(dev, GRR_GSR);
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ks_soft_reset(ks, GRR_GSR);
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/* turn off the IRQs and ack any outstanding */
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ks_wrreg16(dev, KS_IER, 0x0000);
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ks_wrreg16(dev, KS_ISR, 0xffff);
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ks_wrreg16(ks, KS_IER, 0x0000);
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ks_wrreg16(ks, KS_ISR, 0xffff);
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/* shutdown RX/TX QMU */
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ks_disable_qmu(dev);
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ks_disable_qmu(ks);
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}
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static void ks8851_mll_phy_configure(struct eth_device *dev)
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static void ks8851_mll_phy_configure(struct ks_net *ks)
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{
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u16 data;
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ks_setup(dev);
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ks_setup_int(dev);
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ks_setup(ks);
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ks_setup_int(ks);
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/* Probing the phy */
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data = ks_rdreg16(dev, KS_OBCR);
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ks_wrreg16(dev, KS_OBCR, data | OBCR_ODS_16MA);
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data = ks_rdreg16(ks, KS_OBCR);
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ks_wrreg16(ks, KS_OBCR, data | OBCR_ODS_16MA);
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debug(DRIVERNAME ": phy initialized\n");
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}
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static void ks8851_mll_enable(struct eth_device *dev)
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static void ks8851_mll_enable(struct ks_net *ks)
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{
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ks_wrreg16(dev, KS_ISR, 0xffff);
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ks_enable_int(dev);
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ks_enable_qmu(dev);
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ks_wrreg16(ks, KS_ISR, 0xffff);
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ks_enable_int(ks);
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ks_enable_qmu(ks);
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}
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static int ks8851_mll_init(struct eth_device *dev, bd_t *bd)
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{
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if (ks_read_selftest(dev)) {
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struct ks_net *ks = container_of(dev, struct ks_net, dev);
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if (ks_read_selftest(ks)) {
|
||||
printf(DRIVERNAME ": Selftest failed\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
ks8851_mll_reset(dev);
|
||||
ks8851_mll_reset(ks);
|
||||
|
||||
/* Configure the PHY, initialize the link state */
|
||||
ks8851_mll_phy_configure(dev);
|
||||
ks8851_mll_phy_configure(ks);
|
||||
|
||||
/* Turn on Tx + Rx */
|
||||
ks8851_mll_enable(dev);
|
||||
ks8851_mll_enable(ks);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ks_write_qmu(struct eth_device *dev, u8 *pdata, u16 len)
|
||||
static void ks_write_qmu(struct ks_net *ks, u8 *pdata, u16 len)
|
||||
{
|
||||
__le16 txw[2];
|
||||
/* start header at txb[0] to align txw entries */
|
||||
@ -417,22 +423,23 @@ static void ks_write_qmu(struct eth_device *dev, u8 *pdata, u16 len)
|
||||
txw[1] = cpu_to_le16(len);
|
||||
|
||||
/* 1. set sudo-DMA mode */
|
||||
ks_wrreg16(dev, KS_TXFDPR, TXFDPR_TXFPAI);
|
||||
ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
|
||||
ks_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI);
|
||||
ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL | RXQCR_SDA);
|
||||
/* 2. write status/length info */
|
||||
ks_outblk(dev, txw, 4);
|
||||
ks_outblk(ks, txw, 4);
|
||||
/* 3. write pkt data */
|
||||
ks_outblk(dev, (u16 *)pdata, ALIGN(len, 4));
|
||||
ks_outblk(ks, (u16 *)pdata, ALIGN(len, 4));
|
||||
/* 4. reset sudo-DMA mode */
|
||||
ks_wrreg16(dev, KS_RXQCR, RXQCR_CMD_CNTL);
|
||||
ks_wrreg16(ks, KS_RXQCR, RXQCR_CMD_CNTL);
|
||||
/* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
|
||||
ks_wrreg16(dev, KS_TXQCR, TXQCR_METFE);
|
||||
ks_wrreg16(ks, KS_TXQCR, TXQCR_METFE);
|
||||
/* 6. wait until TXQCR_METFE is auto-cleared */
|
||||
do { } while (ks_rdreg16(dev, KS_TXQCR) & TXQCR_METFE);
|
||||
do { } while (ks_rdreg16(ks, KS_TXQCR) & TXQCR_METFE);
|
||||
}
|
||||
|
||||
static int ks8851_mll_send(struct eth_device *dev, void *packet, int length)
|
||||
{
|
||||
struct ks_net *ks = container_of(dev, struct ks_net, dev);
|
||||
u8 *data = (u8 *)packet;
|
||||
u16 tmplen = (u16)length;
|
||||
u16 retv;
|
||||
@ -441,9 +448,9 @@ static int ks8851_mll_send(struct eth_device *dev, void *packet, int length)
|
||||
* Extra space are required:
|
||||
* 4 byte for alignment, 4 for status/length, 4 for CRC
|
||||
*/
|
||||
retv = ks_rdreg16(dev, KS_TXMIR) & 0x1fff;
|
||||
retv = ks_rdreg16(ks, KS_TXMIR) & 0x1fff;
|
||||
if (retv >= tmplen + 12) {
|
||||
ks_write_qmu(dev, data, tmplen);
|
||||
ks_write_qmu(ks, data, tmplen);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -453,7 +460,9 @@ static int ks8851_mll_send(struct eth_device *dev, void *packet, int length)
|
||||
|
||||
static void ks8851_mll_halt(struct eth_device *dev)
|
||||
{
|
||||
ks8851_mll_reset(dev);
|
||||
struct ks_net *ks = container_of(dev, struct ks_net, dev);
|
||||
|
||||
ks8851_mll_reset(ks);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -464,20 +473,21 @@ static void ks8851_mll_halt(struct eth_device *dev)
|
||||
*/
|
||||
static int ks8851_mll_recv(struct eth_device *dev)
|
||||
{
|
||||
struct ks_net *ks = container_of(dev, struct ks_net, dev);
|
||||
u16 status;
|
||||
|
||||
status = ks_rdreg16(dev, KS_ISR);
|
||||
status = ks_rdreg16(ks, KS_ISR);
|
||||
|
||||
ks_wrreg16(dev, KS_ISR, status);
|
||||
ks_wrreg16(ks, KS_ISR, status);
|
||||
|
||||
if (status & IRQ_RXI)
|
||||
ks_rcv(dev, (uchar **)net_rx_packets);
|
||||
ks_rcv(ks, (uchar **)net_rx_packets);
|
||||
|
||||
if (status & IRQ_LDI) {
|
||||
u16 pmecr = ks_rdreg16(dev, KS_PMECR);
|
||||
u16 pmecr = ks_rdreg16(ks, KS_PMECR);
|
||||
|
||||
pmecr &= ~PMECR_WKEVT_MASK;
|
||||
ks_wrreg16(dev, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
|
||||
ks_wrreg16(ks, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
|
||||
}
|
||||
|
||||
return 0;
|
||||
@ -485,45 +495,44 @@ static int ks8851_mll_recv(struct eth_device *dev)
|
||||
|
||||
static int ks8851_mll_write_hwaddr(struct eth_device *dev)
|
||||
{
|
||||
struct ks_net *ks = container_of(dev, struct ks_net, dev);
|
||||
u16 addrl, addrm, addrh;
|
||||
|
||||
addrh = (dev->enetaddr[0] << 8) | dev->enetaddr[1];
|
||||
addrm = (dev->enetaddr[2] << 8) | dev->enetaddr[3];
|
||||
addrl = (dev->enetaddr[4] << 8) | dev->enetaddr[5];
|
||||
addrh = (ks->dev.enetaddr[0] << 8) | ks->dev.enetaddr[1];
|
||||
addrm = (ks->dev.enetaddr[2] << 8) | ks->dev.enetaddr[3];
|
||||
addrl = (ks->dev.enetaddr[4] << 8) | ks->dev.enetaddr[5];
|
||||
|
||||
ks_wrreg16(dev, KS_MARH, addrh);
|
||||
ks_wrreg16(dev, KS_MARM, addrm);
|
||||
ks_wrreg16(dev, KS_MARL, addrl);
|
||||
ks_wrreg16(ks, KS_MARH, addrh);
|
||||
ks_wrreg16(ks, KS_MARM, addrm);
|
||||
ks_wrreg16(ks, KS_MARL, addrl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ks8851_mll_initialize(u8 dev_num, int base_addr)
|
||||
{
|
||||
struct eth_device *dev;
|
||||
struct ks_net *ks;
|
||||
|
||||
dev = calloc(1, sizeof(*dev));
|
||||
if (!dev)
|
||||
ks = calloc(1, sizeof(*ks));
|
||||
if (!ks)
|
||||
return -ENOMEM;
|
||||
|
||||
dev->iobase = base_addr;
|
||||
|
||||
ks = &ks_str;
|
||||
ks->iobase = base_addr;
|
||||
|
||||
/* Try to detect chip. Will fail if not present. */
|
||||
if (ks8851_mll_detect_chip(dev)) {
|
||||
free(dev);
|
||||
if (ks8851_mll_detect_chip(ks)) {
|
||||
free(ks);
|
||||
return -1;
|
||||
}
|
||||
|
||||
dev->init = ks8851_mll_init;
|
||||
dev->halt = ks8851_mll_halt;
|
||||
dev->send = ks8851_mll_send;
|
||||
dev->recv = ks8851_mll_recv;
|
||||
dev->write_hwaddr = ks8851_mll_write_hwaddr;
|
||||
sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num);
|
||||
ks->dev.init = ks8851_mll_init;
|
||||
ks->dev.halt = ks8851_mll_halt;
|
||||
ks->dev.send = ks8851_mll_send;
|
||||
ks->dev.recv = ks8851_mll_recv;
|
||||
ks->dev.write_hwaddr = ks8851_mll_write_hwaddr;
|
||||
sprintf(ks->dev.name, "%s-%hu", DRIVERNAME, dev_num);
|
||||
|
||||
eth_register(dev);
|
||||
eth_register(&ks->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user