mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 04:36:16 +09:00
Merge branch 'master' of git://git.denx.de/u-boot-i2c
This commit is contained in:
Wolfgang Denk
commit
b76335178e
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@ -27,7 +27,7 @@
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#include "omap24xx_i2c.h"
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#define I2C_TIMEOUT 10
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#define I2C_TIMEOUT 1000
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static void wait_for_bb (void);
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static u16 wait_for_pin (void);
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@ -159,58 +159,56 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
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/* no stop bit needed here */
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writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con);
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status = wait_for_pin ();
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if (status & I2C_STAT_XRDY) {
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/* Important: have to use byte access */
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writeb (regoffset, &i2c_base->data);
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udelay (20000);
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if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
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/* send register offset */
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while (1) {
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status = wait_for_pin();
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if (status == 0 || status & I2C_STAT_NACK) {
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i2c_error = 1;
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goto read_exit;
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}
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if (status & I2C_STAT_XRDY) {
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/* Important: have to use byte access */
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writeb(regoffset, &i2c_base->data);
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writew(I2C_STAT_XRDY, &i2c_base->stat);
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}
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if (status & I2C_STAT_ARDY) {
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writew(I2C_STAT_ARDY, &i2c_base->stat);
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break;
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}
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} else {
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i2c_error = 1;
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}
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if (!i2c_error) {
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writew (I2C_CON_EN, &i2c_base->con);
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while (readw(&i2c_base->stat) &
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(I2C_STAT_XRDY | I2C_STAT_ARDY)) {
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udelay (10000);
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/* Have to clear pending interrupt to clear I2C_STAT */
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writew (0xFFFF, &i2c_base->stat);
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/* set slave address */
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writew(devaddr, &i2c_base->sa);
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/* read one byte from slave */
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writew(1, &i2c_base->cnt);
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/* need stop bit here */
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writew(I2C_CON_EN | I2C_CON_MST |
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I2C_CON_STT | I2C_CON_STP,
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&i2c_base->con);
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/* receive data */
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while (1) {
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status = wait_for_pin();
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if (status == 0 || status & I2C_STAT_NACK) {
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i2c_error = 1;
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goto read_exit;
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}
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/* set slave address */
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writew (devaddr, &i2c_base->sa);
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/* read one byte from slave */
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writew (1, &i2c_base->cnt);
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/* need stop bit here */
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writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
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&i2c_base->con);
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status = wait_for_pin ();
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if (status & I2C_STAT_RRDY) {
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#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
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defined(CONFIG_OMAP44XX)
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*value = readb (&i2c_base->data);
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*value = readb(&i2c_base->data);
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#else
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*value = readw (&i2c_base->data);
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*value = readw(&i2c_base->data);
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#endif
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udelay (20000);
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} else {
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i2c_error = 1;
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writew(I2C_STAT_RRDY, &i2c_base->stat);
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}
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if (!i2c_error) {
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writew (I2C_CON_EN, &i2c_base->con);
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while (readw (&i2c_base->stat) &
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(I2C_STAT_RRDY | I2C_STAT_ARDY)) {
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udelay (10000);
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writew (0xFFFF, &i2c_base->stat);
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}
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if (status & I2C_STAT_ARDY) {
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writew(I2C_STAT_ARDY, &i2c_base->stat);
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break;
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}
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}
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read_exit:
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flush_fifo();
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writew (0xFFFF, &i2c_base->stat);
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writew (0, &i2c_base->cnt);
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@ -220,7 +218,7 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
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static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
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{
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int i2c_error = 0;
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u16 status, stat;
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u16 status;
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/* wait until bus not busy */
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wait_for_bb ();
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@ -233,49 +231,55 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
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writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
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I2C_CON_STP, &i2c_base->con);
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/* wait until state change */
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status = wait_for_pin ();
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if (status & I2C_STAT_XRDY) {
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while (1) {
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status = wait_for_pin();
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if (status == 0 || status & I2C_STAT_NACK) {
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i2c_error = 1;
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goto write_exit;
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}
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if (status & I2C_STAT_XRDY) {
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#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
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defined(CONFIG_OMAP44XX)
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/* send out 1 byte */
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writeb (regoffset, &i2c_base->data);
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writew (I2C_STAT_XRDY, &i2c_base->stat);
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/* send register offset */
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writeb(regoffset, &i2c_base->data);
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writew(I2C_STAT_XRDY, &i2c_base->stat);
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status = wait_for_pin ();
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if ((status & I2C_STAT_XRDY)) {
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/* send out next 1 byte */
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writeb (value, &i2c_base->data);
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writew (I2C_STAT_XRDY, &i2c_base->stat);
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} else {
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i2c_error = 1;
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}
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while (1) {
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status = wait_for_pin();
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if (status == 0 || status & I2C_STAT_NACK) {
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i2c_error = 1;
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goto write_exit;
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}
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if (status & I2C_STAT_XRDY) {
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/* send data */
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writeb(value, &i2c_base->data);
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writew(I2C_STAT_XRDY, &i2c_base->stat);
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}
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if (status & I2C_STAT_ARDY) {
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writew(I2C_STAT_ARDY, &i2c_base->stat);
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break;
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}
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}
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break;
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#else
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/* send out two bytes */
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writew ((value << 8) + regoffset, &i2c_base->data);
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/* send out two bytes */
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writew((value << 8) + regoffset, &i2c_base->data);
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writew(I2C_STAT_XRDY, &i2c_base->stat);
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#endif
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/* must have enough delay to allow BB bit to go low */
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udelay (50000);
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if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
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i2c_error = 1;
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}
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} else {
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if (status & I2C_STAT_ARDY) {
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writew(I2C_STAT_ARDY, &i2c_base->stat);
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break;
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}
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}
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wait_for_bb();
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status = readw(&i2c_base->stat);
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if (status & I2C_STAT_NACK)
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i2c_error = 1;
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}
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if (!i2c_error) {
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int eout = 200;
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writew (I2C_CON_EN, &i2c_base->con);
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while ((stat = readw (&i2c_base->stat)) || (readw (&i2c_base->con) & I2C_CON_MST)) {
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udelay (1000);
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/* have to read to clear intrrupt */
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writew (0xFFFF, &i2c_base->stat);
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if(--eout == 0) /* better leave with error than hang */
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break;
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}
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}
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write_exit:
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flush_fifo();
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writew (0xFFFF, &i2c_base->stat);
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writew (0, &i2c_base->cnt);
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@ -306,6 +310,7 @@ static void flush_fifo(void)
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int i2c_probe (uchar chip)
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{
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u16 status;
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int res = 1; /* default = fail */
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if (chip == readw (&i2c_base->oa)) {
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@ -321,19 +326,37 @@ int i2c_probe (uchar chip)
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writew (chip, &i2c_base->sa);
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/* stop bit needed here */
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writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con);
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/* enough delay for the NACK bit set */
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udelay (50000);
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if (!(readw (&i2c_base->stat) & I2C_STAT_NACK)) {
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res = 0; /* success case */
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flush_fifo();
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writew(0xFFFF, &i2c_base->stat);
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} else {
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writew(0xFFFF, &i2c_base->stat); /* failue, clear sources*/
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writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); /* finish up xfer */
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udelay(20000);
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wait_for_bb ();
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while (1) {
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status = wait_for_pin();
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if (status == 0) {
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res = 1;
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goto probe_exit;
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}
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if (status & I2C_STAT_NACK) {
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res = 1;
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writew(0xff, &i2c_base->stat);
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writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con);
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wait_for_bb ();
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break;
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}
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if (status & I2C_STAT_ARDY) {
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writew(I2C_STAT_ARDY, &i2c_base->stat);
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break;
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}
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if (status & I2C_STAT_RRDY) {
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res = 0;
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#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
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defined(CONFIG_OMAP44XX)
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readb(&i2c_base->data);
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#else
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readw(&i2c_base->data);
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#endif
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writew(I2C_STAT_RRDY, &i2c_base->stat);
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}
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}
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probe_exit:
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flush_fifo();
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writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/
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writew(0xFFFF, &i2c_base->stat);
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@ -392,13 +415,13 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
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static void wait_for_bb (void)
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{
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int timeout = 10;
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int timeout = I2C_TIMEOUT;
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u16 stat;
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writew(0xFFFF, &i2c_base->stat); /* clear current interruts...*/
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while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
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writew (stat, &i2c_base->stat);
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udelay (50000);
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udelay(1000);
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}
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if (timeout <= 0) {
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@ -411,7 +434,7 @@ static void wait_for_bb (void)
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static u16 wait_for_pin (void)
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{
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u16 status;
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int timeout = 10;
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int timeout = I2C_TIMEOUT;
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do {
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udelay (1000);
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@ -424,8 +447,10 @@ static u16 wait_for_pin (void)
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if (timeout <= 0) {
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printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
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readw (&i2c_base->stat));
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writew(0xFFFF, &i2c_base->stat);
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}
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writew(0xFFFF, &i2c_base->stat);
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status = 0;
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}
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return status;
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}
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