arm: rmobile: Add HopeRun HiHope RZ/G2M board support
The HiHope RZ/G2M board from HopeRun consists of main board (HopeRun HiHope RZ/G2M main board) and sub board(HopeRun HiHope RZ/G2M sub board). The HiHope RZ/G2M sub board sits below the HiHope RZ/G2M main board. This patch adds the required board support to boot HopeRun HiHope RZ/G2M board. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
This commit is contained in:
Biju Das
Marek Vasut
parent
40ac794524
commit
b650c83825
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@ -822,6 +822,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
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r8a774a1-beacon-rzg2m-kit.dtb \
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r8a774b1-beacon-rzg2n-kit.dtb \
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r8a774e1-beacon-rzg2h-kit.dtb \
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r8a774a1-hihope-rzg2m-u-boot.dtb \
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r8a77950-ulcb-u-boot.dtb \
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r8a77950-salvator-x-u-boot.dtb \
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r8a77960-ulcb-u-boot.dtb \
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@ -4,6 +4,8 @@ menu "Select Target SoC"
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config R8A774A1
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bool "Renesas SoC R8A774A1"
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imply CLK_R8A774A1
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imply PINCTRL_PFC_R8A774A1
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config R8A774B1
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bool "Renesas SoC R8A774B1"
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@ -99,6 +101,15 @@ config TARGET_EBISU
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help
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Support for Renesas R-Car Gen3 Ebisu platform
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config TARGET_HIHOPE_RZG2
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bool "HiHope RZ/G2 board"
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imply R8A774A1
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imply SYS_MALLOC_F
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imply MULTI_DTB_FIT
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imply MULTI_DTB_FIT_USER_DEFINED_AREA
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help
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Support for RZG2 HiHope platform
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config TARGET_SALVATOR_X
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bool "Salvator-X board"
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imply R8A7795
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@ -133,12 +144,15 @@ source "board/renesas/ebisu/Kconfig"
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source "board/renesas/salvator-x/Kconfig"
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source "board/renesas/ulcb/Kconfig"
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source "board/beacon/beacon-rzg2m/Kconfig"
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source "board/hoperun/hihope-rzg2/Kconfig"
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config MULTI_DTB_FIT_UNCOMPRESS_SZ
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default 0x80000 if TARGET_HIHOPE_RZG2
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default 0x80000 if TARGET_SALVATOR_X
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default 0x80000 if TARGET_ULCB
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config MULTI_DTB_FIT_USER_DEF_ADDR
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default 0x49000000 if TARGET_HIHOPE_RZG2
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default 0x49000000 if TARGET_SALVATOR_X
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default 0x49000000 if TARGET_ULCB
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@ -0,0 +1,15 @@
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if TARGET_HIHOPE_RZG2
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config SYS_SOC
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default "rmobile"
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config SYS_BOARD
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default "hihope-rzg2"
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config SYS_VENDOR
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default "hoperun"
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config SYS_CONFIG_NAME
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default "hihope-rzg2"
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endif
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@ -0,0 +1,6 @@
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HIHOPE_RZG2 BOARD
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M: Biju Das <biju.das.jz@bp.renesas.com>
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S: Maintained
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F: board/hoperun/hihope-rzg2/
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F: include/configs/hihope-rzg2.h
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F: configs/hihope_rzg2_defconfig
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@ -0,0 +1,9 @@
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#
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# board/hoperun/hihope-rzg2/Makefile
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#
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# Copyright (C) 2021 Renesas Electronics Corporation
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := hihope-rzg2.o ../../renesas/rcar-common/common.o
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@ -0,0 +1,105 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* board/hoperun/hihope-rzg2/hihope-rzg2.c
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* This file is HiHope RZ/G2M board support.
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*
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* Copyright (C) 2021 Renesas Electronics Corporation
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*/
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#include <common.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/rcar-mstp.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/libfdt.h>
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#define RST_BASE 0xE6160000
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#define RST_CA57RESCNT (RST_BASE + 0x40)
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#define RST_CA53RESCNT (RST_BASE + 0x44)
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#define RST_CA57_CODE 0xA5A5000F
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#define RST_CA53_CODE 0x5A5A000F
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DECLARE_GLOBAL_DATA_PTR;
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#define HSUSB_MSTP704 BIT(4) /* HSUSB */
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/* HSUSB block registers */
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#define HSUSB_REG_LPSTS 0xE6590102
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#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
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#define HSUSB_REG_UGCTRL2 0xE6590184
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#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
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#define HSUSB_REG_UGCTRL2_RESERVED_3 0x1 /* bit[3:0] should be B'0001 */
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#define PRR_REGISTER (0xFFF00044)
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int board_init(void)
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{
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u32 i;
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/* address of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
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/* Configure the HSUSB block */
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mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
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/*
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* We need to add a barrier instruction after HSUSB module stop release.
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* This barrier instruction can be either reading back the same MSTP
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* register or any other register in the same IP block. So like linux
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* adding check for MSTPSR register, which indicates the clock has been
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* started.
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*/
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for (i = 1000; i > 0; --i) {
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if (!(readl(MSTPSR7) & HSUSB_MSTP704))
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break;
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cpu_relax();
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}
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/* Select EHCI/OHCI host module for USB2.0 ch0 */
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writel(HSUSB_REG_UGCTRL2_USB0SEL_EHCI | HSUSB_REG_UGCTRL2_RESERVED_3,
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HSUSB_REG_UGCTRL2);
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/* low power status */
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setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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unsigned long midr, cputype;
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asm volatile("mrs %0, midr_el1" : "=r" (midr));
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cputype = (midr >> 4) & 0xfff;
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if (cputype == 0xd03)
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writel(RST_CA53_CODE, RST_CA53RESCNT);
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else
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writel(RST_CA57_CODE, RST_CA57RESCNT);
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}
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#if defined(CONFIG_MULTI_DTB_FIT)
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/* If the firmware passed a device tree, use it for board identification. */
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extern u64 rcar_atf_boot_args[];
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static bool is_hoperun_hihope_rzg2_board(const char *board_name)
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{
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void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
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bool ret = false;
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if ((fdt_magic(atf_fdt_blob) == FDT_MAGIC) &&
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(fdt_node_check_compatible(atf_fdt_blob, 0, board_name) == 0))
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ret = true;
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return ret;
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}
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int board_fit_config_name_match(const char *name)
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{
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if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2m") &&
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!strcmp(name, "r8a774a1-hihope-rzg2m-u-boot"))
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return 0;
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return -1;
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}
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#endif
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@ -0,0 +1,82 @@
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CONFIG_ARM=y
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CONFIG_ARCH_CPU_INIT=y
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CONFIG_ARCH_RMOBILE=y
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CONFIG_SYS_TEXT_BASE=0x50000000
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CONFIG_ENV_SIZE=0x20000
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CONFIG_ENV_OFFSET=0xFFFE0000
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CONFIG_DM_GPIO=y
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CONFIG_RCAR_GEN3=y
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CONFIG_TARGET_HIHOPE_RZG2=y
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# CONFIG_SPL is not set
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CONFIG_DEFAULT_DEVICE_TREE="r8a774a1-hihope-rzg2m-u-boot"
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CONFIG_FIT=y
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CONFIG_SUPPORT_RAW_INITRD=y
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
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CONFIG_DEFAULT_FDT_FILE="r8a774a1-hihope-rzg2m.dtb"
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# CONFIG_BOARD_EARLY_INIT_F is not set
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_BOOTZ=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_PART=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_OF_CONTROL=y
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CONFIG_OF_LIST="r8a774a1-hihope-rzg2m-u-boot"
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CONFIG_MULTI_DTB_FIT_LZO=y
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CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_SYS_MMC_ENV_DEV=1
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CONFIG_SYS_MMC_ENV_PART=2
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CONFIG_VERSION_VARIABLE=y
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CONFIG_REGMAP=y
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CONFIG_SYSCON=y
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CONFIG_CLK=y
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CONFIG_CLK_RENESAS=y
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CONFIG_GPIO_HOG=y
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CONFIG_RCAR_GPIO=y
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CONFIG_DM_PCA953X=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_RCAR_I2C=y
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CONFIG_SYS_I2C_RCAR_IIC=y
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CONFIG_DM_MMC=y
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CONFIG_MMC_IO_VOLTAGE=y
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CONFIG_MMC_UHS_SUPPORT=y
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CONFIG_MMC_HS400_SUPPORT=y
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CONFIG_RENESAS_SDHI=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_BAR=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_SPI_FLASH_USE_4K_SECTORS=y
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CONFIG_BITBANGMII=y
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CONFIG_PHY_REALTEK=y
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CONFIG_DM_ETH=y
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CONFIG_RENESAS_RAVB=y
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CONFIG_DM_REGULATOR=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_GPIO=y
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CONFIG_SCIF_CONSOLE=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_RENESAS_RPC_SPI=y
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CONFIG_TEE=y
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CONFIG_OPTEE=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_GENERIC=y
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CONFIG_USB_STORAGE=y
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CONFIG_OF_LIBFDT_OVERLAY=y
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@ -0,0 +1,20 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* include/configs/hihope-rzg2.h
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* This file is HOPERUN HiHope RZ/G2 board configuration.
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*
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* Copyright (C) 2020 Renesas Electronics Corporation
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*/
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#ifndef __HIHOPE_RZG2_H
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#define __HIHOPE_RZG2_H
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#include "rcar-gen3-common.h"
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/* Ethernet RAVB */
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#define CONFIG_BITBANGMII_MULTI
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/* Generic Timer Definitions (use in assembler source) */
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#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
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#endif /* __HIHOPE_RZG2_H */
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