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https://github.com/brain-hackers/u-boot-brain
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arm: dts: k3-am642: Add r5 specific dt support
Add initial support for dt that runs on r5. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
This commit is contained in:
Dave Gerlach
Lokesh Vutla
parent
5db2915a72
commit
b6059ddc45
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@ -1056,7 +1056,8 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
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k3-j721e-r5-common-proc-board.dtb \
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k3-j7200-common-proc-board.dtb \
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k3-j7200-r5-common-proc-board.dtb
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dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb
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dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
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k3-am642-r5-evm.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt7622-rfb.dtb \
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58
arch/arm/dts/k3-am642-evm-u-boot.dtsi
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58
arch/arm/dts/k3-am642-evm-u-boot.dtsi
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@ -0,0 +1,58 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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tick-timer = &timer1;
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};
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};
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&cbass_main{
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u-boot,dm-spl;
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timer1: timer@2400000 {
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compatible = "ti,omap5430-timer";
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reg = <0x0 0x2400000 0x0 0x80>;
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ti,timer-alwon;
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clock-frequency = <250000000>;
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u-boot,dm-spl;
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};
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};
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&main_uart0 {
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u-boot,dm-spl;
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};
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&dmss {
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u-boot,dm-spl;
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};
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&secure_proxy_main {
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u-boot,dm-spl;
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};
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&dmsc {
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u-boot,dm-spl;
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};
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&k3_pds {
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u-boot,dm-spl;
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};
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&k3_clks {
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u-boot,dm-spl;
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};
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&k3_reset {
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u-boot,dm-spl;
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};
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&sdhci0 {
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u-boot,dm-spl;
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};
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&sdhci1 {
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u-boot,dm-spl;
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};
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169
arch/arm/dts/k3-am642-r5-evm.dts
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169
arch/arm/dts/k3-am642-r5-evm.dts
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@ -0,0 +1,169 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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#include "k3-am642.dtsi"
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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tick-timer = &timer1;
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};
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aliases {
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remoteproc0 = &sysctrler;
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remoteproc1 = &a53_0;
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};
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memory@80000000 {
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device_type = "memory";
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/* 2G RAM */
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reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
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};
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a53_0: a53@0 {
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compatible = "ti,am654-rproc";
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reg = <0x00 0x00a90000 0x00 0x10>;
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power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
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<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
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resets = <&k3_reset 135 0>;
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clocks = <&k3_clks 61 0>;
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assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
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assigned-clock-parents = <&k3_clks 61 2>;
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assigned-clock-rates = <200000000>, <1000000000>;
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ti,sci = <&dmsc>;
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ti,sci-proc-id = <32>;
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ti,sci-host-id = <10>;
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u-boot,dm-spl;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure_ddr: optee@9e800000 {
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reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
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alignment = <0x1000>;
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no-map;
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};
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};
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clk_200mhz: dummy-clock-200mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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u-boot,dm-spl;
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};
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};
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&cbass_main {
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sysctrler: sysctrler {
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compatible = "ti,am654-system-controller";
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mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
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mbox-names = "tx", "rx";
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u-boot,dm-spl;
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};
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};
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&main_pmx0 {
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u-boot,dm-spl;
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main_uart0_pins_default: main-uart0-pins-default {
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u-boot,dm-spl;
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
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AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
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AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
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AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
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>;
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};
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main_uart1_pins_default: main-uart1-pins-default {
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u-boot,dm-spl;
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
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AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
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AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
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AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
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>;
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};
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main_mmc0_pins_default: main-mmc0-pins-default {
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u-boot,dm-spl;
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pinctrl-single,pins = <
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AM64X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
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AM64X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
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AM64X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
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AM64X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
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AM64X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
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AM64X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
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AM64X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
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AM64X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
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AM64X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
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AM64X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
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AM64X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
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>;
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};
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main_mmc1_pins_default: main-mmc1-pins-default {
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u-boot,dm-spl;
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
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AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
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AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
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AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
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AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
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AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
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AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
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AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
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>;
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};
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};
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&dmsc {
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mboxes= <&secure_proxy_main 0>,
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<&secure_proxy_main 1>,
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<&secure_proxy_main 0>;
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mbox-names = "rx", "tx", "notify";
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ti,host-id = <35>;
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ti,secure-host;
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};
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&main_uart0 {
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/delete-property/ power-domains;
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/delete-property/ clocks;
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/delete-property/ clock-names;
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pinctrl-names = "default";
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pinctrl-0 = <&main_uart0_pins_default>;
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status = "okay";
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};
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&main_uart1 {
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u-boot,dm-spl;
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pinctrl-names = "default";
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pinctrl-0 = <&main_uart1_pins_default>;
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};
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&sdhci0 {
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/delete-property/ power-domains;
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clocks = <&clk_200mhz>;
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clock-names = "clk_xin";
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ti,driver-strength-ohm = <50>;
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disable-wp;
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pinctrl-0 = <&main_mmc0_pins_default>;
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};
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&sdhci1 {
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/delete-property/ power-domains;
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clocks = <&clk_200mhz>;
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clock-names = "clk_xin";
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ti,driver-strength-ohm = <50>;
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disable-wp;
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pinctrl-0 = <&main_mmc1_pins_default>;
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};
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#include "k3-am642-evm-u-boot.dtsi"
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