mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-29 16:10:24 +09:00
ppc4xx: Maintenance patch for VOH405 boards
- add EEPROM write protection - initialize NAND GPIOs - use correct io accessors - slow down I2C clock to 100kHz - enable ext. I2C bus - cleanup Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
This commit is contained in:
Matthias Fuchs
Stefan Roese
parent
c05569066d
commit
b56bd0fcfc
@ -22,6 +22,7 @@
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/processor.h>
|
||||
#include <command.h>
|
||||
#include <malloc.h>
|
||||
@ -112,11 +113,11 @@ int misc_init_f (void)
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
|
||||
volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
|
||||
volatile unsigned short *lcd_contrast =
|
||||
unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
|
||||
unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
|
||||
unsigned short *lcd_contrast =
|
||||
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
|
||||
volatile unsigned short *lcd_backlight =
|
||||
unsigned short *lcd_backlight =
|
||||
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
|
||||
unsigned char *dst;
|
||||
ulong len = sizeof(fpgadata);
|
||||
@ -180,25 +181,37 @@ int misc_init_r (void)
|
||||
/*
|
||||
* Reset FPGA via FPGA_INIT pin
|
||||
*/
|
||||
out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT); /* reset low */
|
||||
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT); /* reset low */
|
||||
udelay(1000); /* wait 1ms */
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT); /* reset high */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT); /* reset high */
|
||||
udelay(1000); /* wait 1ms */
|
||||
|
||||
/*
|
||||
* Reset external DUARTs
|
||||
*/
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
|
||||
udelay(10); /* wait 10us */
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
|
||||
udelay(1000); /* wait 1ms */
|
||||
|
||||
/*
|
||||
* Set NAND-FLASH GPIO signals to default
|
||||
*/
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
|
||||
|
||||
/*
|
||||
* Setup EEPROM write protection
|
||||
*/
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
|
||||
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP);
|
||||
|
||||
/*
|
||||
* Enable interrupts in exar duart mcr[3]
|
||||
*/
|
||||
*duart0_mcr = 0x08;
|
||||
*duart1_mcr = 0x08;
|
||||
out_8(duart0_mcr, 0x08);
|
||||
out_8(duart1_mcr, 0x08);
|
||||
|
||||
/*
|
||||
* Init lcd interface and display logo
|
||||
@ -240,17 +253,23 @@ int misc_init_r (void)
|
||||
/*
|
||||
* Set invert bit in small lcd controller
|
||||
*/
|
||||
*(unsigned char *)(CFG_LCD_SMALL_REG + 2) |= 0x01;
|
||||
out_8((unsigned char *)(CFG_LCD_SMALL_REG + 2),
|
||||
in_8((unsigned char *)(CFG_LCD_SMALL_REG + 2)) | 0x01);
|
||||
|
||||
/*
|
||||
* Set default contrast voltage on epson vga controller
|
||||
*/
|
||||
*lcd_contrast = 0x4646;
|
||||
out_be16(lcd_contrast, 0x4646);
|
||||
|
||||
/*
|
||||
* Enable backlight
|
||||
*/
|
||||
*lcd_backlight = 0xffff;
|
||||
out_be16(lcd_backlight, 0xffff);
|
||||
|
||||
/*
|
||||
* Enable external I2C bus
|
||||
*/
|
||||
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_IIC_ON);
|
||||
|
||||
return (0);
|
||||
}
|
||||
@ -281,11 +300,6 @@ int checkboard (void)
|
||||
|
||||
putc ('\n');
|
||||
|
||||
/*
|
||||
* Disable sleep mode in LXT971
|
||||
*/
|
||||
lxt971_no_sleep();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -334,3 +348,86 @@ void ide_set_reset(int on)
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_IDE_RESET */
|
||||
|
||||
#if defined(CONFIG_RESET_PHY_R)
|
||||
void reset_phy(void)
|
||||
{
|
||||
#ifdef CONFIG_LXT971_NO_SLEEP
|
||||
|
||||
/*
|
||||
* Disable sleep mode in LXT971
|
||||
*/
|
||||
lxt971_no_sleep();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CFG_EEPROM_WREN)
|
||||
/* Input: <dev_addr> I2C address of EEPROM device to enable.
|
||||
* <state> -1: deliver current state
|
||||
* 0: disable write
|
||||
* 1: enable write
|
||||
* Returns: -1: wrong device address
|
||||
* 0: dis-/en- able done
|
||||
* 0/1: current state if <state> was -1.
|
||||
*/
|
||||
int eeprom_write_enable (unsigned dev_addr, int state)
|
||||
{
|
||||
if (CFG_I2C_EEPROM_ADDR != dev_addr) {
|
||||
return -1;
|
||||
} else {
|
||||
switch (state) {
|
||||
case 1:
|
||||
/* Enable write access, clear bit GPIO0. */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
|
||||
state = 0;
|
||||
break;
|
||||
case 0:
|
||||
/* Disable write access, set bit GPIO0. */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
|
||||
state = 0;
|
||||
break;
|
||||
default:
|
||||
/* Read current status back. */
|
||||
state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
|
||||
break;
|
||||
}
|
||||
}
|
||||
return state;
|
||||
}
|
||||
|
||||
int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
int query = argc == 1;
|
||||
int state = 0;
|
||||
|
||||
if (query) {
|
||||
/* Query write access state. */
|
||||
state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
|
||||
if (state < 0) {
|
||||
puts ("Query of write access state failed.\n");
|
||||
} else {
|
||||
printf ("Write access for device 0x%0x is %sabled.\n",
|
||||
CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
|
||||
state = 0;
|
||||
}
|
||||
} else {
|
||||
if ('0' == argv[1][0]) {
|
||||
/* Disable write access. */
|
||||
state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
|
||||
} else {
|
||||
/* Enable write access. */
|
||||
state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
|
||||
}
|
||||
if (state < 0) {
|
||||
puts ("Setup of write access state failed.\n");
|
||||
}
|
||||
}
|
||||
|
||||
return state;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
|
||||
"eepwren - Enable / disable / query EEPROM write access\n",
|
||||
NULL);
|
||||
#endif /* #if defined(CFG_EEPROM_WREN) */
|
||||
|
||||
@ -52,9 +52,13 @@
|
||||
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#undef CONFIG_HAS_ETH1
|
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 0 /* PHY address */
|
||||
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
|
||||
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
|
||||
|
||||
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
|
||||
|
||||
@ -204,8 +208,6 @@
|
||||
#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
|
||||
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
|
||||
|
||||
#define CONFIG_ATAPI 1 /* ATAPI for Travelstar */
|
||||
|
||||
#define CFG_ATA_BASE_ADDR 0xF0100000
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||
#define CFG_ATA_IDE1_OFFSET 0x0010
|
||||
@ -244,11 +246,6 @@
|
||||
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
|
||||
#if 0 /* test-only */
|
||||
#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
|
||||
#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
@ -281,19 +278,12 @@
|
||||
* I2C EEPROM (CAT24WC16) for environment
|
||||
*/
|
||||
#define CONFIG_HARD_I2C /* I2c with hardware support */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
|
||||
#if 0 /* test-only */
|
||||
/* CAT24WC08/16... */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
|
||||
/* mask of address bits that overflow into the "EEPROM chip address" */
|
||||
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
|
||||
/* 16 byte page write mode using*/
|
||||
/* last 4 bits of the address */
|
||||
#else
|
||||
#define CFG_EEPROM_WREN 1
|
||||
|
||||
/* CAT24WC32/64... */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
|
||||
/* mask of address bits that overflow into the "EEPROM chip address" */
|
||||
@ -301,7 +291,6 @@
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
|
||||
/* 32 byte page write mode using*/
|
||||
/* last 5 bits of the address */
|
||||
#endif
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE
|
||||
|
||||
@ -400,18 +389,20 @@
|
||||
* GPIO0[28-29] - UART1 data signal input/output
|
||||
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO
|
||||
*/
|
||||
#define CFG_GPIO0_OSRH 0x40000550
|
||||
#define CFG_GPIO0_OSRH 0x00000550
|
||||
#define CFG_GPIO0_OSRL 0x00000110
|
||||
#define CFG_GPIO0_ISR1H 0x00000000
|
||||
#define CFG_GPIO0_ISR1L 0x15555440
|
||||
#define CFG_GPIO0_TSRH 0x00000000
|
||||
#define CFG_GPIO0_TSRL 0x00000000
|
||||
#define CFG_GPIO0_TCR 0xF7FE0017
|
||||
#define CFG_GPIO0_TCR 0x777E0017
|
||||
|
||||
#define CFG_DUART_RST (0x80000000 >> 14)
|
||||
#define CFG_LCD_ENDIAN (0x80000000 >> 7)
|
||||
#define CFG_IIC_ON (0x80000000 >> 8)
|
||||
#define CFG_LCD0_RST (0x80000000 >> 30)
|
||||
#define CFG_LCD1_RST (0x80000000 >> 31)
|
||||
#define CFG_EEPROM_WP (0x80000000 >> 0)
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
|
||||
Loading…
Reference in New Issue
Block a user