From b56b9a0884afab53f7c93cd3c90648437ca7e35e Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Tue, 18 Feb 2014 07:32:01 -0500 Subject: [PATCH] ARM: AM43xx: Change DDR3 Reset Value The bit DDR3_RST_DEF_VAL inside CTRL_DDR_IO represents the default value of the ddr reset value for DDR3 before the EMIF takes over. We must have this bit set high so that on exit from DeepSleep0 within the kernel the reset line has the proper value. Signed-off-by: Dave Gerlach --- arch/arm/cpu/armv7/am33xx/emif4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index d28fceb75c..3e39752380 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -113,7 +113,7 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl); while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0) ; - writel(0x0, &ddrctrl->ddrioctrl); + writel(0x80000000, &ddrctrl->ddrioctrl); config_io_ctrl(ioregs);