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mips: add KSEG1 wrapper for change_k0_cca

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change_k0_cca() is called multiple times. Move the code for
changing to KSEG1 to a macro to avoid code duplication.

Also fix missing change to KSEG1 when changing to CONF_CM_CACHABLE_COW.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Daniel Schwierzeck 2020-07-12 00:45:55 +02:00
parent 54e7fbd5ad
commit b55e07e565
1 changed files with 18 additions and 14 deletions
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32
arch/mips/lib/cache_init.S
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@ -79,6 +79,21 @@
.set pop
.endm
/*
* The changing of Kernel mode cacheability must be done from KSEG1.
* If the code is executing from KSEG0, jump to KSEG1 during the execution
* of change_k0_cca. change_k0_cca itself clears all hazards when returning.
*/
.macro change_k0_cca_kseg1 mode
PTR_LA t0, change_k0_cca
li t1, CPHYSADDR(~0)
and t0, t0, t1
PTR_LI t1, CKSEG1
or t0, t0, t1
li a0, \mode
jalr t0
.endm
/*
* mips_cache_reset - low level initialisation of the primary caches
*
@ -317,18 +332,9 @@ l1_init:
sync
/*
* Enable use of the I-cache by setting Config.K0. The code for this
* must be executed from KSEG1. Jump from KSEG0 to KSEG1 to do this.
* Jump back to KSEG0 after caches are enabled and insert an
* instruction hazard barrier.
* Enable use of the I-cache by setting Config.K0.
*/
PTR_LA t0, change_k0_cca
li t1, CPHYSADDR(~0)
and t0, t0, t1
PTR_LI t1, CKSEG1
or t0, t0, t1
li a0, CONF_CM_CACHABLE_NONCOHERENT
jalr.hb t0
change_k0_cca_kseg1 CONF_CM_CACHABLE_NONCOHERENT
/*
* then initialize D-cache.
@ -388,9 +394,7 @@ l2_unbypass:
beqz t0, 2f
/* Change Config.K0 to a coherent CCA */
PTR_LA t0, change_k0_cca
li a0, CONF_CM_CACHABLE_COW
jalr t0
change_k0_cca_kseg1 CONF_CM_CACHABLE_COW
/*
* Join the coherent domain such that the caches of this core are kept