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caam: enable support for iMX7ULP

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Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Franck LENORMAND 2021-03-25 17:30:23 +08:00 committed by Stefano Babic
parent 68a905d1ff
commit b543800241
5 changed files with 21 additions and 5 deletions
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3
arch/arm/Kconfig
View File

@ -875,6 +875,9 @@ config ARCH_MX31
config ARCH_MX7ULP
bool "NXP MX7ULP"
select CPU_V7A
select SYS_FSL_HAS_SEC if IMX_HAB
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select ROM_UNIFIED_SECTIONS
imply MXC_GPIO
imply SYS_THUMB_BUILD

12
arch/arm/include/asm/arch-mx7ulp/imx-regs.h
View File

@ -16,6 +16,8 @@
#define CAAM_SEC_SRAM_SIZE (SZ_32K)
#define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1)
#define CAAM_ARB_BASE_ADDR CAAM_SEC_SRAM_BASE
#define OCRAM_0_BASE (0x2F000000)
#define OCRAM_0_SIZE (SZ_128K)
#define OCRAM_0_END (OCRAM_0_BASE + OCRAM_0_SIZE - 1)
@ -224,6 +226,16 @@
#define IOMUXC_DDR_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC_DDR_AIPS3_SLOT)))
#define MMDC0_PCC_REG (PCC3_RBASE + (4 * MMDC0_PCC3_SLOT))
#define CAAM_IPS_BASE_ADDR (AIPS2_BASE + 0x240000) /* 40240000 */
#define CONFIG_SYS_FSL_SEC_OFFSET 0
#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32)))
#define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33)))
#define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34)))

1
arch/arm/mach-imx/mx7ulp/Kconfig
View File

@ -9,6 +9,7 @@ config LDO_ENABLED_MODE
Select this option to enable the PMC1 LDO.
config MX7ULP
select HAS_CAAM
bool
choice

2
drivers/crypto/fsl/jobdesc.c
View File

@ -15,7 +15,7 @@
#include "rsa_caam.h"
#include <asm/cache.h>
#if defined(CONFIG_MX6) || defined(CONFIG_MX7)
#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
/*!
* Secure memory run command
*

8
include/fsl_sec.h
View File

@ -195,7 +195,7 @@ typedef struct ccsr_sec {
struct jr_regs {
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
!(defined(CONFIG_MX6) || defined(CONFIG_MX7))
!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP))
u32 irba_l;
u32 irba_h;
#else
@ -209,7 +209,7 @@ struct jr_regs {
u32 rsvd3;
u32 irja;
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
!(defined(CONFIG_MX6) || defined(CONFIG_MX7))
!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP))
u32 orba_l;
u32 orba_h;
#else
@ -242,7 +242,7 @@ struct jr_regs {
*/
struct sg_entry {
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
!(defined(CONFIG_MX6) || defined(CONFIG_MX7))
!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP))
uint32_t addr_lo; /* Memory Address - lo */
uint32_t addr_hi; /* Memory Address of start of buffer - hi */
#else
@ -263,7 +263,7 @@ struct sg_entry {
#define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */
#if defined(CONFIG_MX6) || defined(CONFIG_MX7)
#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
/* Job Ring Base Address */
#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
/* Secure Memory Offset varies accross versions */