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video: dw-mipi-dsi: driver-specific configuration of phy timings
The timing values for dw-dsi are often dependent on the used display and according to Philippe Cornu will most likely also depend on the used phy technology in the soc-specific implementation. To solve this and allow specific implementations to define them as needed add a new get_timing callback to phy_ops and call this from the dphy_timing function to retrieve the necessary values for the specific mode. This is based on the Linux commit [1] and adapted to the U-Boot driver. [1] 25ed8aeb9c39 ("drm/bridge/synopsys: dsi: driver-specific configuration of phy timings") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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@ -645,8 +645,13 @@ static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
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static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
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static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
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{
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{
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const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
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struct mipi_dsi_phy_timing timing = {0x40, 0x40, 0x40, 0x40};
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u32 hw_version;
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u32 hw_version;
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if (phy_ops->get_timing)
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phy_ops->get_timing(dsi->device, dsi->lane_mbps, &timing);
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/*
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/*
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* TODO dw drv improvements
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* TODO dw drv improvements
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* data & clock lane timers should be computed according to panel
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* data & clock lane timers should be computed according to panel
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@ -658,16 +663,16 @@ static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
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hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
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hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
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if (hw_version >= HWVER_131) {
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if (hw_version >= HWVER_131) {
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dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(0x40) |
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dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
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PHY_LP2HS_TIME_V131(0x40));
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PHY_LP2HS_TIME_V131(timing.data_lp2hs));
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dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
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dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
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} else {
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} else {
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dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) |
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dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(timing.data_hs2lp) |
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PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
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PHY_LP2HS_TIME(timing.data_lp2hs) | MAX_RD_TIME(10000));
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}
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}
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dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
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dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(timing.clk_hs2lp)
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| PHY_CLKLP2HS_TIME(0x40));
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| PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
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}
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}
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static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
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static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
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@ -96,6 +96,20 @@ struct mipi_dsi_host_ops {
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const struct mipi_dsi_msg *msg);
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const struct mipi_dsi_msg *msg);
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};
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};
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/**
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* struct mipi_dsi_phy_timing - DSI host phy timings
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* @data_hs2lp: High Speed to Low Speed Data Transition Time
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* @data_lp2hs: Low Speed to High Speed Data Transition Time
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* @clk_hs2lp: High Speed to Low Speed Clock Transition Time
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* @clk_lp2hs: Low Speed to High Speed Clock Transition Time
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*/
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struct mipi_dsi_phy_timing {
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u16 data_hs2lp;
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u16 data_lp2hs;
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u16 clk_hs2lp;
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u16 clk_lp2hs;
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};
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/**
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/**
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* struct mipi_dsi_phy_ops - DSI host physical operations
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* struct mipi_dsi_phy_ops - DSI host physical operations
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* @init: initialized host physical part
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* @init: initialized host physical part
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@ -107,6 +121,8 @@ struct mipi_dsi_phy_ops {
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int (*get_lane_mbps)(void *priv_data, struct display_timing *timings,
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int (*get_lane_mbps)(void *priv_data, struct display_timing *timings,
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u32 lanes, u32 format, unsigned int *lane_mbps);
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u32 lanes, u32 format, unsigned int *lane_mbps);
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void (*post_set_mode)(void *priv_data, unsigned long mode_flags);
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void (*post_set_mode)(void *priv_data, unsigned long mode_flags);
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int (*get_timing)(void *priv_data, unsigned int lane_mbps,
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struct mipi_dsi_phy_timing *timing);
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};
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};
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/**
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/**
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