brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

mx6: Set shared override bit in PL310 AUX_CTRL register

Browse Source 
Having bit 22 cleared in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

This was inspired by a patch from Catalin Marinas [1] and also from recent
discussions in the linux-arm-kernel list [2] where Russell King and Rob Herring
suggested that bootloaders should initialize the cache.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/031810.html
[2] https://lkml.org/lkml/2015/2/20/199

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Fabio Estevam 2015-03-11 17:12:12 -03:00 committed by Stefano Babic
parent 9927d60f4a
commit b4ed9f86df
2 changed files with 10 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm/cpu/armv7/mx6/soc.c
View File

@ -523,6 +523,14 @@ void v7_outer_cache_enable(void)
struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
unsigned int val;
/*
* Set bit 22 in the auxiliary control register. If this bit
* is cleared, PL310 treats Normal Shared Non-cacheable
* accesses as Cacheable no-allocate.
*/
setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
#if defined CONFIG_MX6SL
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
val = readl(&iomux->gpr[11]);

2
arch/arm/include/asm/pl310.h
View File

@ -16,6 +16,8 @@
#define L2X0_STNDBY_MODE_EN (1 << 0)
#define L2X0_CTRL_EN 1
#define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22)
struct pl310_regs {
u32 pl310_cache_id;
u32 pl310_cache_type;