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Fix bug in [id]cache_status commands for MPC85xx processors;
should look at LSB of L1CSRn registers to determine if L1 cache is enabled, not the MSB. Patch by Murray Jensen, 19 Jul 2005
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@ -2,6 +2,11 @@
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Changes since U-Boot 1.1.4:
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Changes since U-Boot 1.1.4:
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======================================================================
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======================================================================
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* Fix bug in [id]cache_status commands for MPC85xx processors;
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should look at LSB of L1CSRn registers to determine if L1 cache is
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enabled, not the MSB.
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Patch by Murray Jensen, 19 Jul 2005
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* Fix array overflow with fw_setenv on uninitialised environment
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* Fix array overflow with fw_setenv on uninitialised environment
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Patch by Murray Jensen, 15 Jul 2005
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Patch by Murray Jensen, 15 Jul 2005
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@ -715,7 +715,7 @@ icache_disable:
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.globl icache_status
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.globl icache_status
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icache_status:
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icache_status:
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mfspr r3,L1CSR1
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mfspr r3,L1CSR1
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srwi r3, r3, 31 /* >>31 => select bit 0 */
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andi. r3,r3,1
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blr
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blr
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.globl dcache_enable
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.globl dcache_enable
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@ -748,7 +748,7 @@ dcache_disable:
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.globl dcache_status
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.globl dcache_status
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dcache_status:
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dcache_status:
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mfspr r3,L1CSR0
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mfspr r3,L1CSR0
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srwi r3, r3, 31 /* >>31 => select bit 0 */
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andi. r3,r3,1
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blr
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blr
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.globl get_pir
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.globl get_pir
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