From b32e9a757837d75ffc1b2252df96834d82a825ff Mon Sep 17 00:00:00 2001
From: Alex Marginean <alexandru.marginean@nxp.com>
Date: Wed, 3 Jul 2019 12:11:43 +0300
Subject: [PATCH] arm: dts: ls1028a updates for network interfaces

Defines LS1028A RDB SGMII port, QDS RGMII port.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
 arch/arm/dts/fsl-ls1028a-qds.dts | 13 +++++++++++++
 arch/arm/dts/fsl-ls1028a-rdb.dts | 13 +++++++++++++
 arch/arm/dts/fsl-ls1028a.dtsi    | 24 ++++++++++++++++++++++++
 3 files changed, 50 insertions(+)

diff --git a/arch/arm/dts/fsl-ls1028a-qds.dts b/arch/arm/dts/fsl-ls1028a-qds.dts
index 46a0419d77..94d0aa0f95 100644
--- a/arch/arm/dts/fsl-ls1028a-qds.dts
+++ b/arch/arm/dts/fsl-ls1028a-qds.dts
@@ -86,3 +86,16 @@
 &usb2 {
 	status = "okay";
 };
+
+&enetc1 {
+	status = "okay";
+	phy-mode = "rgmii";
+	phy-handle = <&qds_phy0>;
+};
+
+&mdio0 {
+	status = "okay";
+	qds_phy0: phy@5 {
+		reg = <5>;
+	};
+};
diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts
index 932cfa2275..052538937b 100644
--- a/arch/arm/dts/fsl-ls1028a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1028a-rdb.dts
@@ -86,3 +86,16 @@
 &usb2 {
 	status = "okay";
 };
+
+&enetc0 {
+	status = "okay";
+	phy-mode = "sgmii";
+	phy-handle = <&rdb_phy0>;
+};
+
+&mdio0 {
+	status = "okay";
+	rdb_phy0: phy@2 {
+		reg = <2>;
+	};
+};
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 49074112c4..43a154e8e7 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -117,6 +117,30 @@
 		#size-cells = <2>;
 		device_type = "pci";
 		ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>;
+		enetc0: pci@0,0 {
+			reg = <0x000000 0 0 0 0>;
+			status = "disabled";
+		};
+		enetc1: pci@0,1 {
+			reg = <0x000100 0 0 0 0>;
+			status = "disabled";
+		};
+		enetc2: pci@0,2 {
+			reg = <0x000200 0 0 0 0>;
+			status = "okay";
+			phy-mode = "internal";
+		};
+		mdio0: pci@0,3 {
+			#address-cells=<0>;
+			#size-cells=<1>;
+			reg = <0x000300 0 0 0 0>;
+			status = "disabled";
+		};
+		enetc6: pci@0,6 {
+			reg = <0x000600 0 0 0 0>;
+			status = "okay";
+			phy-mode = "internal";
+		};
 	};
 
 	i2c0: i2c@2000000 {