x86: Add an option to control the position of U-Boot
The existing work-around for positioning U-Boot in the ROM when it actually runs from RAM still exists and there is not obvious way to change this. Add a proper Kconfig option to handle this case. This also adds a new bool property to indicate whether CONFIG_SYS_TEXT_BASE exists. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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9
Kconfig
9
Kconfig
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@ -545,9 +545,14 @@ config SYS_EXTRA_OPTIONS
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configuration to Kconfig. Since this option will be removed sometime,
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configuration to Kconfig. Since this option will be removed sometime,
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new boards should not use this option.
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new boards should not use this option.
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config SYS_TEXT_BASE
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config HAVE_SYS_TEXT_BASE
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bool
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depends on !NIOS2 && !XTENSA
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depends on !NIOS2 && !XTENSA
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depends on !EFI_APP
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depends on !EFI_APP
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default y
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config SYS_TEXT_BASE
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depends on HAVE_SYS_TEXT_BASE
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default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3
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default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3
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default 0x4a000000 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S
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default 0x4a000000 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S
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default 0x2a000000 if ARCH_SUNXI && MACH_SUN9I
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default 0x2a000000 if ARCH_SUNXI && MACH_SUN9I
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@ -556,8 +561,6 @@ config SYS_TEXT_BASE
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help
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help
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The address in memory that U-Boot will be running from, initially.
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The address in memory that U-Boot will be running from, initially.
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config SYS_CLK_FREQ
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config SYS_CLK_FREQ
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depends on ARC || ARCH_SUNXI || MPC83xx
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depends on ARC || ARCH_SUNXI || MPC83xx
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int "CPU clock frequency"
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int "CPU clock frequency"
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@ -899,4 +899,9 @@ config CACHE_QOS_SIZE_PER_BIT
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depends on INTEL_CAR_CQOS
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depends on INTEL_CAR_CQOS
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default 0x20000 # 128 KB
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default 0x20000 # 128 KB
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config X86_OFFSET_U_BOOT
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hex "Offset of U-Boot in ROM image"
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depends on HAVE_SYS_TEXT_BASE
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default SYS_TEXT_BASE
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endmenu
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endmenu
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@ -50,7 +50,7 @@
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u-boot-spl-dtb {
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u-boot-spl-dtb {
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};
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};
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u-boot {
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u-boot {
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offset = <CONFIG_SYS_TEXT_BASE>;
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offset = <CONFIG_X86_OFFSET_U_BOOT>;
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};
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};
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#elif defined(CONFIG_SPL)
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#elif defined(CONFIG_SPL)
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u-boot-spl-with-ucode-ptr {
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u-boot-spl-with-ucode-ptr {
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@ -60,23 +60,11 @@
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type = "u-boot-dtb-with-ucode";
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type = "u-boot-dtb-with-ucode";
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};
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};
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u-boot {
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u-boot {
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/*
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offset = <CONFIG_X86_OFFSET_U_BOOT>;
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* TODO(sjg@chromium.org):
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* Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But
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* for boards with textbase in SDRAM we cannot do this. Just use
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* an assumed-valid value (1MB before the end of flash) here so
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* that we can actually build an image for coreboot, etc.
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* We need a better solution, perhaps a separate Kconfig.
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*/
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#if CONFIG_SYS_TEXT_BASE == 0x1110000
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offset = <0xfff00000>;
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#else
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offset = <CONFIG_SYS_TEXT_BASE>;
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#endif
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};
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};
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#else
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#else
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u-boot-with-ucode-ptr {
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u-boot-with-ucode-ptr {
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offset = <CONFIG_SYS_TEXT_BASE>;
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offset = <CONFIG_X86_OFFSET_U_BOOT>;
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};
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};
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#endif
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#endif
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#ifdef CONFIG_HAVE_MICROCODE
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#ifdef CONFIG_HAVE_MICROCODE
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@ -16,6 +16,7 @@ CONFIG_HAVE_REFCODE=y
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CONFIG_SMP=y
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CONFIG_SMP=y
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CONFIG_HAVE_VGA_BIOS=y
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CONFIG_HAVE_VGA_BIOS=y
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CONFIG_SPL_TEXT_BASE=0xffe70000
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CONFIG_SPL_TEXT_BASE=0xffe70000
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CONFIG_X86_OFFSET_U_BOOT=0xfff00000
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CONFIG_BOOTSTAGE=y
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CONFIG_BOOTSTAGE=y
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CONFIG_BOOTSTAGE_REPORT=y
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CONFIG_BOOTSTAGE_REPORT=y
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CONFIG_SHOW_BOOT_PROGRESS=y
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CONFIG_SHOW_BOOT_PROGRESS=y
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@ -13,6 +13,7 @@ CONFIG_SMP=y
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CONFIG_GENERATE_PIRQ_TABLE=y
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CONFIG_GENERATE_PIRQ_TABLE=y
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CONFIG_GENERATE_MP_TABLE=y
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CONFIG_GENERATE_MP_TABLE=y
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CONFIG_GENERATE_ACPI_TABLE=y
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CONFIG_GENERATE_ACPI_TABLE=y
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CONFIG_X86_OFFSET_U_BOOT=0xfff00000
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CONFIG_SPL_TEXT_BASE=0xfffd0000
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CONFIG_SPL_TEXT_BASE=0xfffd0000
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_BUILD_ROM=y
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CONFIG_BUILD_ROM=y
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