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mpc83xx: cosmetic: MVBLM7.h checkpatch compliance

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Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Joe Hershberger 2011-10-11 23:57:20 -05:00 committed by Kim Phillips
parent 5afe9722b0
commit b2773a5e1c
1 changed files with 76 additions and 40 deletions
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116
include/configs/MVBLM7.h
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@ -107,13 +107,19 @@
#define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 256 #define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V) #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\ | OR_UPM_XAM \
OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \ | OR_GPCM_CSNT \
OR_GPCM_EAD) | OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
| OR_GPCM_TRLX \
| OR_GPCM_EHTR \
| OR_GPCM_EAD)
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT)) #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \
| (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
/* /*
* U-Boot memory configuration * U-Boot memory configuration
@ -122,10 +128,11 @@
#undef CONFIG_SYS_RAMBOOT #undef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
@ -157,7 +164,7 @@
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \ #define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_CONSOLE ttyS0 #define CONFIG_CONSOLE ttyS0
#define CONFIG_BAUDRATE 115200 #define CONFIG_BAUDRATE 115200
@ -177,7 +184,8 @@
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
#define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) #define CONFIG_SYS_PCI1_MMIO_BASE \
(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
@ -204,16 +212,16 @@
#define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_FEC1_PHY_NORXERR #define CONFIG_FEC1_PHY_NORXERR
#define CONFIG_SYS_TSEC1_OFFSET 0x24000 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define TSEC1_PHY_ADDR 0x10 #define TSEC1_PHY_ADDR 0x10
#define TSEC1_PHYIDX 0 #define TSEC1_PHYIDX 0
#define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED) #define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
#define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME "TSEC1" #define CONFIG_TSEC2_NAME "TSEC1"
#define CONFIG_FEC2_PHY_NORXERR #define CONFIG_FEC2_PHY_NORXERR
#define CONFIG_SYS_TSEC2_OFFSET 0x25000 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
#define TSEC2_PHY_ADDR 0x11 #define TSEC2_PHY_ADDR 0x11
#define TSEC2_PHYIDX 0 #define TSEC2_PHYIDX 0
#define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED) #define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
@ -250,7 +258,7 @@
#define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x2000
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#define CONFIG_LOADS_ECHO #define CONFIG_LOADS_ECHO
#define CONFIG_SYS_LOADS_BAUD_CHANGE #define CONFIG_SYS_LOADS_BAUD_CHANGE
@ -280,7 +288,7 @@
*/ */
#define CONFIG_SYS_LONGHELP #define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING #define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
@ -292,7 +300,8 @@
#define CONFIG_SYS_PROMPT "mvBL-M7> " #define CONFIG_SYS_PROMPT "mvBL-M7> "
#define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ 1000
@ -302,7 +311,8 @@
* have to be in the first 256 MB of memory, since this is * have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization. * the maximum mapped by the Linux kernel during initialization.
*/ */
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_HRCW_LOW 0x0 #define CONFIG_SYS_HRCW_LOW 0x0
#define CONFIG_SYS_HRCW_HIGH 0x0 #define CONFIG_SYS_HRCW_HIGH 0x0
@ -311,7 +321,7 @@
* System performance * System performance
*/ */
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
@ -333,15 +343,30 @@
#define CONFIG_HIGH_BATS 1 #define CONFIG_HIGH_BATS 1
/* DDR */ /* DDR */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | BATL_PP_10 \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
/* PCI */ /* PCI */
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | BATL_PP_10 \
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\ | BATL_MEMCOHERENCE)
BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
| BATL_PP_10 \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
/* no PCI2 */ /* no PCI2 */
#define CONFIG_SYS_IBAT3L 0 #define CONFIG_SYS_IBAT3L 0
@ -350,14 +375,25 @@
#define CONFIG_SYS_IBAT4U 0 #define CONFIG_SYS_IBAT4U 0
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
BATL_GUARDEDSTORAGE) | BATL_PP_10 \
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */ /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ #define CONFIG_SYS_IBAT6L (0xF0000000 \
| BATL_PP_10 \
| BATL_MEMCOHERENCE \
| \
BATL_GUARDEDSTORAGE) BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT6U (0xF0000000 \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT7L 0 #define CONFIG_SYS_IBAT7L 0
#define CONFIG_SYS_IBAT7U 0 #define CONFIG_SYS_IBAT7U 0
@ -392,8 +428,8 @@
#define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_RESET_TO_RETRY 1000 #define CONFIG_RESET_TO_RETRY 1000
#define MV_CI mvBL-M7 #define MV_CI "mvBL-M7"
#define MV_VCI mvBL-M7 #define MV_VCI "mvBL-M7"
#define MV_FPGA_DATA 0xfff40000 #define MV_FPGA_DATA 0xfff40000
#define MV_FPGA_SIZE 0 #define MV_FPGA_SIZE 0
#define MV_KERNEL_ADDR 0xff810000 #define MV_KERNEL_ADDR 0xff810000
@ -409,15 +445,15 @@
#define MV_DTB_ADDR_RAM 0x00600000 #define MV_DTB_ADDR_RAM 0x00600000
#define MV_INITRD_ADDR_RAM 0x01000000 #define MV_INITRD_ADDR_RAM 0x01000000
#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \ #define CONFIG_BOOTCOMMAND "if imi ${script_addr}; " \
then source ${script_addr}; \ "then source ${script_addr}; " \
else source ${script_addr2}; \ "else source ${script_addr2}; " \
fi;" "fi;"
#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" #define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
#define CONFIG_EXTRA_ENV_SETTINGS \ #define CONFIG_EXTRA_ENV_SETTINGS \
"console_nr=0\0" \ "console_nr=0\0" \
"baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" \ "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" \
"stdin=serial\0" \ "stdin=serial\0" \
"stdout=serial\0" \ "stdout=serial\0" \
"stderr=serial\0" \ "stderr=serial\0" \
@ -435,8 +471,8 @@
"mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \ "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
"dtb_name=" MK_STR(MV_DTB_NAME) "\0" \ "dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
"mv_version=" U_BOOT_VERSION "\0" \ "mv_version=" U_BOOT_VERSION "\0" \
"dhcp_client_id=" MK_STR(MV_CI) "\0" \ "dhcp_client_id=" MV_CI "\0" \
"dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \ "dhcp_vendor-class-identifier=" MV_VCI "\0" \
"netretry=no\0" \ "netretry=no\0" \
"use_static_ipaddr=no\0" \ "use_static_ipaddr=no\0" \
"static_ipaddr=192.168.90.10\0" \ "static_ipaddr=192.168.90.10\0" \