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https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
mpc83xx: cosmetic: MVBLM7.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Joe Hershberger
Kim Phillips
parent
5afe9722b0
commit
b2773a5e1c
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@ -107,13 +107,19 @@
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
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#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
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OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\
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OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \
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OR_GPCM_EAD)
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
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#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
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| OR_UPM_XAM \
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| OR_GPCM_CSNT \
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| OR_GPCM_ACS_DIV2 \
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| OR_GPCM_XACS \
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| OR_GPCM_SCY_15 \
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| OR_GPCM_TRLX \
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| OR_GPCM_EHTR \
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| OR_GPCM_EAD)
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
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#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \
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| (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
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/*
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* U-Boot memory configuration
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@ -122,10 +128,11 @@
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#undef CONFIG_SYS_RAMBOOT
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
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@ -157,7 +164,7 @@
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONFIG_CONSOLE ttyS0
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#define CONFIG_BAUDRATE 115200
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@ -177,7 +184,8 @@
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#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
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#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
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#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
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#define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
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#define CONFIG_SYS_PCI1_MMIO_BASE \
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(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
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#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
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#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
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#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
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@ -204,16 +212,16 @@
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_FEC1_PHY_NORXERR
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#define CONFIG_SYS_TSEC1_OFFSET 0x24000
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#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
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#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
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#define TSEC1_PHY_ADDR 0x10
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#define TSEC1_PHYIDX 0
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#define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
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#define CONFIG_HAS_ETH1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define CONFIG_FEC2_PHY_NORXERR
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#define CONFIG_SYS_TSEC2_OFFSET 0x25000
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#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
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#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
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#define TSEC2_PHY_ADDR 0x11
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#define TSEC2_PHYIDX 0
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#define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
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@ -250,7 +258,7 @@
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x2000
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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#define CONFIG_LOADS_ECHO
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#define CONFIG_SYS_LOADS_BAUD_CHANGE
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@ -280,7 +288,7 @@
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*/
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
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#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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@ -292,7 +300,8 @@
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#define CONFIG_SYS_PROMPT "mvBL-M7> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_HZ 1000
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@ -302,7 +311,8 @@
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* have to be in the first 256 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
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/* Initial Memory map for Linux*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
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#define CONFIG_SYS_HRCW_LOW 0x0
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#define CONFIG_SYS_HRCW_HIGH 0x0
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@ -311,7 +321,7 @@
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* System performance
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
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#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
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#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
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@ -333,15 +343,30 @@
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#define CONFIG_HIGH_BATS 1
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/* DDR */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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/* PCI */
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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/* no PCI2 */
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#define CONFIG_SYS_IBAT3L 0
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@ -350,14 +375,25 @@
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#define CONFIG_SYS_IBAT4U 0
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/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
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#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
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#define CONFIG_SYS_IBAT6L (0xF0000000 \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE \
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| \
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT6U (0xF0000000 \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_IBAT7L 0
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#define CONFIG_SYS_IBAT7U 0
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@ -392,8 +428,8 @@
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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#define CONFIG_RESET_TO_RETRY 1000
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#define MV_CI mvBL-M7
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#define MV_VCI mvBL-M7
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#define MV_CI "mvBL-M7"
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#define MV_VCI "mvBL-M7"
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#define MV_FPGA_DATA 0xfff40000
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#define MV_FPGA_SIZE 0
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#define MV_KERNEL_ADDR 0xff810000
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@ -409,15 +445,15 @@
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#define MV_DTB_ADDR_RAM 0x00600000
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#define MV_INITRD_ADDR_RAM 0x01000000
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#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \
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then source ${script_addr}; \
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else source ${script_addr2}; \
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fi;"
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#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; " \
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"then source ${script_addr}; " \
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"else source ${script_addr2}; " \
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"fi;"
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#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"console_nr=0\0" \
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"baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" \
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"baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" \
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"stdin=serial\0" \
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"stdout=serial\0" \
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"stderr=serial\0" \
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@ -435,8 +471,8 @@
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"mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
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"dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
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"mv_version=" U_BOOT_VERSION "\0" \
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"dhcp_client_id=" MK_STR(MV_CI) "\0" \
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"dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
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"dhcp_client_id=" MV_CI "\0" \
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"dhcp_vendor-class-identifier=" MV_VCI "\0" \
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"netretry=no\0" \
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"use_static_ipaddr=no\0" \
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"static_ipaddr=192.168.90.10\0" \
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