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powerpc/85xx: update the work-around for P4080 erratum SERDES-9
The documented work-around for P4080 erratum SERDES-9 has been updated. It is now compatible with the work-around for erratum A-4580. This requires adding a few bitfield macros for the BnTTLCRy0 register. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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@ -714,9 +714,13 @@ void fsl_serdes_init(void)
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
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/*
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/*
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* Set BnTTLCRy0[FLT_SEL] = 000011 and set BnTTLCRy0[17] = 1 for
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* Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1
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* each of the SerDes lanes selected as SGMII, XAUI, SRIO, or
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* for each of the SerDes lanes selected as SGMII, XAUI, SRIO,
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* AURORA before the device is initialized.
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* or AURORA before the device is initialized.
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*
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* Note that this part of the SERDES-9 work-around is
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* redundant if the work-around for A-4580 has already been
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* applied via PBI.
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*/
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*/
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switch (lane_prtcl) {
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switch (lane_prtcl) {
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case SGMII_FM1_DTSEC1:
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case SGMII_FM1_DTSEC1:
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@ -733,10 +737,12 @@ void fsl_serdes_init(void)
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case SRIO1:
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case SRIO1:
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case SRIO2:
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case SRIO2:
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case AURORA:
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case AURORA:
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clrsetbits_be32(&srds_regs->lane[idx].ttlcr0,
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out_be32(&srds_regs->lane[idx].ttlcr0,
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SRDS_TTLCR0_FLT_SEL_MASK,
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SRDS_TTLCR0_FLT_SEL_KFR_26 |
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SRDS_TTLCR0_FLT_SEL_750PPM |
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SRDS_TTLCR0_FLT_SEL_KPH_28 |
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SRDS_TTLCR0_PM_DIS);
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SRDS_TTLCR0_FLT_SEL_750PPM |
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SRDS_TTLCR0_FREQOVD_EN);
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break;
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default:
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default:
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break;
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break;
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}
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}
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@ -2637,8 +2637,11 @@ typedef struct serdes_corenet {
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u32 res3;
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u32 res3;
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u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
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u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
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#define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
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#define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
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#define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000
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#define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000
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#define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
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#define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
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#define SRDS_TTLCR0_PM_DIS 0x00004000
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#define SRDS_TTLCR0_PM_DIS 0x00004000
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#define SRDS_TTLCR0_FREQOVD_EN 0x00000001
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u32 res4[7];
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u32 res4[7];
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} lane[24];
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} lane[24];
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u32 res6[384];
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u32 res6[384];
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