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mxs: spl_mem_init: Remove erroneous DDR setting

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On mx23 there is no 'DRAM init complete' in register HW_DRAM_CTL18.

Remove this erroneous setting.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Fabio Estevam 2013-05-03 04:37:11 +00:00 committed by Stefano Babic
parent 8a47c997c5
commit b0d4bf9f0c
1 changed files with 0 additions and 4 deletions
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4
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
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@ -279,10 +279,6 @@ static void mx23_mem_init(void)
setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
/* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */
while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10)))
;
}
#endif