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https://github.com/brain-hackers/u-boot-brain
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board: ls1012a: LS1012A-2G5RDB board support
LS1012A-2G5RDB belongs to LS1012A family with features 2 2.5G SGMII PFE MAC, SATA, USB 2.0/3.0, WiFi DDR, eMMC, QuadSPI, UART. Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
parent
bdc48ec61e
commit
b0ce187b1f
@ -968,6 +968,18 @@ config TARGET_LS1012ARDB
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development platform that supports the QorIQ LS1012A
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development platform that supports the QorIQ LS1012A
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Layerscape Architecture processor.
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Layerscape Architecture processor.
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config TARGET_LS1012A2G5RDB
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bool "Support ls1012a2g5rdb"
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select ARCH_LS1012A
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select ARM64
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select BOARD_LATE_INIT
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imply SCSI
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help
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Support for Freescale LS1012A2G5RDB platform.
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The LS1012A 2G5 Reference design board (RDB) is a high-performance
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development platform that supports the QorIQ LS1012A
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Layerscape Architecture processor.
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config TARGET_LS1012AFRDM
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config TARGET_LS1012AFRDM
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bool "Support ls1012afrdm"
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bool "Support ls1012afrdm"
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select ARCH_LS1012A
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select ARCH_LS1012A
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@ -90,7 +90,7 @@ config PSCI_RESET
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!TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
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!TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
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!TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
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!TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
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!TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
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!TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
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!TARGET_LS1012AQDS && \
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!TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
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!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
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!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
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!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
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!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
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!TARGET_LS2081ARDB && \
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!TARGET_LS2081ARDB && \
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@ -209,6 +209,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
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fsl-ls1046a-rdb.dtb \
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fsl-ls1046a-rdb.dtb \
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fsl-ls1012a-qds.dtb \
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fsl-ls1012a-qds.dtb \
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fsl-ls1012a-rdb.dtb \
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fsl-ls1012a-rdb.dtb \
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fsl-ls1012a-2g5rdb.dtb \
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fsl-ls1012a-frdm.dtb
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fsl-ls1012a-frdm.dtb
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dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
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dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
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43
arch/arm/dts/fsl-ls1012a-2g5rdb.dts
Normal file
43
arch/arm/dts/fsl-ls1012a-2g5rdb.dts
Normal file
@ -0,0 +1,43 @@
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/*
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* NXP ls1012a 2G5RDB board device tree source
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*
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include "fsl-ls1012a.dtsi"
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/ {
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model = "LS1012A 2G5RDB Board";
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aliases {
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spi0 = &qspi;
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};
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chosen {
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stdout-path = &duart0;
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};
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};
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&qspi {
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bus-num = <0>;
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status = "okay";
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qflash0: s25fl128s@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-flash";
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spi-max-frequency = <20000000>;
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reg = <0>;
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};
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};
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&i2c0 {
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status = "okay";
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};
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&duart0 {
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status = "okay";
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};
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@ -15,3 +15,21 @@ config SYS_CONFIG_NAME
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source "board/freescale/common/Kconfig"
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source "board/freescale/common/Kconfig"
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endif
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endif
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if TARGET_LS1012A2G5RDB
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config SYS_BOARD
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default "ls1012ardb"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "fsl-layerscape"
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config SYS_CONFIG_NAME
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default "ls1012a2g5rdb"
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source "board/freescale/common/Kconfig"
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endif
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@ -8,3 +8,10 @@ F: configs/ls1012ardb_qspi_defconfig
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M: Sumit Garg <sumit.garg@nxp.com>
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M: Sumit Garg <sumit.garg@nxp.com>
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S: Maintained
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S: Maintained
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F: configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
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F: configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
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LS1012A2G5RDB BOARD
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M: Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
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S: Maintained
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F: board/freescale/ls1012ardb/
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F: include/configs/ls1012a2g5rdb.h
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F: configs/ls1012a2g5rdb_qspi_defconfig
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@ -52,3 +52,46 @@ U-boot | 1MB | 0x4010_0000
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U-boot Env | 1MB | 0x4020_0000
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U-boot Env | 1MB | 0x4020_0000
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PPA FIT image | 2MB | 0x4050_0000
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PPA FIT image | 2MB | 0x4050_0000
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Linux ITB | ~53MB | 0x40A0_0000
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Linux ITB | ~53MB | 0x40A0_0000
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LS1012A2G5RDB board Overview
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-----------------------
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- SERDES Connections, 3 lanes supporting:
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- SGMII, SGMII 2.5
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- SATA 3.0
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- DDR Controller
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- 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
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-QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
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signals to
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- QSPI NOR flash memory
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- USB 3.0
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- one high-speed USB 2.0/3.0 port.
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- SDIO WiFi, SPI
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- 2 I2C controllers
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- One SATA onboard connectors
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- UART
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- The LS1012A processor consists of two UART controllers,
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out of which only UART1 is used on 2G5RDB.
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- ARM JTAG support
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Major Difference between LS1012ARDB and LS1012A-2G5RDB
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------------------------------------------------------
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1. LS1012A-2G5RDB has Type C USB connector unlike USB Type A/B of LS1012ARDB
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2. LS1012A-2G5RDB has 2 2.5G AQR PHY unlike 2 1G Realtek RTL8211FS PHYs
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of LS1012ARDB
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3. LS1012A-2G5RDB is not having Arduino header
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4. LS1012A-2G5RDB doesn't have PCI slot
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Booting Options
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---------------
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QSPI Flash
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QSPI flash map
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--------------
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Images | Size |QSPI Flash Address
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------------------------------------------
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RCW + PBI | 1MB | 0x4000_0000
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U-boot | 1MB | 0x4010_0000
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U-boot Env | 1MB | 0x4030_0000
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PPA FIT image | 2MB | 0x4040_0000
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PFE firmware | 20K | 0x00a0_0000
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Linux ITB | ~53MB | 0x4100_0000
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@ -28,6 +28,7 @@ DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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int checkboard(void)
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{
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{
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#ifdef CONFIG_TARGET_LS1012ARDB
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u8 in1;
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u8 in1;
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puts("Board: LS1012ARDB ");
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puts("Board: LS1012ARDB ");
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@ -77,7 +78,10 @@ int checkboard(void)
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puts(": bank2\n");
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puts(": bank2\n");
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else
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else
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puts("unknown\n");
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puts("unknown\n");
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#else
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puts("Board: LS1012A2G5RDB ");
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#endif
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return 0;
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return 0;
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}
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}
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@ -150,6 +154,7 @@ int board_init(void)
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return 0;
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return 0;
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}
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}
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#ifdef CONFIG_TARGET_LS1012ARDB
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int esdhc_status_fixup(void *blob, const char *compat)
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int esdhc_status_fixup(void *blob, const char *compat)
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{
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{
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char esdhc1_path[] = "/soc/esdhc@1580000";
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char esdhc1_path[] = "/soc/esdhc@1580000";
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@ -193,7 +198,6 @@ int esdhc_status_fixup(void *blob, const char *compat)
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if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
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if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
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sdhc2_en = true;
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sdhc2_en = true;
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}
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}
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if (sdhc2_en)
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if (sdhc2_en)
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do_fixup_by_path(blob, esdhc1_path, "status", "okay",
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do_fixup_by_path(blob, esdhc1_path, "status", "okay",
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sizeof("okay"), 1);
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sizeof("okay"), 1);
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@ -202,6 +206,7 @@ int esdhc_status_fixup(void *blob, const char *compat)
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sizeof("disabled"), 1);
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sizeof("disabled"), 1);
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return 0;
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return 0;
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}
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}
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#endif
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int ft_board_setup(void *blob, bd_t *bd)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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{
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40
configs/ls1012a2g5rdb_qspi_defconfig
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40
configs/ls1012a2g5rdb_qspi_defconfig
Normal file
@ -0,0 +1,40 @@
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CONFIG_ARM=y
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CONFIG_TARGET_LS1012A2G5RDB=y
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CONFIG_FSL_LS_PPA=y
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CONFIG_QSPI_AHB_INIT=y
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CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb"
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CONFIG_DISTRO_DEFAULTS=y
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# CONFIG_SYS_MALLOC_F is not set
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
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CONFIG_QSPI_BOOT=y
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CONFIG_BOOTDELAY=10
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_CMD_GREPENV=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_CACHE=y
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CONFIG_OF_CONTROL=y
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_DM=y
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# CONFIG_BLK is not set
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CONFIG_DM_MMC=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_NETDEVICES=y
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CONFIG_SYS_NS16550=y
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CONFIG_DM_SPI=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_DWC3=y
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CONFIG_USB_STORAGE=y
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122
include/configs/ls1012a2g5rdb.h
Normal file
122
include/configs/ls1012a2g5rdb.h
Normal file
@ -0,0 +1,122 @@
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/*
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __LS1012A2G5RDB_H__
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#define __LS1012A2G5RDB_H__
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#include "ls1012a_common.h"
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/* PFE Ethernet */
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#ifdef CONFIG_FSL_PFE
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#define EMAC1_PHY_ADDR 0x2
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#define EMAC2_PHY_ADDR 0x1
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#define CONFIG_PHYLIB
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#define CONFIG_PHYLIB_10G
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#define CONFIG_PHY_AQUANTIA
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#endif
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/* DDR */
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL 1
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#define CONFIG_NR_DRAM_BANKS 2
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#define CONFIG_SYS_SDRAM_SIZE 0x40000000
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#define CONFIG_CMD_MEMINFO
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#define CONFIG_CMD_MEMTEST
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#define CONFIG_SYS_MEMTEST_START 0x80000000
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#define CONFIG_SYS_MEMTEST_END 0x9fffffff
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/* MMC */
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#ifdef CONFIG_MMC
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
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#endif
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/* SATA */
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#define CONFIG_LIBATA
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#define CONFIG_SCSI_AHCI
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#define CONFIG_SCSI_AHCI_PLAT
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#define CONFIG_SYS_SATA AHCI_BASE_ADDR
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#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
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#define CONFIG_SYS_SCSI_MAX_LUN 1
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#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
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CONFIG_SYS_SCSI_MAX_LUN)
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#define CONFIG_NET_MULTI
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#define CONFIG_CMD_MEMINFO
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#define CONFIG_CMD_MEMTEST
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#define CONFIG_SYS_MEMTEST_START 0x80000000
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#define CONFIG_SYS_MEMTEST_END 0x9fffffff
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#undef CONFIG_EXTRA_ENV_SETTINGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"verify=no\0" \
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"fdt_high=0xffffffffffffffff\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"fdt_addr=0x00f00000\0" \
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"kernel_addr=0x01000000\0" \
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"kernelheader_addr=0x800000\0" \
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"scriptaddr=0x80000000\0" \
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"scripthdraddr=0x80080000\0" \
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"fdtheader_addr_r=0x80100000\0" \
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"kernelheader_addr_r=0x80200000\0" \
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"kernel_addr_r=0x81000000\0" \
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"fdt_addr_r=0x90000000\0" \
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"load_addr=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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"kernelheader_size=0x40000\0" \
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"console=ttyS0,115200\0" \
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BOOTENV \
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"boot_scripts=ls1012ardb_boot.scr\0" \
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"boot_script_hdr=hdr_ls1012ardb_bs.out\0" \
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"scan_dev_for_boot_part=" \
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"part list ${devtype} ${devnum} devplist; " \
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"env exists devplist || setenv devplist 1; " \
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"for distro_bootpart in ${devplist}; do " \
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"if fstype ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"bootfstype; then " \
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"run scan_dev_for_boot; " \
|
||||||
|
"fi; " \
|
||||||
|
"done\0" \
|
||||||
|
"scan_dev_for_boot=" \
|
||||||
|
"echo Scanning ${devtype} " \
|
||||||
|
"${devnum}:${distro_bootpart}...; " \
|
||||||
|
"for prefix in ${boot_prefixes}; do " \
|
||||||
|
"run scan_dev_for_scripts; " \
|
||||||
|
"done;" \
|
||||||
|
"\0" \
|
||||||
|
"boot_a_script=" \
|
||||||
|
"load ${devtype} ${devnum}:${distro_bootpart} " \
|
||||||
|
"${scriptaddr} ${prefix}${script}; " \
|
||||||
|
"env exists secureboot && load ${devtype} " \
|
||||||
|
"${devnum}:${distro_bootpart} " \
|
||||||
|
"${scripthdraddr} ${prefix}${boot_script_hdr} " \
|
||||||
|
"&& esbc_validate ${scripthdraddr};" \
|
||||||
|
"source ${scriptaddr}\0" \
|
||||||
|
"installer=load mmc 0:2 $load_addr " \
|
||||||
|
"/flex_installer_arm64.itb; " \
|
||||||
|
"bootm $load_addr#$board\0" \
|
||||||
|
"qspi_bootcmd=echo Trying load from qspi..;" \
|
||||||
|
"sf probe && sf read $load_addr " \
|
||||||
|
"$kernel_addr $kernel_size; env exists secureboot " \
|
||||||
|
"&& sf read $kernelheader_addr_r $kernelheader_addr " \
|
||||||
|
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
|
||||||
|
"bootm $load_addr#$board\0"
|
||||||
|
|
||||||
|
#undef CONFIG_BOOTCOMMAND
|
||||||
|
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
|
||||||
|
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
|
||||||
|
"env exists secureboot && esbc_halt;"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
|
||||||
|
#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
|
||||||
|
|
||||||
|
#include <asm/fsl_secure_boot.h>
|
||||||
|
|
||||||
|
#endif /* __LS1012A2G5RDB_H__ */
|
Loading…
Reference in New Issue
Block a user