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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

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- Add DM_ETH support for lx2160aqds, ls2080aqds, ls1088aqds
- QSI related fixes on ls1012a, ls2080a, ls1046a, ls1088a, ls1043a based
  platforms
- Bug-fixes/updtaes related to ls1046afrwy, fsl-mc, msi-map property
This commit is contained in:
Tom Rini 2020-05-20 08:46:56 -04:00
commit b0b13f4114
104 changed files with 1692 additions and 506 deletions
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13
arch/arm/dts/Makefile
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@ -374,16 +374,27 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
ls1021a-iot-duart.dtb ls1021a-tsn.dtb
dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-qds-42-x.dtb \
fsl-ls2080a-rdb.dtb \
fsl-ls2081a-rdb.dtb \
fsl-ls2088a-rdb-qspi.dtb \
fsl-ls1088a-rdb.dtb \
fsl-ls1088a-qds.dtb \
fsl-ls1088a-qds-21-x.dtb \
fsl-ls1088a-qds-29-x.dtb \
fsl-ls1028a-rdb.dtb \
fsl-ls1028a-qds-duart.dtb \
fsl-ls1028a-qds-lpuart.dtb \
fsl-lx2160a-rdb.dtb \
fsl-lx2160a-qds.dtb
fsl-lx2160a-qds.dtb \
fsl-lx2160a-qds-3-x-x.dtb \
fsl-lx2160a-qds-3-11-x.dtb \
fsl-lx2160a-qds-7-x-x.dtb \
fsl-lx2160a-qds-7-11-x.dtb \
fsl-lx2160a-qds-19-x-x.dtb \
fsl-lx2160a-qds-19-11-x.dtb \
fsl-lx2160a-qds-20-x-x.dtb \
fsl-lx2160a-qds-20-11-x.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \

5
arch/arm/dts/fsl-ls1012a-2g5rdb.dts
View File

@ -21,14 +21,13 @@
};
&qspi {
bus-num = <0>;
status = "okay";
qflash0: s25fl128s@0 {
s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <20000000>;
spi-max-frequency = <50000000>;
reg = <0>;
};
};

5
arch/arm/dts/fsl-ls1012a-frdm.dtsi
View File

@ -15,14 +15,13 @@
};
&qspi {
bus-num = <0>;
status = "okay";
qflash0: s25fl128s@0 {
s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <20000000>;
spi-max-frequency = <50000000>;
reg = <0>;
};
};

5
arch/arm/dts/fsl-ls1012a-qds.dtsi
View File

@ -43,14 +43,13 @@
};
&qspi {
bus-num = <0>;
status = "okay";
qflash0: s25fl128s@0 {
s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <20000000>;
spi-max-frequency = <50000000>;
reg = <0>;
};
};

5
arch/arm/dts/fsl-ls1012a-rdb.dtsi
View File

@ -19,14 +19,13 @@
};
&qspi {
bus-num = <0>;
status = "okay";
qflash0: s25fl128s@0 {
s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <20000000>;
spi-max-frequency = <50000000>;
reg = <0>;
};
};

4
arch/arm/dts/fsl-ls1012a.dtsi
View File

@ -107,14 +107,12 @@
};
qspi: quadspi@1550000 {
compatible = "fsl,vf610-qspi";
compatible = "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x1550000 0x0 0x10000>,
<0x0 0x40000000 0x0 0x4000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
num-cs = <1>;
big-endian;
status = "disabled";
};

5
arch/arm/dts/fsl-ls1043a-qds.dtsi
View File

@ -53,14 +53,13 @@
};
&qspi {
bus-num = <0>;
status = "okay";
qflash0: s25fl128s@0 {
s25fl128s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <20000000>;
spi-max-frequency = <50000000>;
reg = <0>;
};
};

6
arch/arm/dts/fsl-ls1043a.dtsi
View File

@ -210,14 +210,12 @@
status = "disabled";
};
qspi: quadspi@1550000 {
compatible = "fsl,vf610-qspi";
compatible = "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x1550000 0x0 0x10000>,
<0x0 0x40000000 0x0 0x4000000>;
<0x0 0x40000000 0x0 0x1000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
num-cs = <2>;
big-endian;
status = "disabled";
};

5
arch/arm/dts/fsl-ls1046a-frwy.dts
View File

@ -19,13 +19,12 @@
};
&qspi {
bus-num = <0>;
status = "okay";
qflash0: mt25qu512abb8esf@0 {
mt25qu512a0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
};

5
arch/arm/dts/fsl-ls1046a-qds.dtsi
View File

@ -53,14 +53,13 @@
};
&qspi {
bus-num = <0>;
status = "okay";
qflash0: s25fl128s@0 {
s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <20000000>;
spi-max-frequency = <50000000>;
reg = <0>;
};
};

5
arch/arm/dts/fsl-ls1046a-rdb.dts
View File

@ -21,10 +21,9 @@
};
&qspi {
bus-num = <0>;
status = "okay";
qflash0: s25fs512s@0 {
s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@ -32,7 +31,7 @@
reg = <0>;
};
qflash1: s25fs512s@1 {
s25fs512s1: flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";

4
arch/arm/dts/fsl-ls1046a.dtsi
View File

@ -211,14 +211,12 @@
};
qspi: quadspi@1550000 {
compatible = "fsl,vf610-qspi";
compatible = "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x1550000 0x0 0x10000>,
<0x0 0x40000000 0x0 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
num-cs = <4>;
big-endian;
status = "disabled";
};

16
arch/arm/dts/fsl-ls1088a-qds-21-x.dts Normal file
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@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1088AQDS device tree source for SERDES protocol 21.x
*
* Copyright 2020 NXP
*
*/
/dts-v1/;
#include "fsl-ls1088a-qds-sd1-21.dtsi"
/ {
model = "NXP Layerscape 1088a QDS Board (DTS 21-x)";
compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
};

16
arch/arm/dts/fsl-ls1088a-qds-29-x.dts Normal file
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@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1088AQDS device tree source for SERDES protocol 29.x
*
* Copyright 2020 NXP
*
*/
/dts-v1/;
#include "fsl-ls1088a-qds-sd1-29.dtsi"
/ {
model = "NXP Layerscape 1088a QDS Board (DTS 29-x)";
compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
};

30
arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi Normal file
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@ -0,0 +1,30 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1088AQDS device tree source for SERDES block #1 - protocol 21 (0x15)
*
* Copyright 2020 NXP
*/
#include "fsl-ls1088a-qds.dtsi"
&dpmac1 {
status = "okay";
phy-connection-type = "xfi";
};
&dpmac2 {
status = "okay";
phy-connection-type = "xfi";
};
&dpmac4 {
status = "okay";
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii-id";
};
&dpmac5 {
status = "okay";
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii-id";
};

18
arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi Normal file
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@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1088AQDS device tree source for SERDES block #1 - protocol 29 (0x1d)
*
* Copyright 2020 NXP
*/
#include "fsl-ls1088a-qds.dtsi"
&dpmac1 {
status = "okay";
phy-connection-type = "xfi";
};
&dpmac2 {
status = "okay";
phy-connection-type = "xfi";
};

124
arch/arm/dts/fsl-ls1088a-qds.dts
View File

@ -1,133 +1,15 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP ls1088a QDS board device tree source
* NXP ls1088a QDS default board device tree source
*
* Copyright 2017 NXP
* Copyright 2020 NXP
*/
/dts-v1/;
#include "fsl-ls1088a.dtsi"
#include "fsl-ls1088a-qds.dtsi"
/ {
model = "NXP Layerscape 1088a QDS Board";
compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
aliases {
spi0 = &qspi;
spi1 = &dspi;
};
};
&i2c0 {
status = "okay";
u-boot,dm-pre-reloc;
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
rtc@51 {
compatible = "pcf2127-rtc";
reg = <0x51>;
};
};
};
};
&ifc {
#address-cells = <2>;
#size-cells = <1>;
/* NOR, NAND Flashes and FPGA on board */
ranges = <0 0 0x5 0x80000000 0x08000000
2 0 0x5 0x30000000 0x00010000
3 0 0x5 0x20000000 0x00010000>;
status = "okay";
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
nand@2,0 {
compatible = "fsl,ifc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x1 0x0 0x10000>;
};
fpga: board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus", "fsl,ls1088aqds-fpga",
"fsl,fpga-qixis";
reg = <0x2 0x0 0x0000100>;
bank-width = <1>;
device-width = <1>;
ranges = <0 2 0 0x100>;
};
};
&dspi {
bus-num = <0>;
status = "okay";
dflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <1000000>; /* input clock */
};
dflash1: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <3500000>;
reg = <1>;
};
dflash2: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <3500000>;
reg = <2>;
};
};
&qspi {
bus-num = <0>;
status = "okay";
qflash0: s25fs512s@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
};
qflash1: s25fs512s@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <1>;
};
};
&sata {
status = "okay";
};

186
arch/arm/dts/fsl-ls1088a-qds.dtsi Normal file
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@ -0,0 +1,186 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP ls1088a QDS common board device tree source
*
* Copyright 2017-2020 NXP
*/
#include "fsl-ls1088a.dtsi"
/ {
aliases {
spi0 = &qspi;
spi1 = &dspi;
};
};
&emdio1 {
status = "okay";
};
&emdio2 {
status = "okay";
};
&i2c0 {
status = "okay";
u-boot,dm-pre-reloc;
fpga@66 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "simple-mfd";
reg = <0x66>;
mux-mdio@54 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-i2creg";
reg = <0x54>;
#mux-control-cells = <1>;
mux-reg-masks = <0x54 0xe0>; // reg 0x54, bits 7:5
mdio-parent-bus = <&emdio1>;
mdio@00 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00>;
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
};
mdio@20 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x20>;
rgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
};
emdio1_slot1: mdio@40 { /* I/O Slot #1 */
reg = <0x40>;
device-name = "emdio1_slot1";
#address-cells = <1>;
#size-cells = <0>;
};
emdio1_slot3: mdio@60 { /* I/O Slot #3 */
reg = <0x60>;
device-name = "emdio1_slot3";
#address-cells = <1>;
#size-cells = <0>;
};
};
};
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
rtc@51 {
compatible = "pcf2127-rtc";
reg = <0x51>;
};
};
};
};
&ifc {
#address-cells = <2>;
#size-cells = <1>;
/* NOR, NAND Flashes and FPGA on board */
ranges = <0 0 0x5 0x80000000 0x08000000
2 0 0x5 0x30000000 0x00010000
3 0 0x5 0x20000000 0x00010000>;
status = "okay";
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
nand@2,0 {
compatible = "fsl,ifc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x1 0x0 0x10000>;
};
fpga: board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus", "fsl,ls1088aqds-fpga",
"fsl,fpga-qixis";
reg = <0x2 0x0 0x0000100>;
bank-width = <1>;
device-width = <1>;
ranges = <0 2 0 0x100>;
};
};
&dspi {
bus-num = <0>;
status = "okay";
dflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <1000000>; /* input clock */
};
dflash1: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <3500000>;
reg = <1>;
};
dflash2: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <3500000>;
reg = <2>;
};
};
&qspi {
status = "okay";
s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
};
s25fs512s1: flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <1>;
};
};
&sata {
status = "okay";
};

5
arch/arm/dts/fsl-ls1088a-rdb.dts
View File

@ -143,10 +143,9 @@
};
&qspi {
bus-num = <0>;
status = "okay";
qflash0: s25fs512s@0 {
s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@ -154,7 +153,7 @@
reg = <0>;
};
qflash1: s25fs512s@1 {
s25fs512s1: flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";

2
arch/arm/dts/fsl-ls1088a.dtsi
View File

@ -92,7 +92,7 @@
};
qspi: quadspi@1550000 {
compatible = "fsl,vf610-qspi";
compatible = "fsl,ls1088a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c0000 0x0 0x10000>,

16
arch/arm/dts/fsl-ls2080a-qds-42-x.dts Normal file
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS2080AQDS device tree source for SERDES protocol 42.x
*
* Copyright 2020 NXP
*
*/
/dts-v1/;
#include "fsl-ls2080a-qds-sd1-42.dtsi"
/ {
model = "NXP Layerscape LS2080AQDS Board (DTS 42-x)";
compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
};

48
arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi Normal file
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@ -0,0 +1,48 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS2080aQDS device tree source for SERDES block #1 - protocol 42 (0x2a)
*
* Copyright 2020 NXP
*/
#include "fsl-ls2080a-qds.dtsi"
&dpmac1 {
status = "okay";
phy-connection-type = "xfi";
};
&dpmac2 {
status = "okay";
phy-connection-type = "xfi";
};
&dpmac3 {
status = "okay";
phy-connection-type = "xfi";
};
&dpmac4 {
status = "okay";
phy-connection-type = "xfi";
};
&dpmac5 {
status = "okay";
phy-connection-type = "xfi";
};
&dpmac6 {
status = "okay";
phy-connection-type = "xfi";
};
&dpmac7 {
status = "okay";
phy-connection-type = "xfi";
};
&dpmac8 {
status = "okay";
phy-connection-type = "xfi";
};

73
arch/arm/dts/fsl-ls2080a-qds.dts
View File

@ -1,13 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Freescale ls2080a QDS board device tree source
* Freescale ls2080a QDS defaul board device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*/
/dts-v1/;
#include "fsl-ls2080a.dtsi"
#include "fsl-ls2080a-qds.dtsi"
/ {
model = "Freescale Layerscape 2080a QDS Board";
@ -18,72 +18,3 @@
spi1 = &dspi;
};
};
&i2c0 {
status = "okay";
pca9547@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00>;
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
};
};
};
};
&dspi {
bus-num = <0>;
status = "okay";
dflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
dflash1: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <1>;
};
dflash2: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <2>;
};
};
&qspi {
bus-num = <0>;
status = "okay";
qflash0: s25fs256s@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&sata {
status = "okay";
};

77
arch/arm/dts/fsl-ls2080a-qds.dtsi Normal file
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@ -0,0 +1,77 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Freescale ls2080a QDS common device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
#include "fsl-ls2080a.dtsi"
&i2c0 {
status = "okay";
pca9547@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00>;
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
};
};
};
};
&dspi {
bus-num = <0>;
status = "okay";
dflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
dflash1: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <1>;
};
dflash2: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <2>;
};
};
&qspi {
status = "okay";
s25fs256s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
&sata {
status = "okay";
};

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@ -96,13 +96,13 @@
};
qspi: quadspi@1550000 {
compatible = "fsl,vf610-qspi";
compatible = "fsl,ls2080a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c0000 0x0 0x10000>,
<0x0 0x20000000 0x0 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
num-cs = <4>;
status = "disabled";
};
esdhc: esdhc@0 {

5
arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
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@ -125,10 +125,9 @@
};
&qspi {
bus-num = <0>;
status = "okay";
qflash0: s25fs512s@0 {
s25fs512s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@ -136,7 +135,7 @@
reg = <0>;
};
qflash1: s25fs512s@1 {
s25fs512s1: flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";

19
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@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LX2160AQDS device tree source for SERDES protocol 19.11.x
*
* Copyright 2020 NXP
*
*/
/dts-v1/;
#include "fsl-lx2160a-qds-sd1-19.dtsi"
#include "fsl-lx2160a-qds-sd2-11.dtsi"
/ {
model = "NXP Layerscape LX2160AQDS Board (DTS 19.11.x)";
compatible = "fsl,lx2160aqds", "fsl,lx2160a";
};

17
arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts Normal file
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@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LX2160AQDS device tree source for SERDES protocol 19.x.x
*
* Copyright 2020 NXP
*
*/
/dts-v1/;
#include "fsl-lx2160a-qds-sd1-19.dtsi"
/ {
model = "NXP Layerscape LX2160AQDS Board (DTS 19.x.x)";
compatible = "fsl,lx2160aqds", "fsl,lx2160a";
};

19
arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts Normal file
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@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LX2160AQDS device tree source for SERDES protocol 20.11.x
*
* Copyright 2020 NXP
*
*/
/dts-v1/;
#include "fsl-lx2160a-qds-sd1-20.dtsi"
#include "fsl-lx2160a-qds-sd2-11.dtsi"
/ {
model = "NXP Layerscape LX2160AQDS Board (DTS 20.11.x)";
compatible = "fsl,lx2160aqds", "fsl,lx2160a";
};

17
arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts Normal file
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@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LX2160AQDS device tree source for SERDES protocol 20.x.x
*
* Copyright 2020 NXP
*
*/
/dts-v1/;
#include "fsl-lx2160a-qds-sd1-20.dtsi"
/ {
model = "NXP Layerscape LX2160AQDS Board (DTS 20.x.x)";
compatible = "fsl,lx2160aqds", "fsl,lx2160a";
};

19
arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts Normal file
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@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LX2160AQDS device tree source for SERDES protocol 3.11.x
*
* Copyright 2020 NXP
*
*/
/dts-v1/;
#include "fsl-lx2160a-qds-sd1-3.dtsi"
#include "fsl-lx2160a-qds-sd2-11.dtsi"
/ {
model = "NXP Layerscape LX2160AQDS Board (DTS 3.11.x)";
compatible = "fsl,lx2160aqds", "fsl,lx2160a";
};

17
arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts Normal file
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@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LX2160AQDS device tree source for SERDES protocol 3.x.x
*
* Copyright 2020 NXP
*
*/
/dts-v1/;
#include "fsl-lx2160a-qds-sd1-3.dtsi"
/ {
model = "NXP Layerscape LX2160AQDS Board (DTS 3.x.x)";
compatible = "fsl,lx2160aqds", "fsl,lx2160a";
};

19
arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts Normal file
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@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LX2160AQDS device tree source for SERDES protocol 7.11.x
*
* Copyright 2020 NXP
*
*/
/dts-v1/;
#include "fsl-lx2160a-qds-sd1-7.dtsi"
#include "fsl-lx2160a-qds-sd2-11.dtsi"
/ {
model = "NXP Layerscape LX2160AQDS Board (DTS 7.11.x)";
compatible = "fsl,lx2160aqds", "fsl,lx2160a";
};

17
arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts Normal file
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@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LX2160AQDS device tree source for SERDES protocol 7.x.x
*
* Copyright 2020 NXP
*
*/
/dts-v1/;
#include "fsl-lx2160a-qds-sd1-7.dtsi"
/ {
model = "NXP Layerscape LX2160AQDS Board (DTS 7-x-x)";
compatible = "fsl,lx2160aqds", "fsl,lx2160a";
};

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arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi Normal file
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@ -0,0 +1,75 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 19
*
* Some assumptions are made:
* * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4)
* * mezzanine card M13 is connected to IO SLOT6 (25g-aui for DPMAC 5,6)
* * mezzanine card M7 is connected to IO SLOT2 (xlaui4 for DPMAC 2)
*
* Copyright 2020 NXP
*
*/
#include "fsl-lx2160a-qds.dtsi"
&dpmac2 {
status = "okay";
phy-handle = <&cortina_phy0>;
phy-connection-type = "xlaui4";
};
&dpmac3 {
status = "okay";
phy-handle = <&aquantia_phy1>;
phy-connection-type = "usxgmii";
};
&dpmac4 {
status = "okay";
phy-handle = <&aquantia_phy2>;
phy-connection-type = "usxgmii";
};
&dpmac5 {
status = "okay";
phy-handle = <&inphi_phy0>;
phy-connection-type = "25g-aui";
};
&dpmac6 {
status = "okay";
phy-handle = <&inphi_phy1>;
phy-connection-type = "25g-aui";
};
&emdio1_slot1 {
aquantia_phy1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
aquantia_phy2: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
};
&emdio1_slot2 {
cortina_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
&emdio1_slot6 {
inphi_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0210.7440";
reg = <0x0>;
};
inphi_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0210.7440";
reg = <0x1>;
};
};

39
arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi Normal file
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@ -0,0 +1,39 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 20
*
* Some assumptions are made:
* * 2 mezzanine cards M13 are connected to IO SLOT1 and IO SLOT2
* (xlaui4 for DPMAC 1,2)
*
* Copyright 2020 NXP
*
*/
#include "fsl-lx2160a-qds.dtsi"
&dpmac1 {
status = "okay";
phy-handle = <&cortina_phy1_0>;
phy-connection-type = "xlaui4";
};
&dpmac2 {
status = "okay";
phy-handle = <&cortina_phy2_0>;
phy-connection-type = "xlaui4";
};
&emdio1_slot1 {
cortina_phy1_0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
&emdio1_slot2 {
cortina_phy2_0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};

55
arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi Normal file
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@ -0,0 +1,55 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 3
*
* Some assumptions are made:
* * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4,5,6)
*
* Copyright 2020 NXP
*
*/
#include "fsl-lx2160a-qds.dtsi"
&dpmac3 {
status = "okay";
phy-handle = <&aquantia_phy1>;
phy-connection-type = "usxgmii";
};
&dpmac4 {
status = "okay";
phy-handle = <&aquantia_phy2>;
phy-connection-type = "usxgmii";
};
&dpmac5 {
status = "okay";
phy-handle = <&aquantia_phy3>;
phy-connection-type = "usxgmii";
};
&dpmac6 {
status = "okay";
phy-handle = <&aquantia_phy4>;
phy-connection-type = "usxgmii";
};
&emdio1_slot1 {
aquantia_phy1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
aquantia_phy2: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
aquantia_phy3: ethernet-phy@6 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x2>;
};
aquantia_phy4: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x3>;
};
};

100
arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi Normal file
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@ -0,0 +1,100 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 7
*
* Some assumptions are made:
* * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4,5,6)
* * mezzanine card M1/M4 is connected to IO SLOT2 (sgmii for DPMAC 7,8,9,10)
*
* Copyright 2020 NXP
*
*/
#include "fsl-lx2160a-qds.dtsi"
&dpmac3 {
status = "okay";
phy-handle = <&aquantia_phy1>;
phy-connection-type = "usxgmii";
};
&dpmac4 {
status = "okay";
phy-handle = <&aquantia_phy2>;
phy-connection-type = "usxgmii";
};
&dpmac5 {
status = "okay";
phy-handle = <&aquantia_phy3>;
phy-connection-type = "usxgmii";
};
&dpmac6 {
status = "okay";
phy-handle = <&aquantia_phy4>;
phy-connection-type = "usxgmii";
};
&dpmac7 {
status = "okay";
phy-handle = <&sgmii_phy1>;
phy-connection-type = "sgmii";
};
&dpmac8 {
status = "okay";
phy-handle = <&sgmii_phy2>;
phy-connection-type = "sgmii";
};
&dpmac9 {
status = "okay";
phy-handle = <&sgmii_phy3>;
phy-connection-type = "sgmii";
};
&dpmac10 {
status = "okay";
phy-handle = <&sgmii_phy4>;
phy-connection-type = "sgmii";
};
&emdio1_slot1 {
aquantia_phy1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
aquantia_phy2: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
aquantia_phy3: ethernet-phy@6 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x2>;
};
aquantia_phy4: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x3>;
};
};
&emdio1_slot2 {
sgmii_phy1: ethernet-phy@1c {
reg = <0x1c>;
};
sgmii_phy2: ethernet-phy@1d {
reg = <0x1d>;
};
sgmii_phy3: ethernet-phy@1e {
reg = <0x1e>;
};
sgmii_phy4: ethernet-phy@1f {
reg = <0x1f>;
};
};

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@ -0,0 +1,76 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LX2160AQDS device tree source for the SERDES block #2 - protocol 11
*
* Some assumptions are made:
* * 2 mezzanine cards M1/M4 are connected to IO SLOT 7 and IO SLOT 8
* (sgmii for DPMAC 12, 13, 14, 16, 17, 18)
*
* Copyright 2020 NXP
*
*/
#include "fsl-lx2160a-qds.dtsi"
&dpmac12 {
status = "okay";
phy-handle = <&sgmii_phy7_2>;
phy-connection-type = "sgmii";
};
&dpmac17 {
status = "okay";
phy-handle = <&sgmii_phy7_3>;
phy-connection-type = "sgmii";
};
&dpmac18 {
status = "okay";
phy-handle = <&sgmii_phy7_4>;
phy-connection-type = "sgmii";
};
&dpmac16 {
status = "okay";
phy-handle = <&sgmii_phy8_2>;
phy-connection-type = "sgmii";
};
&dpmac13 {
status = "okay";
phy-handle = <&sgmii_phy8_3>;
phy-connection-type = "sgmii";
};
&dpmac14 {
status = "okay";
phy-handle = <&sgmii_phy8_4>;
phy-connection-type = "sgmii";
};
&emdio1_slot7 {
sgmii_phy7_2: ethernet-phy@1d {
reg = <0x1d>;
};
sgmii_phy7_3: ethernet-phy@1e {
reg = <0x1e>;
};
sgmii_phy7_4: ethernet-phy@1f {
reg = <0x1f>;
};
};
&emdio1_slot8 {
sgmii_phy8_2: ethernet-phy@1d {
reg = <0x1d>;
};
sgmii_phy8_3: ethernet-phy@1e {
reg = <0x1e>;
};
sgmii_phy8_4: ethernet-phy@1f {
reg = <0x1f>;
};
};

67
arch/arm/dts/fsl-lx2160a-qds.dts
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@ -1,14 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LX2160AQDS device tree source
* NXP LX2160AQDS default device tree source
*
* Copyright 2018-2019 NXP
* Copyright 2020 NXP
*
*/
/dts-v1/;
#include "fsl-lx2160a.dtsi"
#include "fsl-lx2160a-qds.dtsi"
/ {
model = "NXP Layerscape LX2160AQDS Board";
@ -17,64 +17,3 @@
spi0 = &fspi;
};
};
&esdhc0 {
status = "okay";
};
&esdhc1 {
status = "okay";
};
&i2c0 {
status = "okay";
u-boot,dm-pre-reloc;
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
rtc@51 {
compatible = "pcf2127-rtc";
reg = <0x51>;
};
};
};
};
&fspi {
status = "okay";
mt35xu512aba0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
spi-rx-bus-width = <8>;
spi-tx-bus-width = <1>;
};
};
&sata0 {
status = "okay";
};
&sata1 {
status = "okay";
};
&sata2 {
status = "okay";
};
&sata3 {
status = "okay";
};

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@ -0,0 +1,169 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LX2160AQDS common device tree source
*
* Copyright 2018-2019 NXP
*
*/
#include "fsl-lx2160a.dtsi"
&dpmac17 {
status = "okay";
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii-id";
};
&dpmac18 {
status = "okay";
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii-id";
};
&emdio1 {
status = "okay";
};
&emdio2 {
status = "okay";
};
&esdhc0 {
status = "okay";
};
&esdhc1 {
status = "okay";
};
&i2c0 {
status = "okay";
u-boot,dm-pre-reloc;
fpga@66 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "simple-mfd";
reg = <0x66>;
mux-mdio@54 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-i2creg";
reg = <0x54>;
#mux-control-cells = <1>;
mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3
mdio-parent-bus = <&emdio1>;
mdio@00 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00>;
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
};
mdio@08 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40>;
rgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
};
emdio1_slot1: mdio@c0 { /* I/O Slot #1 */
reg = <0xC0>;
device-name = "emdio1_slot1";
#address-cells = <1>;
#size-cells = <0>;
};
emdio1_slot2: mdio@c8 { /* I/O Slot #2 */
reg = <0xC8>;
device-name = "emdio1_slot2";
#address-cells = <1>;
#size-cells = <0>;
};
emdio1_slot3: mdio@d0 { /* I/O Slot #3 */
reg = <0xD0>;
device-name = "emdio1_slot3";
#address-cells = <1>;
#size-cells = <0>;
};
emdio1_slot4: mdio@d8 { /* I/O Slot #4 */
reg = <0xD8>;
device-name = "emdio1_slot4";
#address-cells = <1>;
#size-cells = <0>;
};
emdio1_slot5: mdio@e0 { /* I/O Slot #5 */
reg = <0xE0>;
device-name = "emdio1_slot5";
#address-cells = <1>;
#size-cells = <0>;
};
emdio1_slot6: mdio@e8 { /* I/O Slot #6 */
reg = <0xE8>;
device-name = "emdio1_slot6";
#address-cells = <1>;
#size-cells = <0>;
};
emdio1_slot7: mdio@f0 { /* I/O Slot #7 */
reg = <0xF0>;
device-name = "emdio1_slot7";
#address-cells = <1>;
#size-cells = <0>;
};
emdio1_slot8: mdio@f8 { /* I/O Slot #8 */
reg = <0xF8>;
device-name = "emdio1_slot8";
#address-cells = <1>;
#size-cells = <0>;
};
};
};
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
rtc@51 {
compatible = "pcf2127-rtc";
reg = <0x51>;
};
};
};
};
&sata0 {
status = "okay";
};
&sata1 {
status = "okay";
};
&sata2 {
status = "okay";
};
&sata3 {
status = "okay";
};

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@ -2,7 +2,7 @@
/*
* NXP lx2160a SOC common device tree source
*
* Copyright 2018 NXP
* Copyright 2018-2020 NXP
*
*/
@ -383,6 +383,18 @@
#address-cells = <1>;
#size-cells = <0>;
dpmac1: dpmac@1 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x1>;
status = "disabled";
};
dpmac2: dpmac@2 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x2>;
status = "disabled";
};
dpmac3: dpmac@3 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x3>;
@ -395,6 +407,78 @@
status = "disabled";
};
dpmac5: dpmac@5 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x5>;
status = "disabled";
};
dpmac6: dpmac@6 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x6>;
status = "disabled";
};
dpmac7: dpmac@7 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x7>;
status = "disabled";
};
dpmac8: dpmac@8 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x8>;
status = "disabled";
};
dpmac9: dpmac@9 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x9>;
status = "disabled";
};
dpmac10: dpmac@a {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xa>;
status = "disabled";
};
dpmac11: dpmac@b {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xb>;
status = "disabled";
};
dpmac12: dpmac@c {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xc>;
status = "disabled";
};
dpmac13: dpmac@d {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xd>;
status = "disabled";
};
dpmac14: dpmac@e {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xe>;
status = "disabled";
};
dpmac15: dpmac@f {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xf>;
status = "disabled";
};
dpmac16: dpmac@10 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x10>;
status = "disabled";
};
dpmac17: dpmac@11 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x11>;

5
arch/arm/dts/ls1021a-twr.dtsi
View File

@ -24,14 +24,13 @@
};
&qspi {
bus-num = <0>;
status = "okay";
qflash0: n25q128a13@0 {
n25q128a130: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <20000000>;
spi-max-frequency = <50000000>;
reg = <0>;
};
};

6
arch/arm/dts/ls1021a.dtsi
View File

@ -169,14 +169,12 @@
};
qspi: quadspi@1550000 {
compatible = "fsl,vf610-qspi";
compatible = "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1550000 0x10000>,
<0x40000000 0x4000000>;
<0x40000000 0x1000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
num-cs = <2>;
big-endian;
status = "disabled";
};

1
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -310,7 +310,6 @@
#define CONFIG_SYS_FSL_ESDHC_BE
#define CONFIG_SYS_FSL_WDOG_BE
#define CONFIG_SYS_FSL_DSPI_BE
#define CONFIG_SYS_FSL_QSPI_BE
#define CONFIG_SYS_FSL_CCSR_GUR_BE
#define CONFIG_SYS_FSL_PEX_LUT_BE

1
arch/arm/include/asm/arch-ls102xa/config.h
View File

@ -94,7 +94,6 @@
#define CONFIG_SYS_FSL_ESDHC_BE
#define CONFIG_SYS_FSL_WDOG_BE
#define CONFIG_SYS_FSL_DSPI_BE
#define CONFIG_SYS_FSL_QSPI_BE
#define CONFIG_SYS_FSL_DCU_BE
#define CONFIG_SYS_FSL_SEC_MON_LE
#define CONFIG_SYS_FSL_SFP_VER_3_2

89
board/freescale/ls1088a/eth_ls1088aqds.c
View File

@ -26,6 +26,7 @@
#include "ls1088a_qixis.h"
#ifndef CONFIG_DM_ETH
#ifdef CONFIG_FSL_MC_ENET
#define SFP_TX 0
@ -737,6 +738,7 @@ int board_eth_init(bd_t *bis)
error = pci_eth_init(bis);
return error;
}
#endif // !CONFIG_DM_ETH
#if defined(CONFIG_RESET_PHY_R)
void reset_phy(void)
@ -744,3 +746,90 @@ void reset_phy(void)
mc_env_boot();
}
#endif /* CONFIG_RESET_PHY_R */
#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
/* Structure to hold SERDES protocols supported in case of
* CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
*
* @serdes_block: the index of the SERDES block
* @serdes_protocol: the decimal value of the protocol supported
* @dts_needed: DTS notes describing the current configuration are needed
*
* When dts_needed is true, the board_fit_config_name_match() function
* will try to exactly match the current configuration of the block with a DTS
* name provided.
*/
static struct serdes_configuration {
u8 serdes_block;
u32 serdes_protocol;
bool dts_needed;
} supported_protocols[] = {
/* Serdes block #1 */
{1, 21, true},
{1, 29, true},
};
#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
static bool protocol_supported(u8 serdes_block, u32 protocol)
{
struct serdes_configuration serdes_conf;
int i;
for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
serdes_conf = supported_protocols[i];
if (serdes_conf.serdes_block == serdes_block &&
serdes_conf.serdes_protocol == protocol)
return true;
}
return false;
}
static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
{
struct serdes_configuration serdes_conf;
int i;
for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
serdes_conf = supported_protocols[i];
if (serdes_conf.serdes_block == serdes_block &&
serdes_conf.serdes_protocol == protocol) {
if (serdes_conf.dts_needed == true)
sprintf(str, "%u", protocol);
else
sprintf(str, "x");
return;
}
}
}
int board_fit_config_name_match(const char *name)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
char expected_dts[100];
char srds_s1_str[2];
u32 srds_s1, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
FSL_CHASSIS3_SRDS1_PRTCL_MASK;
cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
srds_s1 = serdes_get_number(FSL_SRDS_1, cfg);
/* Check for supported protocols. The default DTS will be used
* in this case
*/
if (!protocol_supported(1, srds_s1))
return -1;
get_str_protocol(1, srds_s1, srds_s1_str);
sprintf(expected_dts, "fsl-ls1088a-qds-%s-x", srds_s1_str);
if (!strcmp(name, expected_dts))
return 0;
return -1;
}
#endif

112
board/freescale/ls2080aqds/eth.c
View File

@ -26,6 +26,8 @@
#define MC_BOOT_ENV_VAR "mcinitcmd"
#ifndef CONFIG_DM_ETH
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
/* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
* Bank 1 -> Lanes A, B, C, D, E, F, G, H
@ -891,10 +893,11 @@ void ls2080a_handle_phy_interface_xsgmii(int i)
}
}
#endif
#endif // !CONFIG_DM_ETH
int board_eth_init(bd_t *bis)
{
int error;
#ifndef CONFIG_DM_ETH
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
@ -908,6 +911,7 @@ int board_eth_init(bd_t *bis)
struct memac_mdio_info *memac_mdio1_info;
unsigned int i;
char *env_hwconfig;
int error;
env_hwconfig = env_get("hwconfig");
@ -972,8 +976,13 @@ int board_eth_init(bd_t *bis)
sgmii_configure_repeater(2);
}
#endif
error = pci_eth_init(bis);
return error;
#endif // !CONFIG_DM_ETH
#ifdef CONFIG_DM_ETH
return 0;
#else
return pci_eth_init(bis);
#endif
}
#if defined(CONFIG_RESET_PHY_R)
@ -982,3 +991,100 @@ void reset_phy(void)
mc_env_boot();
}
#endif /* CONFIG_RESET_PHY_R */
#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
/* Structure to hold SERDES protocols supported in case of
* CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
*
* @serdes_block: the index of the SERDES block
* @serdes_protocol: the decimal value of the protocol supported
* @dts_needed: DTS notes describing the current configuration are needed
*
* When dts_needed is true, the board_fit_config_name_match() function
* will try to exactly match the current configuration of the block with a DTS
* name provided.
*/
static struct serdes_configuration {
u8 serdes_block;
u32 serdes_protocol;
bool dts_needed;
} supported_protocols[] = {
/* Serdes block #1 */
{1, 42, true},
/* Serdes block #2 */
{2, 65, false},
};
#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
static bool protocol_supported(u8 serdes_block, u32 protocol)
{
struct serdes_configuration serdes_conf;
int i;
for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
serdes_conf = supported_protocols[i];
if (serdes_conf.serdes_block == serdes_block &&
serdes_conf.serdes_protocol == protocol)
return true;
}
return false;
}
static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
{
struct serdes_configuration serdes_conf;
int i;
for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
serdes_conf = supported_protocols[i];
if (serdes_conf.serdes_block == serdes_block &&
serdes_conf.serdes_protocol == protocol) {
if (serdes_conf.dts_needed == true)
sprintf(str, "%u", protocol);
else
sprintf(str, "x");
return;
}
}
}
int board_fit_config_name_match(const char *name)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 rcw_status = in_le32(&gur->rcwsr[28]);
char srds_s1_str[2], srds_s2_str[2];
u32 srds_s1, srds_s2;
char expected_dts[100];
srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
/* Check for supported protocols. The default DTS will be used
* in this case
*/
if (!protocol_supported(1, srds_s1) ||
!protocol_supported(2, srds_s2))
return -1;
get_str_protocol(1, srds_s1, srds_s1_str);
get_str_protocol(2, srds_s2, srds_s2_str);
printf("expected_dts %s\n", expected_dts);
sprintf(expected_dts, "fsl-ls2080a-qds-%s-%s",
srds_s1_str, srds_s2_str);
if (!strcmp(name, expected_dts))
return 0;
printf("this is not!\n");
return -1;
}
#endif

4
board/freescale/ls2080aqds/ls2080aqds.c
View File

@ -252,6 +252,10 @@ int board_init(void)
ppa_init();
#endif
#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
pci_init();
#endif
return 0;
}

119
board/freescale/lx2160a/eth_lx2160aqds.c
View File

@ -28,6 +28,7 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_DM_ETH
#define EMI_NONE 0
#define EMI1 1 /* Mdio Bus 1 */
#define EMI2 2 /* Mdio Bus 2 */
@ -442,9 +443,11 @@ static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
}
#endif
#endif /* !CONFIG_DM_ETH */
int board_eth_init(bd_t *bis)
{
#ifndef CONFIG_DM_ETH
#if defined(CONFIG_FSL_MC_ENET)
struct memac_mdio_info mdio_info;
struct memac_mdio_controller *regs;
@ -567,6 +570,7 @@ int board_eth_init(bd_t *bis)
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
#endif /* !CONFIG_DM_ETH */
#ifdef CONFIG_PHY_AQUANTIA
/*
@ -580,7 +584,12 @@ int board_eth_init(bd_t *bis)
gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
#endif
#ifdef CONFIG_DM_ETH
return 0;
#else
return pci_eth_init(bis);
#endif
}
#if defined(CONFIG_RESET_PHY_R)
@ -592,6 +601,7 @@ void reset_phy(void)
}
#endif /* CONFIG_RESET_PHY_R */
#ifndef CONFIG_DM_ETH
#if defined(CONFIG_FSL_MC_ENET)
int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
{
@ -840,4 +850,113 @@ int fdt_fixup_board_phy(void *fdt)
return ret;
}
#endif // CONFIG_FSL_MC_ENET
#endif
#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
/* Structure to hold SERDES protocols supported in case of
* CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
*
* @serdes_block: the index of the SERDES block
* @serdes_protocol: the decimal value of the protocol supported
* @dts_needed: DTS notes describing the current configuration are needed
*
* When dts_needed is true, the board_fit_config_name_match() function
* will try to exactly match the current configuration of the block with a DTS
* name provided.
*/
static struct serdes_configuration {
u8 serdes_block;
u32 serdes_protocol;
bool dts_needed;
} supported_protocols[] = {
/* Serdes block #1 */
{1, 3, true},
{1, 7, true},
{1, 19, true},
{1, 20, true},
/* Serdes block #2 */
{2, 2, false},
{2, 3, false},
{2, 5, false},
{2, 11, true},
/* Serdes block #3 */
{3, 2, false},
{3, 3, false},
};
#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
static bool protocol_supported(u8 serdes_block, u32 protocol)
{
struct serdes_configuration serdes_conf;
int i;
for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
serdes_conf = supported_protocols[i];
if (serdes_conf.serdes_block == serdes_block &&
serdes_conf.serdes_protocol == protocol)
return true;
}
return false;
}
static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
{
struct serdes_configuration serdes_conf;
int i;
for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
serdes_conf = supported_protocols[i];
if (serdes_conf.serdes_block == serdes_block &&
serdes_conf.serdes_protocol == protocol) {
if (serdes_conf.dts_needed == true)
sprintf(str, "%u", protocol);
else
sprintf(str, "x");
return;
}
}
}
int board_fit_config_name_match(const char *name)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 rcw_status = in_le32(&gur->rcwsr[28]);
char srds_s1_str[2], srds_s2_str[2], srds_s3_str[2];
u32 srds_s1, srds_s2, srds_s3;
char expected_dts[100];
srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
srds_s3 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;
srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;
/* Check for supported protocols. The default DTS will be used
* in this case
*/
if (!protocol_supported(1, srds_s1) ||
!protocol_supported(2, srds_s2) ||
!protocol_supported(3, srds_s3))
return -1;
get_str_protocol(1, srds_s1, srds_s1_str);
get_str_protocol(2, srds_s2, srds_s2_str);
get_str_protocol(3, srds_s3, srds_s3_str);
sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s-%s",
srds_s1_str, srds_s2_str, srds_s3_str);
if (!strcmp(name, expected_dts))
return 0;
return -1;
}
#endif

5
board/freescale/lx2160a/lx2160a.c
View File

@ -586,6 +586,9 @@ int board_init(void)
sec_init();
#endif
#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
pci_init();
#endif
return 0;
}
@ -631,7 +634,9 @@ void fdt_fixup_board_enet(void *fdt)
if (get_mc_boot_status() == 0 &&
(is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
fdt_status_okay(fdt, offset);
#ifndef CONFIG_DM_ETH
fdt_fixup_board_phy(fdt);
#endif
} else {
fdt_status_fail(fdt, offset);
}

8
common/board_r.c
View File

@ -373,11 +373,19 @@ static int initr_binman(void)
}
#if defined(CONFIG_MTD_NOR_FLASH)
__weak int is_flash_available(void)
{
return 1;
}
static int initr_flash(void)
{
ulong flash_size = 0;
bd_t *bd = gd->bd;
if (!is_flash_available())
return 0;
puts("Flash: ");
if (board_flash_wp_on())

3
configs/ls1012a2g5rdb_qspi_defconfig
View File

@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012A2G5RDB=y
CONFIG_SYS_TEXT_BASE=0x40100000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
@ -44,6 +44,7 @@ CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y

3
configs/ls1012a2g5rdb_tfa_defconfig
View File

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1012A2G5RDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
@ -44,6 +44,7 @@ CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y

3
configs/ls1012afrdm_qspi_defconfig
View File

@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRDM=y
CONFIG_SYS_TEXT_BASE=0x40100000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
@ -41,6 +41,7 @@ CONFIG_DM_I2C=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y

3
configs/ls1012afrdm_tfa_defconfig
View File

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRDM=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
@ -41,6 +41,7 @@ CONFIG_DM_I2C=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y

2
configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
View File

@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRWY=y
CONFIG_SYS_TEXT_BASE=0x40100000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_DM_GPIO=y
CONFIG_FSL_LS_PPA=y

3
configs/ls1012afrwy_qspi_defconfig
View File

@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRWY=y
CONFIG_SYS_TEXT_BASE=0x40100000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x1D0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
@ -35,6 +35,7 @@ CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x401D0000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y

2
configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
View File

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRWY=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_DM_GPIO=y
CONFIG_NR_DRAM_BANKS=2

4
configs/ls1012afrwy_tfa_defconfig
View File

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRWY=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x1D0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
@ -34,7 +34,7 @@ CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x401D0000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y

3
configs/ls1012aqds_qspi_defconfig
View File

@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012AQDS=y
CONFIG_SYS_TEXT_BASE=0x40100000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
@ -60,6 +60,7 @@ CONFIG_SF_DEFAULT_BUS=1
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y

3
configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
View File

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1012AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_DM_GPIO=y
CONFIG_QSPI_AHB_INIT=y
@ -49,6 +49,7 @@ CONFIG_SF_DEFAULT_BUS=1
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y

3
configs/ls1012aqds_tfa_defconfig
View File

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1012AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
@ -60,6 +60,7 @@ CONFIG_SF_DEFAULT_BUS=1
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y

3
configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
View File

@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012ARDB=y
CONFIG_SYS_TEXT_BASE=0x40100000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_DM_GPIO=y
CONFIG_FSL_LS_PPA=y
@ -44,6 +44,7 @@ CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_E1000=y
CONFIG_PCI=y

3
configs/ls1012ardb_qspi_defconfig
View File

@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012ARDB=y
CONFIG_SYS_TEXT_BASE=0x40100000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x300000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
@ -46,6 +46,7 @@ CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y

3
configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
View File

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1012ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_DM_GPIO=y
CONFIG_QSPI_AHB_INIT=y
@ -43,6 +43,7 @@ CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y

4
configs/ls1012ardb_tfa_defconfig
View File

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1012ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
@ -35,7 +35,6 @@ CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x40500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
@ -46,6 +45,7 @@ CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y

1
configs/ls1043aqds_qspi_defconfig
View File

@ -44,6 +44,7 @@ CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y

1
configs/ls1043aqds_sdcard_qspi_defconfig
View File

@ -58,6 +58,7 @@ CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y

2
configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
View File

@ -48,6 +48,7 @@ CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
@ -62,6 +63,7 @@ CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y

1
configs/ls1043aqds_tfa_defconfig
View File

@ -58,6 +58,7 @@ CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y

1
configs/ls1046afrwy_tfa_defconfig
View File

@ -32,6 +32,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x40500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y

2
configs/ls1046aqds_qspi_defconfig
View File

@ -34,6 +34,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:2m(uboot),14m(free)"
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x40300000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
@ -42,6 +43,7 @@ CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y

1
configs/ls1046aqds_sdcard_qspi_defconfig
View File

@ -58,6 +58,7 @@ CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y

1
configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
View File

@ -47,6 +47,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y

5
configs/ls1046aqds_tfa_defconfig
View File

@ -4,7 +4,7 @@ CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x500000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
@ -42,7 +42,7 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=0
CONFIG_ENV_ADDR=0x60500000
CONFIG_ENV_ADDR=0x40500000
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
@ -57,6 +57,7 @@ CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SF_DEFAULT_BUS=1
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y

1
configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
View File

@ -37,6 +37,7 @@ CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y

2
configs/ls1046ardb_qspi_defconfig
View File

@ -30,6 +30,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.i
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x40300000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
@ -40,6 +41,7 @@ CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y

1
configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
View File

@ -37,6 +37,7 @@ CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y

2
configs/ls1046ardb_tfa_defconfig
View File

@ -33,6 +33,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x40500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
@ -42,6 +43,7 @@ CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y

10
configs/ls1088aqds_tfa_defconfig
View File

@ -27,6 +27,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
@ -35,11 +36,13 @@ CONFIG_CMD_USB=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_OF_LIST="fsl-ls1088a-qds-21-x fsl-ls1088a-qds-29-x"
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x80500000
CONFIG_ENV_ADDR=0x20500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
@ -66,8 +69,13 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

2
configs/ls1088ardb_tfa_defconfig
View File

@ -39,7 +39,7 @@ CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x80500000
CONFIG_ENV_ADDR=0x20500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y

11
configs/ls2088aqds_tfa_defconfig
View File

@ -22,6 +22,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@ -34,10 +35,13 @@ CONFIG_MP=y
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_OF_LIST="fsl-ls2080a-qds-42-x"
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x80500000
CONFIG_ENV_ADDR=0x20500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
@ -61,9 +65,14 @@ CONFIG_PHYLIB_10G=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

1
configs/ls2088ardb_qspi_defconfig
View File

@ -32,6 +32,7 @@ CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x20300000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y

3
configs/ls2088ardb_tfa_defconfig
View File

@ -39,7 +39,8 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x80500000
CONFIG_ENV_ADDR=0x20500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y

8
configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
View File

@ -21,6 +21,7 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x2
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@ -31,6 +32,8 @@ CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds"
CONFIG_OF_LIST="fsl-lx2160a-qds-3-x-x fsl-lx2160a-qds-7-x-x fsl-lx2160a-qds-19-x-x fsl-lx2160a-qds-20-x-x fsl-lx2160a-qds-3-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-19-11-x fsl-lx2160a-qds-20-11-x"
CONFIG_MULTI_DTB_FIT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
@ -53,7 +56,12 @@ CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_E1000=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

8
configs/lx2160aqds_tfa_defconfig
View File

@ -23,6 +23,7 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x2
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@ -33,6 +34,8 @@ CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds"
CONFIG_OF_LIST="fsl-lx2160a-qds-3-x-x fsl-lx2160a-qds-7-x-x fsl-lx2160a-qds-19-x-x fsl-lx2160a-qds-20-x-x fsl-lx2160a-qds-3-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-19-11-x fsl-lx2160a-qds-20-11-x"
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x20500000
@ -57,7 +60,12 @@ CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_E1000=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

2
drivers/net/fm/eth.c
View File

@ -57,10 +57,10 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
bus.priv = priv->mac->phyregs;
#else
bus.priv = priv->pcs_mdio;
#endif
bus.read = memac_mdio_read;
bus.write = memac_mdio_write;
bus.reset = memac_mdio_reset;
#endif
qsgmii_loop:
/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */

34
drivers/net/fsl-mc/mc.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP
* Copyright 2017-2018, 2020 NXP
*/
#include <common.h>
#include <command.h>
@ -320,7 +320,7 @@ void fdt_fixup_mc_ddr(u64 *base, u64 *size)
void fdt_fsl_mc_fixup_iommu_map_entry(void *blob)
{
u32 *prop;
u32 iommu_map[4];
u32 iommu_map[4], phandle;
int offset;
int lenp;
@ -349,6 +349,21 @@ void fdt_fsl_mc_fixup_iommu_map_entry(void *blob)
fdt_setprop_inplace(blob, offset, "iommu-map",
iommu_map, sizeof(iommu_map));
/* get phandle to MSI controller */
prop = (u32 *)fdt_getprop(blob, offset, "msi-parent", 0);
if (!prop) {
debug("\n%s: ERROR: missing msi-parent\n", __func__);
return;
}
phandle = fdt32_to_cpu(*prop);
/* also set msi-map property */
fdt_appendprop_u32(blob, offset, "msi-map", FSL_DPAA2_STREAM_ID_START);
fdt_appendprop_u32(blob, offset, "msi-map", phandle);
fdt_appendprop_u32(blob, offset, "msi-map", FSL_DPAA2_STREAM_ID_START);
fdt_appendprop_u32(blob, offset, "msi-map", FSL_DPAA2_STREAM_ID_END -
FSL_DPAA2_STREAM_ID_START + 1);
}
static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id,
@ -466,8 +481,19 @@ static int mc_fixup_dpc(u64 dpc_addr)
/* fixup MAC addresses for dpmac ports */
nodeoffset = fdt_path_offset(blob, "/board_info/ports");
if (nodeoffset < 0)
goto out;
if (nodeoffset < 0) {
err = fdt_increase_size(blob, 512);
if (err) {
printf("fdt_increase_size: err=%s\n",
fdt_strerror(err));
goto out;
}
nodeoffset = fdt_path_offset(blob, "/board_info");
if (nodeoffset < 0)
nodeoffset = fdt_add_subnode(blob, 0, "board_info");
nodeoffset = fdt_add_subnode(blob, nodeoffset, "ports");
}
err = mc_fixup_mac_addrs(blob, MC_FIXUP_DPC);

19
include/configs/ls1012a_common.h
View File

@ -34,26 +34,11 @@
#define CONFIG_LAYERSCAPE_NS_ACCESS
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
/*SPI device */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_TFABOOT)
#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_FSL_SPI_INTERFACE
#define CONFIG_SF_DATAFLASH
#define QSPI0_AMBA_BASE 0x40000000
#define CONFIG_SPI_FLASH_SPANSION
#define FSL_QSPI_FLASH_SIZE SZ_64M
#define FSL_QSPI_FLASH_NUM 2
/*
* Environment
*/
#define CONFIG_ENV_OVERWRITE
#endif
#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
/* SATA */
#define CONFIG_SCSI_AHCI_PLAT

3
include/configs/ls1012afrwy.h
View File

@ -34,9 +34,6 @@
func(DHCP, dhcp, na)
#endif
#undef FSL_QSPI_FLASH_SIZE
#define FSL_QSPI_FLASH_SIZE SZ_16M
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33

3
include/configs/ls1012ardb.h
View File

@ -15,9 +15,6 @@
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
#define CONFIG_CMD_MEMINFO
/* ENV */
#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
/*
* I2C IO expander
*/

6
include/configs/ls1021aiot.h
View File

@ -138,12 +138,6 @@
/* SPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SPI_FLASH_SPANSION
/* QSPI */
#define QSPI0_AMBA_BASE 0x40000000
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
#define CONFIG_SPI_FLASH_SPANSION
#endif
/* DM SPI */

11
include/configs/ls1021aqds.h
View File

@ -363,20 +363,9 @@ unsigned long get_board_ddr_clk(void);
* MMC
*/
/* SPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
/* QSPI */
#define QSPI0_AMBA_BASE 0x40000000
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
/* DSPI */
/* DM SPI */
#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
#define CONFIG_DM_SPI_FLASH
#define CONFIG_SPI_FLASH_DATAFLASH
#endif
#endif
/*

10
include/configs/ls1021atwr.h
View File

@ -234,16 +234,6 @@
* MMC
*/
/* SPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
/* QSPI */
#define QSPI0_AMBA_BASE 0x40000000
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
/* DSPI */
#endif
/* DM SPI */
#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
#define CONFIG_DM_SPI_FLASH

10
include/configs/ls1043aqds.h
View File

@ -376,16 +376,6 @@ unsigned long get_board_ddr_clk(void);
#define VDD_MV_MIN 819
#define VDD_MV_MAX 1212
/* QSPI device */
#if defined(CONFIG_TFABOOT) || \
(defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI))
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_SPANSION
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
#endif
#endif
/*
* Miscellaneous configurable options
*/

19
include/configs/ls1046afrwy.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
#ifndef __LS1046AFRWY_H__
@ -96,12 +96,17 @@
/*
* Environment
*/
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
#ifndef CONFIG_SPL_BUILD
#undef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(USB, usb, 0) \
func(DHCP, dhcp, na)
#endif
/* FMan */
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
@ -117,12 +122,6 @@
#endif
/* QSPI device */
#ifdef CONFIG_FSL_QSPI
#define FSL_QSPI_FLASH_SIZE SZ_64M
#define FSL_QSPI_FLASH_NUM 1
#endif
#undef CONFIG_BOOTCOMMAND
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
"env exists secureboot && esbc_halt;;"

19
include/configs/ls1046aqds.h
View File

@ -41,16 +41,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SPI_FLASH_EON /* cs2 */
#endif
/* QSPI */
#if defined(CONFIG_TFABOOT) || \
defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_SPANSION
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
#endif
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2
@ -419,16 +409,7 @@ unsigned long get_board_ddr_clk(void);
/*
* Environment
*/
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_TFABOOT
#define CONFIG_SYS_MMC_ENV_DEV 0
#else
#ifdef CONFIG_NAND_BOOT
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
#endif
#define CONFIG_CMDLINE_TAG

20
include/configs/ls1046ardb.h
View File

@ -153,19 +153,8 @@
/*
* Environment
*/
#ifndef SPL_NO_ENV
#define CONFIG_ENV_OVERWRITE
#endif
#ifdef CONFIG_TFABOOT
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
#else
#if defined(CONFIG_SD_BOOT)
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
#endif
#define AQR105_IRQ_MASK 0x80000000
/* FMan */
@ -186,15 +175,6 @@
#endif
/* QSPI device */
#ifndef SPL_NO_QSPI
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_SPANSION
#define FSL_QSPI_FLASH_SIZE (1 << 26)
#define FSL_QSPI_FLASH_NUM 2
#endif
#endif
#ifndef SPL_NO_MISC
#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT

6
include/configs/ls1088a_common.h
View File

@ -35,13 +35,7 @@
#endif
/* Link Definitions */
#ifdef CONFIG_TFABOOT
#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
#else
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
#endif
#endif
#define CONFIG_SKIP_LOWLEVEL_INIT

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