mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-03 10:00:42 +09:00
S5P:SROM config code moved to s5p-common directory
SROM config code is made common for S5P series of boards. smdkc100.c now refers to s5p-common/sromc.c for SROM related subroutines. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
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920c428d0a
commit
b0ad862177
@ -27,7 +27,8 @@ LIB = $(obj)libs5p-common.o
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COBJS-y += cpu_info.o
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COBJS-y += cpu_info.o
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COBJS-y += timer.o
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COBJS-y += timer.o
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COBJS-$(CONFIG_PWM) += pwm.o
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COBJS-y += sromc.o
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COBJS-$(CONFIG_PWM) += pwm.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
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OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
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@ -23,27 +23,27 @@
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#include <common.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/arch/smc.h>
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#include <asm/arch/sromc.h>
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/*
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/*
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* s5pc1xx_config_sromc() - select the proper SROMC Bank and configure the
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* s5p_config_sromc() - select the proper SROMC Bank and configure the
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* band width control and bank control registers
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* band width control and bank control registers
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* srom_bank - SROM Bank 0 to 5
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* srom_bank - SROM
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* smc_bw_conf - SMC Band witdh reg configuration value
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* srom_bw_conf - SMC Band witdh reg configuration value
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* smc_bc_conf - SMC Bank Control reg configuration value
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* srom_bc_conf - SMC Bank Control reg configuration value
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*/
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*/
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void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf)
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void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf)
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{
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{
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u32 tmp;
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u32 tmp;
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struct s5pc1xx_smc *srom =
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struct s5p_sromc *srom =
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(struct s5pc1xx_smc *)samsung_get_base_sromc();
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(struct s5p_sromc *)samsung_get_base_sromc();
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/* Configure SMC_BW register to handle proper SROMC bank */
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/* Configure SMC_BW register to handle proper SROMC bank */
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tmp = srom->bw;
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tmp = srom->bw;
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tmp &= ~(0xF << (srom_bank * 4));
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tmp &= ~(0xF << (srom_bank * 4));
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tmp |= smc_bw_conf;
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tmp |= srom_bw_conf;
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srom->bw = tmp;
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srom->bw = tmp;
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/* Configure SMC_BC register */
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/* Configure SMC_BC register */
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srom->bc[srom_bank] = smc_bc_conf;
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srom->bc[srom_bank] = srom_bc_conf;
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}
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}
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@ -32,7 +32,6 @@ SOBJS = cache.o
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SOBJS += reset.o
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SOBJS += reset.o
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COBJS += clock.o
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COBJS += clock.o
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COBJS += sromc.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
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OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
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@ -23,8 +23,8 @@
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* Only SROMC is defined as of now
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* Only SROMC is defined as of now
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*/
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*/
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#ifndef __ASM_ARCH_SMC_H_
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#ifndef __ASM_ARCH_SROMC_H_
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#define __ASM_ARCH_SMC_H_
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#define __ASM_ARCH_SROMC_H_
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#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0))
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#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0))
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#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
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#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
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@ -41,13 +41,13 @@
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#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
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#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLY__
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struct s5pc1xx_smc {
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struct s5p_sromc {
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unsigned int bw;
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unsigned int bw;
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unsigned int bc[6];
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unsigned int bc[6];
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};
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __ASSEMBLY__ */
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/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
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/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
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void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf);
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void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
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#endif /* __ASM_ARCH_SMC_H_ */
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#endif /* __ASM_ARCH_SMC_H_ */
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51
arch/arm/include/asm/arch-s5pc2xx/sromc.h
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51
arch/arm/include/asm/arch-s5pc2xx/sromc.h
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@ -0,0 +1,51 @@
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/*
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* (C) Copyright 2010 Samsung Electronics
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* Naveen Krishna Ch <ch.naveen@samsung.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Note: This file contains the register description for SROMC
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*
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*/
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#ifndef __ASM_ARCH_SROMC_H_
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#define __ASM_ARCH_SROMC_H_
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#define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0))
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#define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
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/* 1-> Byte base address*/
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#define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2))
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#define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3))
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#define SROMC_BC_TACS(x) (x << 28) /* address set-up */
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#define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */
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#define SROMC_BC_TACC(x) (x << 16) /* access cycle */
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#define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */
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#define SROMC_BC_TAH(x) (x << 8) /* address holding time */
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#define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */
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#define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
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#ifndef __ASSEMBLY__
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struct s5p_sromc {
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unsigned int bw;
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unsigned int bc[4];
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};
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#endif /* __ASSEMBLY__ */
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/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
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void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
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#endif /* __ASM_ARCH_SROMC_H_ */
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@ -24,7 +24,7 @@
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#include <common.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/arch/smc.h>
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#include <asm/arch/sromc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/gpio.h>
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#include <netdev.h>
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#include <netdev.h>
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@ -50,7 +50,7 @@ static void smc9115_pre_init(void)
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| SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0);
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| SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0);
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/* Select and configure the SROMC bank */
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/* Select and configure the SROMC bank */
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s5pc1xx_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
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s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
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}
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}
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int board_init(void)
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int board_init(void)
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