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omap: gpmc: 'nandecc sw' can use HAM1 or BCH8

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The 'nandecc sw' command selects a software-based error correction
algorithm.  By default, this is OMAP_ECC_HAM1_CODE_SW but some
platforms use OMAP_ECC_BCH8_CODE_HW_DETECTION_SW as their
software-based correction algorithm.  Allow a user to be specific e.g.
 # nandecc sw <hamming|bch8>
where 'hamming' is still the default.

Note: we don't just use CONFIG_NAND_OMAP_ECCSCHEME as it might be set
      to a hardware-based ECC scheme---a little strange when the user
      has requested 'sw' ECC.

Signed-off-by: Ash Charles <ashcharles@gmail.com>
This commit is contained in:
Ash Charles 2015-02-18 11:25:11 -08:00 committed by Tom Rini
parent d8af39337e
commit b050898efa
2 changed files with 21 additions and 2 deletions
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11
arch/arm/cpu/armv7/omap3/board.c
View File

@ -347,7 +347,16 @@ static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const arg
goto usage;
}
} else if (strncmp(argv[1], "sw", 2) == 0) {
omap_nand_switch_ecc(0, 0);
if (argc == 2) {
omap_nand_switch_ecc(0, 1);
} else {
if (strncmp(argv[2], "hamming", 7) == 0)
omap_nand_switch_ecc(0, 1);
else if (strncmp(argv[2], "bch8", 4) == 0)
omap_nand_switch_ecc(0, 8);
else
goto usage;
}
} else {
goto usage;
}

12
drivers/mtd/nand/omap_gpmc.c
View File

@ -912,8 +912,18 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
return -EINVAL;
}
} else {
err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
if (eccstrength == 1) {
err = omap_select_ecc_scheme(nand,
OMAP_ECC_HAM1_CODE_SW,
mtd->writesize, mtd->oobsize);
} else if (eccstrength == 8) {
err = omap_select_ecc_scheme(nand,
OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
mtd->writesize, mtd->oobsize);
} else {
printf("nand: error: unsupported ECC scheme\n");
return -EINVAL;
}
}
/* Update NAND handling after ECC mode switch */