phy: dphy: Add configuration helpers
The MIPI D-PHY spec defines default values and boundaries for most of the
parameters it defines. Introduce helpers to help drivers get meaningful
values based on their current parameters, and validate the boundaries of
these parameters if needed.
These helpers and header are taken from Linux commit 9123e3a74ec7 ("Linux 5.9-rc1").
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Neil Armstrong
parent
e14d5762de
commit
afef20585a
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@ -59,6 +59,11 @@ config SPL_NOP_PHY
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This is useful when a driver uses the PHY framework but no real PHY
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hardware exists.
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config MIPI_DPHY_HELPERS
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bool "MIPI D-PHY support helpers"
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help
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Provides a number of helpers a core functions for MIPI D-PHY drivers.
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config BCM6318_USBH_PHY
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bool "BCM6318 USBH PHY support"
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depends on PHY && ARCH_BMIPS
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@ -5,6 +5,7 @@
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obj-$(CONFIG_$(SPL_)PHY) += phy-uclass.o
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obj-$(CONFIG_$(SPL_)NOP_PHY) += nop-phy.o
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obj-$(CONFIG_MIPI_DPHY_HELPERS) += phy-core-mipi-dphy.o
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obj-$(CONFIG_BCM6318_USBH_PHY) += bcm6318-usbh-phy.o
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obj-$(CONFIG_BCM6348_USBH_PHY) += bcm6348-usbh-phy.o
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obj-$(CONFIG_BCM6358_USBH_PHY) += bcm6358-usbh-phy.o
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@ -0,0 +1,161 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2013 NVIDIA Corporation
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* Copyright (C) 2018 Cadence Design Systems Inc.
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*/
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#include <common.h>
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#include <div64.h>
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#include <phy-mipi-dphy.h>
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#define PSEC_PER_SEC 1000000000000LL
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/*
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* Minimum D-PHY timings based on MIPI D-PHY specification. Derived
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* from the valid ranges specified in Section 6.9, Table 14, Page 41
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* of the D-PHY specification (v2.1).
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*/
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int phy_mipi_dphy_get_default_config(unsigned long pixel_clock,
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unsigned int bpp,
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unsigned int lanes,
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struct phy_configure_opts_mipi_dphy *cfg)
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{
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unsigned long long hs_clk_rate;
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unsigned long long ui;
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if (!cfg)
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return -EINVAL;
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hs_clk_rate = pixel_clock * bpp;
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do_div(hs_clk_rate, lanes);
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ui = ALIGN(PSEC_PER_SEC, hs_clk_rate);
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do_div(ui, hs_clk_rate);
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cfg->clk_miss = 0;
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cfg->clk_post = 60000 + 52 * ui;
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cfg->clk_pre = 8000;
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cfg->clk_prepare = 38000;
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cfg->clk_settle = 95000;
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cfg->clk_term_en = 0;
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cfg->clk_trail = 60000;
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cfg->clk_zero = 262000;
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cfg->d_term_en = 0;
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cfg->eot = 0;
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cfg->hs_exit = 100000;
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cfg->hs_prepare = 40000 + 4 * ui;
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cfg->hs_zero = 105000 + 6 * ui;
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cfg->hs_settle = 85000 + 6 * ui;
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cfg->hs_skip = 40000;
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/*
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* The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40)
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* contains this formula as:
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*
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* T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui)
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*
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* where n = 1 for forward-direction HS mode and n = 4 for reverse-
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* direction HS mode. There's only one setting and this function does
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* not parameterize on anything other that ui, so this code will
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* assumes that reverse-direction HS mode is supported and uses n = 4.
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*/
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cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui);
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cfg->init = 100;
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cfg->lpx = 60000;
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cfg->ta_get = 5 * cfg->lpx;
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cfg->ta_go = 4 * cfg->lpx;
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cfg->ta_sure = 2 * cfg->lpx;
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cfg->wakeup = 1000;
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cfg->hs_clk_rate = hs_clk_rate;
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cfg->lanes = lanes;
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return 0;
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}
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/*
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* Validate D-PHY configuration according to MIPI D-PHY specification
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* (v1.2, Section Section 6.9 "Global Operation Timing Parameters").
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*/
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int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg)
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{
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unsigned long long ui;
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if (!cfg)
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return -EINVAL;
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ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate);
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do_div(ui, cfg->hs_clk_rate);
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if (cfg->clk_miss > 60000)
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return -EINVAL;
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if (cfg->clk_post < (60000 + 52 * ui))
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return -EINVAL;
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if (cfg->clk_pre < 8000)
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return -EINVAL;
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if (cfg->clk_prepare < 38000 || cfg->clk_prepare > 95000)
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return -EINVAL;
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if (cfg->clk_settle < 95000 || cfg->clk_settle > 300000)
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return -EINVAL;
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if (cfg->clk_term_en > 38000)
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return -EINVAL;
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if (cfg->clk_trail < 60000)
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return -EINVAL;
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if ((cfg->clk_prepare + cfg->clk_zero) < 300000)
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return -EINVAL;
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if (cfg->d_term_en > (35000 + 4 * ui))
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return -EINVAL;
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if (cfg->eot > (105000 + 12 * ui))
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return -EINVAL;
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if (cfg->hs_exit < 100000)
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return -EINVAL;
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if (cfg->hs_prepare < (40000 + 4 * ui) ||
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cfg->hs_prepare > (85000 + 6 * ui))
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return -EINVAL;
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if ((cfg->hs_prepare + cfg->hs_zero) < (145000 + 10 * ui))
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return -EINVAL;
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if ((cfg->hs_settle < (85000 + 6 * ui)) ||
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(cfg->hs_settle > (145000 + 10 * ui)))
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return -EINVAL;
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if (cfg->hs_skip < 40000 || cfg->hs_skip > (55000 + 4 * ui))
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return -EINVAL;
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if (cfg->hs_trail < max(8 * ui, 60000 + 4 * ui))
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return -EINVAL;
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if (cfg->init < 100)
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return -EINVAL;
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if (cfg->lpx < 50000)
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return -EINVAL;
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if (cfg->ta_get != (5 * cfg->lpx))
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return -EINVAL;
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if (cfg->ta_go != (4 * cfg->lpx))
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return -EINVAL;
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if (cfg->ta_sure < cfg->lpx || cfg->ta_sure > (2 * cfg->lpx))
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return -EINVAL;
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if (cfg->wakeup < 1000)
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return -EINVAL;
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return 0;
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}
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@ -0,0 +1,284 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 Cadence Design Systems Inc.
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*/
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#ifndef __PHY_MIPI_DPHY_H_
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#define __PHY_MIPI_DPHY_H_
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/**
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* struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
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*
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* This structure is used to represent the configuration state of a
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* MIPI D-PHY phy.
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*/
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struct phy_configure_opts_mipi_dphy {
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/**
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* @clk_miss:
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*
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* Timeout, in picoseconds, for receiver to detect absence of
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* Clock transitions and disable the Clock Lane HS-RX.
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*
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* Maximum value: 60000 ps
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*/
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unsigned int clk_miss;
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/**
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* @clk_post:
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*
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* Time, in picoseconds, that the transmitter continues to
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* send HS clock after the last associated Data Lane has
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* transitioned to LP Mode. Interval is defined as the period
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* from the end of @hs_trail to the beginning of @clk_trail.
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*
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* Minimum value: 60000 ps + 52 * @hs_clk_rate period in ps
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*/
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unsigned int clk_post;
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/**
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* @clk_pre:
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*
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* Time, in UI, that the HS clock shall be driven by
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* the transmitter prior to any associated Data Lane beginning
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* the transition from LP to HS mode.
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*
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* Minimum value: 8 UI
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*/
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unsigned int clk_pre;
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/**
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* @clk_prepare:
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*
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* Time, in picoseconds, that the transmitter drives the Clock
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* Lane LP-00 Line state immediately before the HS-0 Line
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* state starting the HS transmission.
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*
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* Minimum value: 38000 ps
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* Maximum value: 95000 ps
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*/
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unsigned int clk_prepare;
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/**
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* @clk_settle:
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*
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* Time interval, in picoseconds, during which the HS receiver
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* should ignore any Clock Lane HS transitions, starting from
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* the beginning of @clk_prepare.
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*
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* Minimum value: 95000 ps
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* Maximum value: 300000 ps
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*/
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unsigned int clk_settle;
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/**
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* @clk_term_en:
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*
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* Time, in picoseconds, for the Clock Lane receiver to enable
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* the HS line termination.
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*
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* Maximum value: 38000 ps
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*/
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unsigned int clk_term_en;
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/**
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* @clk_trail:
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*
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* Time, in picoseconds, that the transmitter drives the HS-0
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* state after the last payload clock bit of a HS transmission
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* burst.
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*
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* Minimum value: 60000 ps
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*/
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unsigned int clk_trail;
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/**
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* @clk_zero:
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*
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* Time, in picoseconds, that the transmitter drives the HS-0
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* state prior to starting the Clock.
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*/
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unsigned int clk_zero;
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/**
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* @d_term_en:
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*
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* Time, in picoseconds, for the Data Lane receiver to enable
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* the HS line termination.
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*
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* Maximum value: 35000 ps + 4 * @hs_clk_rate period in ps
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*/
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unsigned int d_term_en;
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/**
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* @eot:
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*
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* Transmitted time interval, in picoseconds, from the start
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* of @hs_trail or @clk_trail, to the start of the LP- 11
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* state following a HS burst.
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*
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* Maximum value: 105000 ps + 12 * @hs_clk_rate period in ps
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*/
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unsigned int eot;
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/**
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* @hs_exit:
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*
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* Time, in picoseconds, that the transmitter drives LP-11
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* following a HS burst.
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*
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* Minimum value: 100000 ps
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*/
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unsigned int hs_exit;
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/**
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* @hs_prepare:
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*
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* Time, in picoseconds, that the transmitter drives the Data
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* Lane LP-00 Line state immediately before the HS-0 Line
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* state starting the HS transmission.
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*
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* Minimum value: 40000 ps + 4 * @hs_clk_rate period in ps
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* Maximum value: 85000 ps + 6 * @hs_clk_rate period in ps
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*/
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unsigned int hs_prepare;
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/**
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* @hs_settle:
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*
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* Time interval, in picoseconds, during which the HS receiver
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* shall ignore any Data Lane HS transitions, starting from
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* the beginning of @hs_prepare.
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*
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* Minimum value: 85000 ps + 6 * @hs_clk_rate period in ps
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* Maximum value: 145000 ps + 10 * @hs_clk_rate period in ps
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*/
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unsigned int hs_settle;
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/**
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* @hs_skip:
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*
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* Time interval, in picoseconds, during which the HS-RX
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* should ignore any transitions on the Data Lane, following a
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* HS burst. The end point of the interval is defined as the
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* beginning of the LP-11 state following the HS burst.
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*
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* Minimum value: 40000 ps
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* Maximum value: 55000 ps + 4 * @hs_clk_rate period in ps
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*/
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unsigned int hs_skip;
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/**
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* @hs_trail:
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*
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* Time, in picoseconds, that the transmitter drives the
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* flipped differential state after last payload data bit of a
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* HS transmission burst
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*
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* Minimum value: max(8 * @hs_clk_rate period in ps,
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* 60000 ps + 4 * @hs_clk_rate period in ps)
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*/
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unsigned int hs_trail;
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/**
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* @hs_zero:
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*
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* Time, in picoseconds, that the transmitter drives the HS-0
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* state prior to transmitting the Sync sequence.
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*/
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unsigned int hs_zero;
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/**
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* @init:
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*
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* Time, in microseconds for the initialization period to
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* complete.
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*
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* Minimum value: 100 us
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*/
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unsigned int init;
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/**
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* @lpx:
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*
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* Transmitted length, in picoseconds, of any Low-Power state
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* period.
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*
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* Minimum value: 50000 ps
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*/
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unsigned int lpx;
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/**
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* @ta_get:
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*
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* Time, in picoseconds, that the new transmitter drives the
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* Bridge state (LP-00) after accepting control during a Link
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* Turnaround.
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*
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* Value: 5 * @lpx
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*/
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unsigned int ta_get;
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/**
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* @ta_go:
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*
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* Time, in picoseconds, that the transmitter drives the
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* Bridge state (LP-00) before releasing control during a Link
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* Turnaround.
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*
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* Value: 4 * @lpx
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*/
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unsigned int ta_go;
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/**
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* @ta_sure:
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*
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* Time, in picoseconds, that the new transmitter waits after
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* the LP-10 state before transmitting the Bridge state
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* (LP-00) during a Link Turnaround.
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*
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* Minimum value: @lpx
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* Maximum value: 2 * @lpx
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*/
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unsigned int ta_sure;
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/**
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* @wakeup:
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*
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* Time, in microseconds, that a transmitter drives a Mark-1
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* state prior to a Stop state in order to initiate an exit
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* from ULPS.
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*
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* Minimum value: 1000 us
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*/
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unsigned int wakeup;
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/**
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* @hs_clk_rate:
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*
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* Clock rate, in Hertz, of the high-speed clock.
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*/
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unsigned long hs_clk_rate;
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/**
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* @lp_clk_rate:
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*
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* Clock rate, in Hertz, of the low-power clock.
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*/
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unsigned long lp_clk_rate;
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/**
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* @lanes:
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*
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* Number of active, consecutive, data lanes, starting from
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* lane 0, used for the transmissions.
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*/
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unsigned char lanes;
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};
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int phy_mipi_dphy_get_default_config(unsigned long pixel_clock,
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unsigned int bpp,
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unsigned int lanes,
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struct phy_configure_opts_mipi_dphy *cfg);
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int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg);
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#endif /* __PHY_MIPI_DPHY_H_ */
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