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colibri_vf: use leveling evaluated by DDR validation tools

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The DDR validation tool (which is part of Processor Expert) allows
to evaluate leveling parameters for CR105/CR106/CR110. Several
runs have been made with Colibri VF50 and VF61 and it seems to
evaluate very similar values. Use this values by default.

Note: The newly evaluated parameters seem to require CTLUPD_AREF
to be enabled!

Note 2: The tool also evaluated 6 as a new value for PHY02/18
GATE_CFG (Coarse adjust of gate open time). However, this seems
not to work in practise.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This commit is contained in:
Stefan Agner 2019-03-25 17:25:11 +01:00 committed by Stefano Babic
parent be24fc7807
commit afda2ace8a
1 changed files with 7 additions and 0 deletions
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7
board/toradex/colibri_vf/colibri_vf.c
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@ -29,6 +29,13 @@ DECLARE_GLOBAL_DATA_PTR;
#define PTC0_GPIO_45 45
static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
{ DDRMC_CR79_CTLUPD_AREF(1), 79 },
/* sets manual values for read lvl. (gate) delay of data slice 0/1 */
{ DDRMC_CR105_RDLVL_DL_0(28), 105 },
{ DDRMC_CR106_RDLVL_GTDL_0(24), 106 },
{ DDRMC_CR110_RDLVL_DL_1(28) | DDRMC_CR110_RDLVL_GTDL_1(24), 110 },
{ DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, 102 },
/* AXI */
{ DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
{ DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },