mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-29 16:10:24 +09:00
Merge branch '2020-10-22-misc-changes'
- Assorted updates for Xen, IPQ40xx, ASpeed, Keymile - Assorted typo / documentation fixes - Fix default preboot cmd to act like before with USB_STORAGE set - A number of other bugfixes throughout the code
This commit is contained in:
commit
ae4fdd7b04
@ -241,6 +241,9 @@ F: include/dt-bindings/clock/qcom,ipq4019-gcc.h
|
|||||||
F: include/dt-bindings/reset/qcom,ipq4019-reset.h
|
F: include/dt-bindings/reset/qcom,ipq4019-reset.h
|
||||||
F: drivers/reset/reset-ipq4019.c
|
F: drivers/reset/reset-ipq4019.c
|
||||||
F: drivers/phy/phy-qcom-ipq4019-usb.c
|
F: drivers/phy/phy-qcom-ipq4019-usb.c
|
||||||
|
F: drivers/spi/spi-qup.c
|
||||||
|
F: drivers/net/mdio-ipq4019.c
|
||||||
|
F: drivers/rng/msm_rng.c
|
||||||
|
|
||||||
ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
|
ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
|
||||||
M: Stefan Roese <sr@denx.de>
|
M: Stefan Roese <sr@denx.de>
|
||||||
|
4
Makefile
4
Makefile
@ -860,13 +860,13 @@ else
|
|||||||
BOARD_SIZE_CHECK =
|
BOARD_SIZE_CHECK =
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifneq ($(CONFIG_SPL_SIZE_LIMIT),0)
|
ifneq ($(CONFIG_SPL_SIZE_LIMIT),0x0)
|
||||||
SPL_SIZE_CHECK = @$(call size_check,$@,$$(tools/spl_size_limit))
|
SPL_SIZE_CHECK = @$(call size_check,$@,$$(tools/spl_size_limit))
|
||||||
else
|
else
|
||||||
SPL_SIZE_CHECK =
|
SPL_SIZE_CHECK =
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifneq ($(CONFIG_TPL_SIZE_LIMIT),0)
|
ifneq ($(CONFIG_TPL_SIZE_LIMIT),0x0)
|
||||||
TPL_SIZE_CHECK = @$(call size_check,$@,$(CONFIG_TPL_SIZE_LIMIT))
|
TPL_SIZE_CHECK = @$(call size_check,$@,$(CONFIG_TPL_SIZE_LIMIT))
|
||||||
else
|
else
|
||||||
TPL_SIZE_CHECK =
|
TPL_SIZE_CHECK =
|
||||||
|
46
README
46
README
@ -51,31 +51,28 @@ In case you have questions about, problems with or contributions for
|
|||||||
U-Boot, you should send a message to the U-Boot mailing list at
|
U-Boot, you should send a message to the U-Boot mailing list at
|
||||||
<u-boot@lists.denx.de>. There is also an archive of previous traffic
|
<u-boot@lists.denx.de>. There is also an archive of previous traffic
|
||||||
on the mailing list - please search the archive before asking FAQ's.
|
on the mailing list - please search the archive before asking FAQ's.
|
||||||
Please see http://lists.denx.de/pipermail/u-boot and
|
Please see https://lists.denx.de/pipermail/u-boot and
|
||||||
http://dir.gmane.org/gmane.comp.boot-loaders.u-boot
|
https://marc.info/?l=u-boot
|
||||||
|
|
||||||
|
|
||||||
Where to get source code:
|
Where to get source code:
|
||||||
=========================
|
=========================
|
||||||
|
|
||||||
The U-Boot source code is maintained in the Git repository at
|
The U-Boot source code is maintained in the Git repository at
|
||||||
git://www.denx.de/git/u-boot.git ; you can browse it online at
|
https://gitlab.denx.de/u-boot/u-boot.git ; you can browse it online at
|
||||||
http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=summary
|
https://gitlab.denx.de/u-boot/u-boot
|
||||||
|
|
||||||
The "snapshot" links on this page allow you to download tarballs of
|
The "Tags" links on this page allow you to download tarballs of
|
||||||
any version you might be interested in. Official releases are also
|
any version you might be interested in. Official releases are also
|
||||||
available for FTP download from the ftp://ftp.denx.de/pub/u-boot/
|
available from the DENX file server through HTTPS or FTP.
|
||||||
directory.
|
https://ftp.denx.de/pub/u-boot/
|
||||||
|
ftp://ftp.denx.de/pub/u-boot/
|
||||||
Pre-built (and tested) images are available from
|
|
||||||
ftp://ftp.denx.de/pub/u-boot/images/
|
|
||||||
|
|
||||||
|
|
||||||
Where we come from:
|
Where we come from:
|
||||||
===================
|
===================
|
||||||
|
|
||||||
- start from 8xxrom sources
|
- start from 8xxrom sources
|
||||||
- create PPCBoot project (http://sourceforge.net/projects/ppcboot)
|
- create PPCBoot project (https://sourceforge.net/projects/ppcboot)
|
||||||
- clean up code
|
- clean up code
|
||||||
- make it easier to add custom boards
|
- make it easier to add custom boards
|
||||||
- make it possible to add other [PowerPC] CPUs
|
- make it possible to add other [PowerPC] CPUs
|
||||||
@ -84,10 +81,10 @@ Where we come from:
|
|||||||
* S-Record download
|
* S-Record download
|
||||||
* network boot
|
* network boot
|
||||||
* ATA disk / SCSI ... boot
|
* ATA disk / SCSI ... boot
|
||||||
- create ARMBoot project (http://sourceforge.net/projects/armboot)
|
- create ARMBoot project (https://sourceforge.net/projects/armboot)
|
||||||
- add other CPU families (starting with ARM)
|
- add other CPU families (starting with ARM)
|
||||||
- create U-Boot project (http://sourceforge.net/projects/u-boot)
|
- create U-Boot project (https://sourceforge.net/projects/u-boot)
|
||||||
- current project page: see http://www.denx.de/wiki/U-Boot
|
- current project page: see https://www.denx.de/wiki/U-Boot
|
||||||
|
|
||||||
|
|
||||||
Names and Spelling:
|
Names and Spelling:
|
||||||
@ -139,12 +136,12 @@ Directory Hierarchy:
|
|||||||
/mips Files generic to MIPS architecture
|
/mips Files generic to MIPS architecture
|
||||||
/nds32 Files generic to NDS32 architecture
|
/nds32 Files generic to NDS32 architecture
|
||||||
/nios2 Files generic to Altera NIOS2 architecture
|
/nios2 Files generic to Altera NIOS2 architecture
|
||||||
/openrisc Files generic to OpenRISC architecture
|
|
||||||
/powerpc Files generic to PowerPC architecture
|
/powerpc Files generic to PowerPC architecture
|
||||||
/riscv Files generic to RISC-V architecture
|
/riscv Files generic to RISC-V architecture
|
||||||
/sandbox Files generic to HW-independent "sandbox"
|
/sandbox Files generic to HW-independent "sandbox"
|
||||||
/sh Files generic to SH architecture
|
/sh Files generic to SH architecture
|
||||||
/x86 Files generic to x86 architecture
|
/x86 Files generic to x86 architecture
|
||||||
|
/xtensa Files generic to Xtensa architecture
|
||||||
/api Machine/arch independent API for external apps
|
/api Machine/arch independent API for external apps
|
||||||
/board Board dependent files
|
/board Board dependent files
|
||||||
/cmd U-Boot commands functions
|
/cmd U-Boot commands functions
|
||||||
@ -154,6 +151,7 @@ Directory Hierarchy:
|
|||||||
/doc Documentation (don't expect too much)
|
/doc Documentation (don't expect too much)
|
||||||
/drivers Commonly used device drivers
|
/drivers Commonly used device drivers
|
||||||
/dts Contains Makefile for building internal U-Boot fdt.
|
/dts Contains Makefile for building internal U-Boot fdt.
|
||||||
|
/env Environment files
|
||||||
/examples Example code for standalone applications, etc.
|
/examples Example code for standalone applications, etc.
|
||||||
/fs Filesystem code (cramfs, ext2, jffs2, etc.)
|
/fs Filesystem code (cramfs, ext2, jffs2, etc.)
|
||||||
/include Header Files
|
/include Header Files
|
||||||
@ -212,7 +210,7 @@ board. This allows feature development which is not board- or architecture-
|
|||||||
specific to be undertaken on a native platform. The sandbox is also used to
|
specific to be undertaken on a native platform. The sandbox is also used to
|
||||||
run some of U-Boot's tests.
|
run some of U-Boot's tests.
|
||||||
|
|
||||||
See doc/arch/index.rst for more details.
|
See doc/arch/sandbox.rst for more details.
|
||||||
|
|
||||||
|
|
||||||
Board Initialisation Flow:
|
Board Initialisation Flow:
|
||||||
@ -608,7 +606,7 @@ The following options need to be configured:
|
|||||||
This setting is mandatory for all boards that have only one
|
This setting is mandatory for all boards that have only one
|
||||||
machine type and must be used to specify the machine type
|
machine type and must be used to specify the machine type
|
||||||
number as it appears in the ARM machine registry
|
number as it appears in the ARM machine registry
|
||||||
(see http://www.arm.linux.org.uk/developer/machines/).
|
(see https://www.arm.linux.org.uk/developer/machines/).
|
||||||
Only boards that have multiple machine types supported
|
Only boards that have multiple machine types supported
|
||||||
in a single configuration file and the machine type is
|
in a single configuration file and the machine type is
|
||||||
runtime discoverable, do not have to use this setting.
|
runtime discoverable, do not have to use this setting.
|
||||||
@ -620,7 +618,7 @@ The following options need to be configured:
|
|||||||
serverip, gatewayip, hostname, othbootargs.
|
serverip, gatewayip, hostname, othbootargs.
|
||||||
It loads the vxWorks image pointed bootfile.
|
It loads the vxWorks image pointed bootfile.
|
||||||
|
|
||||||
Note: If a "bootargs" environment is defined, it will overwride
|
Note: If a "bootargs" environment is defined, it will override
|
||||||
the defaults discussed just above.
|
the defaults discussed just above.
|
||||||
|
|
||||||
- Cache Configuration:
|
- Cache Configuration:
|
||||||
@ -3021,7 +3019,7 @@ Building U-Boot has been tested in several native build environments
|
|||||||
and in many different cross environments. Of course we cannot support
|
and in many different cross environments. Of course we cannot support
|
||||||
all possibly existing versions of cross development tools in all
|
all possibly existing versions of cross development tools in all
|
||||||
(potentially obsolete) versions. In case of tool chain problems we
|
(potentially obsolete) versions. In case of tool chain problems we
|
||||||
recommend to use the ELDK (see http://www.denx.de/wiki/DULG/ELDK)
|
recommend to use the ELDK (see https://www.denx.de/wiki/DULG/ELDK)
|
||||||
which is extensively used to build and test U-Boot.
|
which is extensively used to build and test U-Boot.
|
||||||
|
|
||||||
If you are not using a native environment, it is assumed that you
|
If you are not using a native environment, it is assumed that you
|
||||||
@ -4175,7 +4173,7 @@ consider minicom to be broken, and recommend not to use it. Under
|
|||||||
Unix, I recommend to use C-Kermit for general purpose use (and
|
Unix, I recommend to use C-Kermit for general purpose use (and
|
||||||
especially for kermit binary protocol download ("loadb" command), and
|
especially for kermit binary protocol download ("loadb" command), and
|
||||||
use "cu" for S-Record download ("loads" command). See
|
use "cu" for S-Record download ("loads" command). See
|
||||||
http://www.denx.de/wiki/view/DULG/SystemSetup#Section_4.3.
|
https://www.denx.de/wiki/view/DULG/SystemSetup#Section_4.3.
|
||||||
for help with kermit.
|
for help with kermit.
|
||||||
|
|
||||||
|
|
||||||
@ -4343,7 +4341,7 @@ On ARM, the following registers are used:
|
|||||||
Note: on ARM, only R_ARM_RELATIVE relocations are supported.
|
Note: on ARM, only R_ARM_RELATIVE relocations are supported.
|
||||||
|
|
||||||
On Nios II, the ABI is documented here:
|
On Nios II, the ABI is documented here:
|
||||||
http://www.altera.com/literature/hb/nios2/n2cpu_nii51016.pdf
|
https://www.altera.com/literature/hb/nios2/n2cpu_nii51016.pdf
|
||||||
|
|
||||||
==> U-Boot will use gp to hold a pointer to the global data
|
==> U-Boot will use gp to hold a pointer to the global data
|
||||||
|
|
||||||
@ -4494,7 +4492,7 @@ int main(int argc, char *argv[])
|
|||||||
|
|
||||||
while (learning) {
|
while (learning) {
|
||||||
Read the README file in the top level directory;
|
Read the README file in the top level directory;
|
||||||
Read http://www.denx.de/twiki/bin/view/DULG/Manual;
|
Read https://www.denx.de/wiki/bin/view/DULG/Manual;
|
||||||
Read applicable doc/README.*;
|
Read applicable doc/README.*;
|
||||||
Read the source, Luke;
|
Read the source, Luke;
|
||||||
/* find . -name "*.[chS]" | xargs grep -i <keyword> */
|
/* find . -name "*.[chS]" | xargs grep -i <keyword> */
|
||||||
@ -4575,7 +4573,7 @@ Since the number of patches for U-Boot is growing, we need to
|
|||||||
establish some rules. Submissions which do not conform to these rules
|
establish some rules. Submissions which do not conform to these rules
|
||||||
may be rejected, even when they contain important and valuable stuff.
|
may be rejected, even when they contain important and valuable stuff.
|
||||||
|
|
||||||
Please see http://www.denx.de/wiki/U-Boot/Patches for details.
|
Please see https://www.denx.de/wiki/U-Boot/Patches for details.
|
||||||
|
|
||||||
Patches shall be sent to the u-boot mailing list <u-boot@lists.denx.de>;
|
Patches shall be sent to the u-boot mailing list <u-boot@lists.denx.de>;
|
||||||
see https://lists.denx.de/listinfo/u-boot
|
see https://lists.denx.de/listinfo/u-boot
|
||||||
|
@ -57,7 +57,7 @@ static int API_getc(va_list ap)
|
|||||||
if ((c = (int *)va_arg(ap, uintptr_t)) == NULL)
|
if ((c = (int *)va_arg(ap, uintptr_t)) == NULL)
|
||||||
return API_EINVAL;
|
return API_EINVAL;
|
||||||
|
|
||||||
*c = getc();
|
*c = getchar();
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -16,7 +16,6 @@
|
|||||||
rst: reset-controller {
|
rst: reset-controller {
|
||||||
u-boot,dm-pre-reloc;
|
u-boot,dm-pre-reloc;
|
||||||
compatible = "aspeed,ast2500-reset";
|
compatible = "aspeed,ast2500-reset";
|
||||||
aspeed,wdt = <&wdt1>;
|
|
||||||
#reset-cells = <1>;
|
#reset-cells = <1>;
|
||||||
};
|
};
|
||||||
|
|
||||||
@ -27,7 +26,7 @@
|
|||||||
0x1e6e0200 0x1d4 >;
|
0x1e6e0200 0x1d4 >;
|
||||||
#reset-cells = <1>;
|
#reset-cells = <1>;
|
||||||
clocks = <&scu ASPEED_CLK_MPLL>;
|
clocks = <&scu ASPEED_CLK_MPLL>;
|
||||||
resets = <&rst AST_RESET_SDRAM>;
|
resets = <&rst ASPEED_RESET_SDRAM>;
|
||||||
};
|
};
|
||||||
|
|
||||||
ahb {
|
ahb {
|
||||||
@ -41,7 +40,7 @@
|
|||||||
reg = <0x1e740100>;
|
reg = <0x1e740100>;
|
||||||
#reset-cells = <1>;
|
#reset-cells = <1>;
|
||||||
clocks = <&scu ASPEED_CLK_SDIO>;
|
clocks = <&scu ASPEED_CLK_SDIO>;
|
||||||
resets = <&rst AST_RESET_SDIO>;
|
resets = <&rst ASPEED_RESET_SDIO>;
|
||||||
};
|
};
|
||||||
|
|
||||||
sdhci1: sdhci@1e740200 {
|
sdhci1: sdhci@1e740200 {
|
||||||
@ -49,7 +48,7 @@
|
|||||||
reg = <0x1e740200>;
|
reg = <0x1e740200>;
|
||||||
#reset-cells = <1>;
|
#reset-cells = <1>;
|
||||||
clocks = <&scu ASPEED_CLK_SDIO>;
|
clocks = <&scu ASPEED_CLK_SDIO>;
|
||||||
resets = <&rst AST_RESET_SDIO>;
|
resets = <&rst ASPEED_RESET_SDIO>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -22,6 +22,7 @@
|
|||||||
|
|
||||||
aliases {
|
aliases {
|
||||||
serial0 = &blsp1_uart1;
|
serial0 = &blsp1_uart1;
|
||||||
|
spi0 = &blsp1_spi1;
|
||||||
};
|
};
|
||||||
|
|
||||||
reserved-memory {
|
reserved-memory {
|
||||||
@ -59,6 +60,13 @@
|
|||||||
u-boot,dm-pre-reloc;
|
u-boot,dm-pre-reloc;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
rng: rng@22000 {
|
||||||
|
compatible = "qcom,prng";
|
||||||
|
reg = <0x22000 0x140>;
|
||||||
|
clocks = <&gcc GCC_PRNG_AHB_CLK>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
reset: gcc-reset@1800000 {
|
reset: gcc-reset@1800000 {
|
||||||
compatible = "qcom,gcc-reset-ipq4019";
|
compatible = "qcom,gcc-reset-ipq4019";
|
||||||
reg = <0x1800000 0x60000>;
|
reg = <0x1800000 0x60000>;
|
||||||
@ -89,6 +97,45 @@
|
|||||||
gpio-count = <100>;
|
gpio-count = <100>;
|
||||||
gpio-bank-name="soc";
|
gpio-bank-name="soc";
|
||||||
#gpio-cells = <2>;
|
#gpio-cells = <2>;
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
|
||||||
|
blsp1_spi1: spi@78b5000 {
|
||||||
|
compatible = "qcom,spi-qup-v2.2.1";
|
||||||
|
reg = <0x78b5000 0x600>;
|
||||||
|
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
|
||||||
|
mdio: mdio@90000 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
compatible = "qcom,ipq4019-mdio";
|
||||||
|
reg = <0x90000 0x64>;
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
ethphy0: ethernet-phy@0 {
|
||||||
|
reg = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ethphy1: ethernet-phy@1 {
|
||||||
|
reg = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ethphy2: ethernet-phy@2 {
|
||||||
|
reg = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ethphy3: ethernet-phy@3 {
|
||||||
|
reg = <3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ethphy4: ethernet-phy@4 {
|
||||||
|
reg = <4>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
usb3_ss_phy: ssphy@9a000 {
|
usb3_ss_phy: ssphy@9a000 {
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* Copyright (C) 2016-2020 ABB
|
* Copyright (C) 2016-2020 Hitachi Power Grids
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "socfpga_arria5.dtsi"
|
#include "socfpga_arria5.dtsi"
|
||||||
@ -8,7 +8,7 @@
|
|||||||
#include <dt-bindings/gpio/gpio.h>
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
model = "ABB SoC SECU1 Board";
|
model = "Hitachi PG SoC SECU1 Board";
|
||||||
compatible = "altr,socfpga-secu1", "altr,socfpga";
|
compatible = "altr,socfpga-secu1", "altr,socfpga";
|
||||||
|
|
||||||
chosen {
|
chosen {
|
||||||
|
@ -19,4 +19,10 @@ int HYPERVISOR_sched_op(int cmd, void *arg);
|
|||||||
int HYPERVISOR_event_channel_op(int cmd, void *arg);
|
int HYPERVISOR_event_channel_op(int cmd, void *arg);
|
||||||
unsigned long HYPERVISOR_hvm_op(int op, void *arg);
|
unsigned long HYPERVISOR_hvm_op(int op, void *arg);
|
||||||
int HYPERVISOR_memory_op(unsigned int cmd, void *arg);
|
int HYPERVISOR_memory_op(unsigned int cmd, void *arg);
|
||||||
|
|
||||||
|
static inline void xen_debug_putc(int c)
|
||||||
|
{
|
||||||
|
register int v __asm__ ("x0") = c;
|
||||||
|
__asm__ __volatile__("hvc 0xfffe" : "=r" (v) : "0" (v));
|
||||||
|
}
|
||||||
#endif /* _ASM_ARM_XEN_HYPERCALL_H */
|
#endif /* _ASM_ARM_XEN_HYPERCALL_H */
|
||||||
|
@ -2,7 +2,7 @@
|
|||||||
/*
|
/*
|
||||||
* Clock drivers for Qualcomm IPQ40xx
|
* Clock drivers for Qualcomm IPQ40xx
|
||||||
*
|
*
|
||||||
* Copyright (c) 2019 Sartura Ltd.
|
* Copyright (c) 2020 Sartura Ltd.
|
||||||
*
|
*
|
||||||
* Author: Robert Marko <robert.marko@sartura.hr>
|
* Author: Robert Marko <robert.marko@sartura.hr>
|
||||||
*
|
*
|
||||||
@ -47,8 +47,25 @@ static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
|
|||||||
return msm_set_rate(clk, rate);
|
return msm_set_rate(clk, rate);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int msm_enable(struct clk *clk)
|
||||||
|
{
|
||||||
|
switch (clk->id) {
|
||||||
|
case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/
|
||||||
|
/* This clock is already initialized by SBL1 */
|
||||||
|
return 0;
|
||||||
|
break;
|
||||||
|
case GCC_PRNG_AHB_CLK: /*PRNG*/
|
||||||
|
/* This clock is already initialized by SBL1 */
|
||||||
|
return 0;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
static struct clk_ops msm_clk_ops = {
|
static struct clk_ops msm_clk_ops = {
|
||||||
.set_rate = msm_clk_set_rate,
|
.set_rate = msm_clk_set_rate,
|
||||||
|
.enable = msm_enable,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct udevice_id msm_clk_ids[] = {
|
static const struct udevice_id msm_clk_ids[] = {
|
||||||
|
@ -18,6 +18,13 @@ static const struct pinctrl_function msm_pinctrl_functions[] = {
|
|||||||
{"blsp_uart0_0", 1}, /* Only for GPIO:16,17 */
|
{"blsp_uart0_0", 1}, /* Only for GPIO:16,17 */
|
||||||
{"blsp_uart0_1", 2}, /* Only for GPIO:60,61 */
|
{"blsp_uart0_1", 2}, /* Only for GPIO:60,61 */
|
||||||
{"blsp_uart1", 1},
|
{"blsp_uart1", 1},
|
||||||
|
{"blsp_spi0_0", 1}, /* Only for GPIO:12,13,14,15 */
|
||||||
|
{"blsp_spi0_1", 2}, /* Only for GPIO:54,55,56,57 */
|
||||||
|
{"blsp_spi1", 2},
|
||||||
|
{"mdio_0", 1}, /* Only for GPIO6 */
|
||||||
|
{"mdio_1", 2}, /* Only for GPIO53 */
|
||||||
|
{"mdc_0", 1}, /* Only for GPIO7 */
|
||||||
|
{"mdc_1", 2}, /* Only for GPIO52 */
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *ipq4019_get_function_name(struct udevice *dev,
|
static const char *ipq4019_get_function_name(struct udevice *dev,
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* ABB PGGA 8309 U-Boot specific Device Tree Source parts
|
* Hitachi Power Grids 8309 U-Boot specific Device Tree Source parts
|
||||||
*
|
*
|
||||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||||
*
|
*
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* ABB PGGA 8321 U-Boot specific Device Tree Source parts
|
* Hitachi Power Grids 8321 U-Boot specific Device Tree Source parts
|
||||||
*
|
*
|
||||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||||
*
|
*
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* ABB PGGA km8321 common ports Device Tree Source
|
* Hitachi Power Grids km8321 common ports Device Tree Source
|
||||||
*
|
*
|
||||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||||
*
|
*
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* ABB PGGA km836x U-Boot specific Device Tree Source parts
|
* Hitachi Power Grids km836x U-Boot specific Device Tree Source parts
|
||||||
*
|
*
|
||||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||||
*
|
*
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* ABB PGGA km836x common ports Device Tree Source
|
* Hitachi Power Grids km836x common ports Device Tree Source
|
||||||
*
|
*
|
||||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||||
*
|
*
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* ABB PGGA kmcoge5ne U-Boot specific Device Tree Source parts
|
* Hitachi Power Grids kmcoge5ne U-Boot specific Device Tree Source parts
|
||||||
*
|
*
|
||||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||||
*
|
*
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* ABB PGGA KMCOGE5ne Device Tree Source
|
* Hitachi Power Grids KMCOGE5ne Device Tree Source
|
||||||
*
|
*
|
||||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||||
*
|
*
|
||||||
@ -12,7 +12,7 @@
|
|||||||
|
|
||||||
/ {
|
/ {
|
||||||
model = "kmcoge5ne";
|
model = "kmcoge5ne";
|
||||||
compatible = "ABB,kmcoge5ne";
|
compatible = "hitachi,kmcoge5ne";
|
||||||
|
|
||||||
aliases {
|
aliases {
|
||||||
ethernet0 = &enet_admin;
|
ethernet0 = &enet_admin;
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* ABB PGGA kmeter1 U-Boot specific Device Tree Source parts
|
* Hitachi Power Grids kmeter1 U-Boot specific Device Tree Source parts
|
||||||
*
|
*
|
||||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||||
*
|
*
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* ABB PGGA KMETER1 Device Tree Source
|
* Hitachi Power Grids KMETER1 Device Tree Source
|
||||||
*
|
*
|
||||||
* 2008-2011 DENX Software Engineering GmbH
|
* 2008-2011 DENX Software Engineering GmbH
|
||||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||||
@ -12,7 +12,7 @@
|
|||||||
|
|
||||||
/ {
|
/ {
|
||||||
model = "KMETER1";
|
model = "KMETER1";
|
||||||
compatible = "ABB,KMETER1";
|
compatible = "keymile,KMETER1";
|
||||||
|
|
||||||
aliases {
|
aliases {
|
||||||
ethernet0 = &enet_piggy2;
|
ethernet0 = &enet_piggy2;
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* ABB PGGA OPTI2 Device Tree Source
|
* Hitachi Power Grids OPTI2 Device Tree Source
|
||||||
*
|
*
|
||||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||||
*
|
*
|
||||||
@ -12,7 +12,7 @@
|
|||||||
|
|
||||||
/ {
|
/ {
|
||||||
model = "KMOPTI2";
|
model = "KMOPTI2";
|
||||||
compatible = "ABB,kmpbec8321";
|
compatible = "hitachi,kmpbec8321";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* ABB PGGA SUPC5 Device Tree Source
|
* Hitachi Power Grids SUPC5 Device Tree Source
|
||||||
*
|
*
|
||||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||||
*
|
*
|
||||||
@ -12,7 +12,7 @@
|
|||||||
|
|
||||||
/ {
|
/ {
|
||||||
model = "SUPC5";
|
model = "SUPC5";
|
||||||
compatible = "ABB,kmpbec8321";
|
compatible = "hitachi,kmpbec8321";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* ABB PGGA SUPM5 Device Tree Source
|
* Hitachi Power Grids SUPM5 Device Tree Source
|
||||||
*
|
*
|
||||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||||
*
|
*
|
||||||
@ -12,7 +12,7 @@
|
|||||||
|
|
||||||
/ {
|
/ {
|
||||||
model = "SUPM5";
|
model = "SUPM5";
|
||||||
compatible = "ABB,kmpbec8321";
|
compatible = "hitachi,kmpbec8321";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* ABB PGGA TEGR1 Device Tree Source
|
* Hitachi Power Grids TEGR1 Device Tree Source
|
||||||
*
|
*
|
||||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||||
*
|
*
|
||||||
@ -10,7 +10,7 @@
|
|||||||
|
|
||||||
/ {
|
/ {
|
||||||
model = "KMTEGR1";
|
model = "KMTEGR1";
|
||||||
compatible = "ABB,kmpbec8309";
|
compatible = "hitachi,kmpbec8309";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* ABB PGGA TEPR2 Device Tree Source
|
* Hitachi Power Grids TEPR2 Device Tree Source
|
||||||
*
|
*
|
||||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||||
*
|
*
|
||||||
@ -12,7 +12,7 @@
|
|||||||
|
|
||||||
/ {
|
/ {
|
||||||
model = "KMTEPR2";
|
model = "KMTEPR2";
|
||||||
compatible = "ABB,kmpbec8321";
|
compatible = "hitachi,kmpbec8321";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* ABB PGGA TUGE1 Device Tree Source
|
* Hitachi Power Grids TUGE1 Device Tree Source
|
||||||
*
|
*
|
||||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||||
*
|
*
|
||||||
@ -12,7 +12,7 @@
|
|||||||
|
|
||||||
/ {
|
/ {
|
||||||
model = "TUGE1";
|
model = "TUGE1";
|
||||||
compatible = "ABB,kmpbec8321";
|
compatible = "hitachi,kmpbec8321";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* ABB PGGA TUXA1 Device Tree Source
|
* Hitachi Power Grids TUXA1 Device Tree Source
|
||||||
*
|
*
|
||||||
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
|
||||||
*
|
*
|
||||||
@ -12,7 +12,7 @@
|
|||||||
|
|
||||||
/ {
|
/ {
|
||||||
model = "TUXA1";
|
model = "TUXA1";
|
||||||
compatible = "ABB,kmpbec8321";
|
compatible = "hitachi,kmpbec8321";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
@ -17,11 +17,9 @@
|
|||||||
/* mtime register */
|
/* mtime register */
|
||||||
#define MTIME_REG(base) ((ulong)(base))
|
#define MTIME_REG(base) ((ulong)(base))
|
||||||
|
|
||||||
static int andes_plmt_get_count(struct udevice *dev, u64 *count)
|
static u64 andes_plmt_get_count(struct udevice *dev)
|
||||||
{
|
{
|
||||||
*count = readq((void __iomem *)MTIME_REG(dev->priv));
|
return readq((void __iomem *)MTIME_REG(dev->priv));
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static const struct timer_ops andes_plmt_ops = {
|
static const struct timer_ops andes_plmt_ops = {
|
||||||
|
@ -62,11 +62,9 @@ int riscv_get_ipi(int hart, int *pending)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int sifive_clint_get_count(struct udevice *dev, u64 *count)
|
static u64 sifive_clint_get_count(struct udevice *dev)
|
||||||
{
|
{
|
||||||
*count = readq((void __iomem *)MTIME_REG(dev->priv));
|
return readq((void __iomem *)MTIME_REG(dev->priv));
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static const struct timer_ops sifive_clint_ops = {
|
static const struct timer_ops sifive_clint_ops = {
|
||||||
|
@ -37,26 +37,20 @@ config KM_RESERVED_PRAM
|
|||||||
|
|
||||||
config KM_CRAMFS_ADDR
|
config KM_CRAMFS_ADDR
|
||||||
hex "CRAMFS Address"
|
hex "CRAMFS Address"
|
||||||
default 0x2400000 if ARCH_KIRKWOOD
|
default 0x3000000
|
||||||
default 0xC00000 if MPC83xx
|
|
||||||
default 0x2000000 if MPC85xx
|
|
||||||
depends on !ARCH_SOCFPGA
|
depends on !ARCH_SOCFPGA
|
||||||
help
|
help
|
||||||
Start address of the CRAMFS containing the Linux kernel.
|
Start address of the CRAMFS containing the Linux kernel.
|
||||||
|
|
||||||
config KM_KERNEL_ADDR
|
config KM_KERNEL_ADDR
|
||||||
hex "Kernel Load Address"
|
hex "Kernel Load Address"
|
||||||
default 0x2000000 if ARCH_KIRKWOOD
|
default 0x2000000
|
||||||
default 0x400000 if MPC83xx
|
|
||||||
default 0x1000000 if MPC85xx || ARCH_SOCFPGA
|
|
||||||
help
|
help
|
||||||
Address where to load Linux kernel in RAM.
|
Address where to load Linux kernel in RAM.
|
||||||
|
|
||||||
config KM_FDT_ADDR
|
config KM_FDT_ADDR
|
||||||
hex "FDT Load Address"
|
hex "FDT Load Address"
|
||||||
default 0x23E0000 if ARCH_KIRKWOOD || ARCH_SOCFPGA
|
default 0x2FC0000
|
||||||
default 0xB80000 if MPC83xx
|
|
||||||
default 0x1F80000 if MPC85xx
|
|
||||||
help
|
help
|
||||||
Address where to load flattened device tree in RAM.
|
Address where to load flattened device tree in RAM.
|
||||||
|
|
||||||
|
@ -185,7 +185,7 @@ int dram_init(void)
|
|||||||
|
|
||||||
int checkboard(void)
|
int checkboard(void)
|
||||||
{
|
{
|
||||||
puts("Board: ABB " CONFIG_SYS_CONFIG_NAME);
|
puts("Board: Hitachi " CONFIG_SYS_CONFIG_NAME);
|
||||||
|
|
||||||
if (piggy_present())
|
if (piggy_present())
|
||||||
puts(" with PIGGY.");
|
puts(" with PIGGY.");
|
||||||
|
@ -1,4 +1,4 @@
|
|||||||
ABB SECU1 BOARD
|
Hitachi Power Grids SECU1 BOARD
|
||||||
M: Holger Brunck <holger.brunck@hitachi-powergrids.com>
|
M: Holger Brunck <holger.brunck@hitachi-powergrids.com>
|
||||||
S: Maintained
|
S: Maintained
|
||||||
F: include/configs/socfpga_arria5_secu1.h
|
F: include/configs/socfpga_arria5_secu1.h
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
#
|
#
|
||||||
# (C) Copyright 2020 ABB
|
# (C) Copyright 2020 Hitachi Power Grids
|
||||||
#
|
#
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
#
|
#
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0+
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
/*
|
/*
|
||||||
* Copyright (C) 2017-2020 ABB
|
* Copyright (C) 2017-2020 Hitachi Power Grids
|
||||||
*/
|
*/
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <i2c.h>
|
#include <i2c.h>
|
||||||
|
@ -99,7 +99,7 @@ static void bootmenu_autoboot_loop(struct bootmenu_data *menu,
|
|||||||
}
|
}
|
||||||
|
|
||||||
menu->delay = -1;
|
menu->delay = -1;
|
||||||
c = getc();
|
c = getchar();
|
||||||
|
|
||||||
switch (c) {
|
switch (c) {
|
||||||
case '\e':
|
case '\e':
|
||||||
@ -141,7 +141,7 @@ static void bootmenu_loop(struct bootmenu_data *menu,
|
|||||||
mdelay(10);
|
mdelay(10);
|
||||||
}
|
}
|
||||||
|
|
||||||
c = getc();
|
c = getchar();
|
||||||
|
|
||||||
switch (*esc) {
|
switch (*esc) {
|
||||||
case 0:
|
case 0:
|
||||||
|
44
cmd/load.c
44
cmd/load.c
@ -81,7 +81,7 @@ static int do_load_serial(struct cmd_tbl *cmdtp, int flag, int argc,
|
|||||||
serial_setbrg();
|
serial_setbrg();
|
||||||
udelay(50000);
|
udelay(50000);
|
||||||
for (;;) {
|
for (;;) {
|
||||||
if (getc() == '\r')
|
if (getchar() == '\r')
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -102,7 +102,7 @@ static int do_load_serial(struct cmd_tbl *cmdtp, int flag, int argc,
|
|||||||
*/
|
*/
|
||||||
for (i=0; i<100; ++i) {
|
for (i=0; i<100; ++i) {
|
||||||
if (tstc()) {
|
if (tstc()) {
|
||||||
(void) getc();
|
getchar();
|
||||||
}
|
}
|
||||||
udelay(1000);
|
udelay(1000);
|
||||||
}
|
}
|
||||||
@ -124,7 +124,7 @@ static int do_load_serial(struct cmd_tbl *cmdtp, int flag, int argc,
|
|||||||
serial_setbrg();
|
serial_setbrg();
|
||||||
udelay(50000);
|
udelay(50000);
|
||||||
for (;;) {
|
for (;;) {
|
||||||
if (getc() == 0x1B) /* ESC */
|
if (getchar() == 0x1B) /* ESC */
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -212,7 +212,7 @@ static int read_record(char *buf, ulong len)
|
|||||||
--len; /* always leave room for terminating '\0' byte */
|
--len; /* always leave room for terminating '\0' byte */
|
||||||
|
|
||||||
for (p=buf; p < buf+len; ++p) {
|
for (p=buf; p < buf+len; ++p) {
|
||||||
c = getc(); /* read character */
|
c = getchar(); /* read character */
|
||||||
if (do_echo)
|
if (do_echo)
|
||||||
putc(c); /* ... and echo it */
|
putc(c); /* ... and echo it */
|
||||||
|
|
||||||
@ -229,7 +229,7 @@ static int read_record(char *buf, ulong len)
|
|||||||
}
|
}
|
||||||
|
|
||||||
/* Check for the console hangup (if any different from serial) */
|
/* Check for the console hangup (if any different from serial) */
|
||||||
if (gd->jt->getc != getc) {
|
if (gd->jt->getc != getchar) {
|
||||||
if (ctrlc()) {
|
if (ctrlc()) {
|
||||||
return (-1);
|
return (-1);
|
||||||
}
|
}
|
||||||
@ -276,7 +276,7 @@ int do_save_serial(struct cmd_tbl *cmdtp, int flag, int argc,
|
|||||||
serial_setbrg();
|
serial_setbrg();
|
||||||
udelay(50000);
|
udelay(50000);
|
||||||
for (;;) {
|
for (;;) {
|
||||||
if (getc() == '\r')
|
if (getchar() == '\r')
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -288,7 +288,7 @@ int do_save_serial(struct cmd_tbl *cmdtp, int flag, int argc,
|
|||||||
|
|
||||||
printf("## Ready for S-Record upload, press ENTER to proceed ...\n");
|
printf("## Ready for S-Record upload, press ENTER to proceed ...\n");
|
||||||
for (;;) {
|
for (;;) {
|
||||||
if (getc() == '\r')
|
if (getchar() == '\r')
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
if (save_serial(offset, size)) {
|
if (save_serial(offset, size)) {
|
||||||
@ -305,7 +305,7 @@ int do_save_serial(struct cmd_tbl *cmdtp, int flag, int argc,
|
|||||||
serial_setbrg();
|
serial_setbrg();
|
||||||
udelay(50000);
|
udelay(50000);
|
||||||
for (;;) {
|
for (;;) {
|
||||||
if (getc() == 0x1B) /* ESC */
|
if (getchar() == 0x1B) /* ESC */
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -459,7 +459,7 @@ static int do_load_serial_bin(struct cmd_tbl *cmdtp, int flag, int argc,
|
|||||||
serial_setbrg();
|
serial_setbrg();
|
||||||
udelay(50000);
|
udelay(50000);
|
||||||
for (;;) {
|
for (;;) {
|
||||||
if (getc() == '\r')
|
if (getchar() == '\r')
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -505,7 +505,7 @@ static int do_load_serial_bin(struct cmd_tbl *cmdtp, int flag, int argc,
|
|||||||
serial_setbrg();
|
serial_setbrg();
|
||||||
udelay(50000);
|
udelay(50000);
|
||||||
for (;;) {
|
for (;;) {
|
||||||
if (getc() == 0x1B) /* ESC */
|
if (getchar() == 0x1B) /* ESC */
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -528,7 +528,7 @@ static ulong load_serial_bin(ulong offset)
|
|||||||
*/
|
*/
|
||||||
for (i=0; i<100; ++i) {
|
for (i=0; i<100; ++i) {
|
||||||
if (tstc()) {
|
if (tstc()) {
|
||||||
(void) getc();
|
getchar();
|
||||||
}
|
}
|
||||||
udelay(1000);
|
udelay(1000);
|
||||||
}
|
}
|
||||||
@ -831,7 +831,7 @@ static int k_recv(void)
|
|||||||
/* get a packet */
|
/* get a packet */
|
||||||
/* wait for the starting character or ^C */
|
/* wait for the starting character or ^C */
|
||||||
for (;;) {
|
for (;;) {
|
||||||
switch (getc ()) {
|
switch (getchar()) {
|
||||||
case START_CHAR: /* start packet */
|
case START_CHAR: /* start packet */
|
||||||
goto START;
|
goto START;
|
||||||
case ETX_CHAR: /* ^C waiting for packet */
|
case ETX_CHAR: /* ^C waiting for packet */
|
||||||
@ -843,13 +843,13 @@ static int k_recv(void)
|
|||||||
START:
|
START:
|
||||||
/* get length of packet */
|
/* get length of packet */
|
||||||
sum = 0;
|
sum = 0;
|
||||||
new_char = getc();
|
new_char = getchar();
|
||||||
if ((new_char & 0xE0) == 0)
|
if ((new_char & 0xE0) == 0)
|
||||||
goto packet_error;
|
goto packet_error;
|
||||||
sum += new_char & 0xff;
|
sum += new_char & 0xff;
|
||||||
length = untochar(new_char);
|
length = untochar(new_char);
|
||||||
/* get sequence number */
|
/* get sequence number */
|
||||||
new_char = getc();
|
new_char = getchar();
|
||||||
if ((new_char & 0xE0) == 0)
|
if ((new_char & 0xE0) == 0)
|
||||||
goto packet_error;
|
goto packet_error;
|
||||||
sum += new_char & 0xff;
|
sum += new_char & 0xff;
|
||||||
@ -876,7 +876,7 @@ START:
|
|||||||
/* END NEW CODE */
|
/* END NEW CODE */
|
||||||
|
|
||||||
/* get packet type */
|
/* get packet type */
|
||||||
new_char = getc();
|
new_char = getchar();
|
||||||
if ((new_char & 0xE0) == 0)
|
if ((new_char & 0xE0) == 0)
|
||||||
goto packet_error;
|
goto packet_error;
|
||||||
sum += new_char & 0xff;
|
sum += new_char & 0xff;
|
||||||
@ -886,19 +886,19 @@ START:
|
|||||||
if (length == -2) {
|
if (length == -2) {
|
||||||
/* (length byte was 0, decremented twice) */
|
/* (length byte was 0, decremented twice) */
|
||||||
/* get the two length bytes */
|
/* get the two length bytes */
|
||||||
new_char = getc();
|
new_char = getchar();
|
||||||
if ((new_char & 0xE0) == 0)
|
if ((new_char & 0xE0) == 0)
|
||||||
goto packet_error;
|
goto packet_error;
|
||||||
sum += new_char & 0xff;
|
sum += new_char & 0xff;
|
||||||
len_hi = untochar(new_char);
|
len_hi = untochar(new_char);
|
||||||
new_char = getc();
|
new_char = getchar();
|
||||||
if ((new_char & 0xE0) == 0)
|
if ((new_char & 0xE0) == 0)
|
||||||
goto packet_error;
|
goto packet_error;
|
||||||
sum += new_char & 0xff;
|
sum += new_char & 0xff;
|
||||||
len_lo = untochar(new_char);
|
len_lo = untochar(new_char);
|
||||||
length = len_hi * 95 + len_lo;
|
length = len_hi * 95 + len_lo;
|
||||||
/* check header checksum */
|
/* check header checksum */
|
||||||
new_char = getc();
|
new_char = getchar();
|
||||||
if ((new_char & 0xE0) == 0)
|
if ((new_char & 0xE0) == 0)
|
||||||
goto packet_error;
|
goto packet_error;
|
||||||
if (new_char != tochar((sum + ((sum >> 6) & 0x03)) & 0x3f))
|
if (new_char != tochar((sum + ((sum >> 6) & 0x03)) & 0x3f))
|
||||||
@ -908,7 +908,7 @@ START:
|
|||||||
}
|
}
|
||||||
/* bring in rest of packet */
|
/* bring in rest of packet */
|
||||||
while (length > 1) {
|
while (length > 1) {
|
||||||
new_char = getc();
|
new_char = getchar();
|
||||||
if ((new_char & 0xE0) == 0)
|
if ((new_char & 0xE0) == 0)
|
||||||
goto packet_error;
|
goto packet_error;
|
||||||
sum += new_char & 0xff;
|
sum += new_char & 0xff;
|
||||||
@ -925,13 +925,13 @@ START:
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
/* get and validate checksum character */
|
/* get and validate checksum character */
|
||||||
new_char = getc();
|
new_char = getchar();
|
||||||
if ((new_char & 0xE0) == 0)
|
if ((new_char & 0xE0) == 0)
|
||||||
goto packet_error;
|
goto packet_error;
|
||||||
if (new_char != tochar((sum + ((sum >> 6) & 0x03)) & 0x3f))
|
if (new_char != tochar((sum + ((sum >> 6) & 0x03)) & 0x3f))
|
||||||
goto packet_error;
|
goto packet_error;
|
||||||
/* get END_CHAR */
|
/* get END_CHAR */
|
||||||
new_char = getc();
|
new_char = getchar();
|
||||||
if (new_char != END_CHAR) {
|
if (new_char != END_CHAR) {
|
||||||
packet_error:
|
packet_error:
|
||||||
/* restore state machines */
|
/* restore state machines */
|
||||||
@ -955,7 +955,7 @@ START:
|
|||||||
|
|
||||||
static int getcxmodem(void) {
|
static int getcxmodem(void) {
|
||||||
if (tstc())
|
if (tstc())
|
||||||
return (getc());
|
return (getchar());
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
static ulong load_serial_ymodem(ulong offset, int mode)
|
static ulong load_serial_ymodem(ulong offset, int mode)
|
||||||
|
@ -880,7 +880,7 @@ config USE_PREBOOT
|
|||||||
config PREBOOT
|
config PREBOOT
|
||||||
string "preboot default value"
|
string "preboot default value"
|
||||||
depends on USE_PREBOOT && !USE_DEFAULT_ENV_FILE
|
depends on USE_PREBOOT && !USE_DEFAULT_ENV_FILE
|
||||||
default "usb start" if USB_KEYBOARD || USB_STORAGE
|
default "usb start" if USB_KEYBOARD
|
||||||
default ""
|
default ""
|
||||||
help
|
help
|
||||||
This is the default of "preboot" environment variable.
|
This is the default of "preboot" environment variable.
|
||||||
|
@ -117,7 +117,7 @@ static int passwd_abort_sha256(uint64_t etime)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
presskey[presskey_len++] = getc();
|
presskey[presskey_len++] = getchar();
|
||||||
|
|
||||||
/* Calculate sha256 upon each new char */
|
/* Calculate sha256 upon each new char */
|
||||||
hash_block(algo_name, (const void *)presskey,
|
hash_block(algo_name, (const void *)presskey,
|
||||||
@ -189,12 +189,12 @@ static int passwd_abort_key(uint64_t etime)
|
|||||||
do {
|
do {
|
||||||
if (tstc()) {
|
if (tstc()) {
|
||||||
if (presskey_len < presskey_max) {
|
if (presskey_len < presskey_max) {
|
||||||
presskey[presskey_len++] = getc();
|
presskey[presskey_len++] = getchar();
|
||||||
} else {
|
} else {
|
||||||
for (i = 0; i < presskey_max - 1; i++)
|
for (i = 0; i < presskey_max - 1; i++)
|
||||||
presskey[i] = presskey[i + 1];
|
presskey[i] = presskey[i + 1];
|
||||||
|
|
||||||
presskey[i] = getc();
|
presskey[i] = getchar();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -257,7 +257,7 @@ static int abortboot_single_key(int bootdelay)
|
|||||||
* Check if key already pressed
|
* Check if key already pressed
|
||||||
*/
|
*/
|
||||||
if (tstc()) { /* we got a key press */
|
if (tstc()) { /* we got a key press */
|
||||||
(void) getc(); /* consume input */
|
getchar(); /* consume input */
|
||||||
puts("\b\b\b 0");
|
puts("\b\b\b 0");
|
||||||
abort = 1; /* don't auto boot */
|
abort = 1; /* don't auto boot */
|
||||||
}
|
}
|
||||||
@ -272,7 +272,7 @@ static int abortboot_single_key(int bootdelay)
|
|||||||
|
|
||||||
abort = 1; /* don't auto boot */
|
abort = 1; /* don't auto boot */
|
||||||
bootdelay = 0; /* no more delay */
|
bootdelay = 0; /* no more delay */
|
||||||
key = getc(); /* consume input */
|
key = getchar();/* consume input */
|
||||||
if (IS_ENABLED(CONFIG_USE_AUTOBOOT_MENUKEY))
|
if (IS_ENABLED(CONFIG_USE_AUTOBOOT_MENUKEY))
|
||||||
menukey = key;
|
menukey = key;
|
||||||
break;
|
break;
|
||||||
@ -363,7 +363,8 @@ void autoboot_command(const char *s)
|
|||||||
{
|
{
|
||||||
debug("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
|
debug("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
|
||||||
|
|
||||||
if (stored_bootdelay != -1 && s && !abortboot(stored_bootdelay)) {
|
if (s && (stored_bootdelay == -2 ||
|
||||||
|
(stored_bootdelay != -1 && !abortboot(stored_bootdelay)))) {
|
||||||
bool lock;
|
bool lock;
|
||||||
int prev;
|
int prev;
|
||||||
|
|
||||||
|
@ -392,6 +392,8 @@ static int reserve_video(void)
|
|||||||
ret = video_reserve(&addr);
|
ret = video_reserve(&addr);
|
||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
return ret;
|
||||||
|
debug("Reserving %luk for video at: %08lx\n",
|
||||||
|
(unsigned long)gd->relocaddr - addr, addr);
|
||||||
gd->relocaddr = addr;
|
gd->relocaddr = addr;
|
||||||
#elif defined(CONFIG_LCD)
|
#elif defined(CONFIG_LCD)
|
||||||
# ifdef CONFIG_FB_ADDR
|
# ifdef CONFIG_FB_ADDR
|
||||||
@ -573,7 +575,9 @@ static int reserve_stacks(void)
|
|||||||
static int reserve_bloblist(void)
|
static int reserve_bloblist(void)
|
||||||
{
|
{
|
||||||
#ifdef CONFIG_BLOBLIST
|
#ifdef CONFIG_BLOBLIST
|
||||||
gd->start_addr_sp = reserve_stack_aligned(CONFIG_BLOBLIST_SIZE);
|
/* Align to a 4KB boundary for easier reading of addresses */
|
||||||
|
gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp - CONFIG_BLOBLIST_SIZE,
|
||||||
|
0x1000);
|
||||||
gd->new_bloblist = map_sysmem(gd->start_addr_sp, CONFIG_BLOBLIST_SIZE);
|
gd->new_bloblist = map_sysmem(gd->start_addr_sp, CONFIG_BLOBLIST_SIZE);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -2170,14 +2170,6 @@ int set_local_var(const char *s, int flg_export)
|
|||||||
|
|
||||||
name=strdup(s);
|
name=strdup(s);
|
||||||
|
|
||||||
#ifdef __U_BOOT__
|
|
||||||
if (env_get(name) != NULL) {
|
|
||||||
printf ("ERROR: "
|
|
||||||
"There is a global environment variable with the same name.\n");
|
|
||||||
free(name);
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
/* Assume when we enter this function that we are already in
|
/* Assume when we enter this function that we are already in
|
||||||
* NAME=VALUE format. So the first order of business is to
|
* NAME=VALUE format. So the first order of business is to
|
||||||
* split 's' on the '=' into 'name' and 'value' */
|
* split 's' on the '=' into 'name' and 'value' */
|
||||||
|
@ -68,7 +68,7 @@ static char *delete_char (char *buffer, char *p, int *colp, int *np, int plen)
|
|||||||
#define CREAD_HIST_CHAR ('!')
|
#define CREAD_HIST_CHAR ('!')
|
||||||
|
|
||||||
#define getcmd_putch(ch) putc(ch)
|
#define getcmd_putch(ch) putc(ch)
|
||||||
#define getcmd_getch() getc()
|
#define getcmd_getch() getchar()
|
||||||
#define getcmd_cbeep() getcmd_putch('\a')
|
#define getcmd_cbeep() getcmd_putch('\a')
|
||||||
|
|
||||||
#define HIST_MAX 20
|
#define HIST_MAX 20
|
||||||
@ -571,7 +571,7 @@ int cli_readline_into_buffer(const char *const prompt, char *buffer,
|
|||||||
return -2; /* timed out */
|
return -2; /* timed out */
|
||||||
WATCHDOG_RESET(); /* Trigger watchdog, if needed */
|
WATCHDOG_RESET(); /* Trigger watchdog, if needed */
|
||||||
|
|
||||||
c = getc();
|
c = getchar();
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Special character handling
|
* Special character handling
|
||||||
|
@ -131,7 +131,7 @@ static int console_setfile(int file, struct stdio_dev * dev)
|
|||||||
*/
|
*/
|
||||||
switch (file) {
|
switch (file) {
|
||||||
case stdin:
|
case stdin:
|
||||||
gd->jt->getc = getc;
|
gd->jt->getc = getchar;
|
||||||
gd->jt->tstc = tstc;
|
gd->jt->tstc = tstc;
|
||||||
break;
|
break;
|
||||||
case stdout:
|
case stdout:
|
||||||
@ -179,7 +179,7 @@ struct stdio_dev **console_devices[MAX_FILES];
|
|||||||
int cd_count[MAX_FILES];
|
int cd_count[MAX_FILES];
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* This depends on tstc() always being called before getc().
|
* This depends on tstc() always being called before getchar().
|
||||||
* This is guaranteed to be true because this routine is called
|
* This is guaranteed to be true because this routine is called
|
||||||
* only from fgetc() which assures it.
|
* only from fgetc() which assures it.
|
||||||
* No attempt is made to demultiplex multiple input sources.
|
* No attempt is made to demultiplex multiple input sources.
|
||||||
@ -404,7 +404,7 @@ int fprintf(int file, const char *fmt, ...)
|
|||||||
|
|
||||||
/** U-Boot INITIAL CONSOLE-COMPATIBLE FUNCTION *****************************/
|
/** U-Boot INITIAL CONSOLE-COMPATIBLE FUNCTION *****************************/
|
||||||
|
|
||||||
int getc(void)
|
int getchar(void)
|
||||||
{
|
{
|
||||||
#ifdef CONFIG_DISABLE_CONSOLE
|
#ifdef CONFIG_DISABLE_CONSOLE
|
||||||
if (gd->flags & GD_FLG_DISABLE_CONSOLE)
|
if (gd->flags & GD_FLG_DISABLE_CONSOLE)
|
||||||
@ -663,7 +663,7 @@ int ctrlc(void)
|
|||||||
{
|
{
|
||||||
if (!ctrlc_disabled && gd->have_console) {
|
if (!ctrlc_disabled && gd->have_console) {
|
||||||
if (tstc()) {
|
if (tstc()) {
|
||||||
switch (getc()) {
|
switch (getchar()) {
|
||||||
case 0x03: /* ^C - Control C */
|
case 0x03: /* ^C - Control C */
|
||||||
ctrlc_was_pressed = 1;
|
ctrlc_was_pressed = 1;
|
||||||
return 1;
|
return 1;
|
||||||
@ -685,10 +685,10 @@ int confirm_yesno(void)
|
|||||||
|
|
||||||
/* Flush input */
|
/* Flush input */
|
||||||
while (tstc())
|
while (tstc())
|
||||||
getc();
|
getchar();
|
||||||
i = 0;
|
i = 0;
|
||||||
while (i < sizeof(str_input)) {
|
while (i < sizeof(str_input)) {
|
||||||
str_input[i] = getc();
|
str_input[i] = getchar();
|
||||||
putc(str_input[i]);
|
putc(str_input[i]);
|
||||||
if (str_input[i] == '\r')
|
if (str_input[i] == '\r')
|
||||||
break;
|
break;
|
||||||
|
@ -801,14 +801,14 @@ static const char *unknown_msg(enum ih_category category)
|
|||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* get_cat_table_entry_name - translate entry id to long name
|
* genimg_get_cat_name - translate entry id to long name
|
||||||
* @category: category to look up (enum ih_category)
|
* @category: category to look up (enum ih_category)
|
||||||
* @id: entry id to be translated
|
* @id: entry id to be translated
|
||||||
*
|
*
|
||||||
* This will scan the translation table trying to find the entry that matches
|
* This will scan the translation table trying to find the entry that matches
|
||||||
* the given id.
|
* the given id.
|
||||||
*
|
*
|
||||||
* @retur long entry name if translation succeeds; error string on failure
|
* @return long entry name if translation succeeds; error string on failure
|
||||||
*/
|
*/
|
||||||
const char *genimg_get_cat_name(enum ih_category category, uint id)
|
const char *genimg_get_cat_name(enum ih_category category, uint id)
|
||||||
{
|
{
|
||||||
@ -825,14 +825,14 @@ const char *genimg_get_cat_name(enum ih_category category, uint id)
|
|||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* get_cat_table_entry_short_name - translate entry id to short name
|
* genimg_get_cat_short_name - translate entry id to short name
|
||||||
* @category: category to look up (enum ih_category)
|
* @category: category to look up (enum ih_category)
|
||||||
* @id: entry id to be translated
|
* @id: entry id to be translated
|
||||||
*
|
*
|
||||||
* This will scan the translation table trying to find the entry that matches
|
* This will scan the translation table trying to find the entry that matches
|
||||||
* the given id.
|
* the given id.
|
||||||
*
|
*
|
||||||
* @retur short entry name if translation succeeds; error string on failure
|
* @return short entry name if translation succeeds; error string on failure
|
||||||
*/
|
*/
|
||||||
const char *genimg_get_cat_short_name(enum ih_category category, uint id)
|
const char *genimg_get_cat_short_name(enum ih_category category, uint id)
|
||||||
{
|
{
|
||||||
@ -858,6 +858,24 @@ const char *genimg_get_cat_desc(enum ih_category category)
|
|||||||
return table_info[category].desc;
|
return table_info[category].desc;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* genimg_cat_has_id - check whether category has entry id
|
||||||
|
* @category: category to look up (enum ih_category)
|
||||||
|
* @id: entry id to be checked
|
||||||
|
*
|
||||||
|
* This will scan the translation table trying to find the entry that matches
|
||||||
|
* the given id.
|
||||||
|
*
|
||||||
|
* @return true if category has entry id; false if not
|
||||||
|
*/
|
||||||
|
bool genimg_cat_has_id(enum ih_category category, uint id)
|
||||||
|
{
|
||||||
|
if (get_table_entry(table_info[category].table, id))
|
||||||
|
return true;
|
||||||
|
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* get_table_entry_name - translate entry id to long name
|
* get_table_entry_name - translate entry id to long name
|
||||||
* @table: pointer to a translation table for entries of a specific type
|
* @table: pointer to a translation table for entries of a specific type
|
||||||
@ -900,6 +918,12 @@ const char *genimg_get_type_name(uint8_t type)
|
|||||||
return (get_table_entry_name(uimage_type, "Unknown Image", type));
|
return (get_table_entry_name(uimage_type, "Unknown Image", type));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
const char *genimg_get_comp_name(uint8_t comp)
|
||||||
|
{
|
||||||
|
return (get_table_entry_name(uimage_comp, "Unknown Compression",
|
||||||
|
comp));
|
||||||
|
}
|
||||||
|
|
||||||
static const char *genimg_get_short_name(const table_entry_t *table, int val)
|
static const char *genimg_get_short_name(const table_entry_t *table, int val)
|
||||||
{
|
{
|
||||||
table = get_table_entry(table, val);
|
table = get_table_entry(table, val);
|
||||||
@ -917,12 +941,6 @@ const char *genimg_get_type_short_name(uint8_t type)
|
|||||||
return genimg_get_short_name(uimage_type, type);
|
return genimg_get_short_name(uimage_type, type);
|
||||||
}
|
}
|
||||||
|
|
||||||
const char *genimg_get_comp_name(uint8_t comp)
|
|
||||||
{
|
|
||||||
return (get_table_entry_name(uimage_comp, "Unknown Compression",
|
|
||||||
comp));
|
|
||||||
}
|
|
||||||
|
|
||||||
const char *genimg_get_comp_short_name(uint8_t comp)
|
const char *genimg_get_comp_short_name(uint8_t comp)
|
||||||
{
|
{
|
||||||
return genimg_get_short_name(uimage_comp, comp);
|
return genimg_get_short_name(uimage_comp, comp);
|
||||||
|
@ -21,6 +21,11 @@ static const char *log_cat_name[LOGC_COUNT - LOGC_NONE] = {
|
|||||||
"driver-model",
|
"driver-model",
|
||||||
"device-tree",
|
"device-tree",
|
||||||
"efi",
|
"efi",
|
||||||
|
"alloc",
|
||||||
|
"sandbox",
|
||||||
|
"bloblist",
|
||||||
|
"devres",
|
||||||
|
"acpi",
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *log_level_name[LOGL_COUNT] = {
|
static const char *log_level_name[LOGL_COUNT] = {
|
||||||
|
@ -37,9 +37,9 @@ config SPL_FRAMEWORK_BOARD_INIT_F
|
|||||||
config SPL_SIZE_LIMIT
|
config SPL_SIZE_LIMIT
|
||||||
hex "Maximum size of SPL image"
|
hex "Maximum size of SPL image"
|
||||||
depends on SPL
|
depends on SPL
|
||||||
default 69632 if ARCH_MX6 && !MX6_OCRAM_256KB
|
default 0x11000 if ARCH_MX6 && !MX6_OCRAM_256KB
|
||||||
default 200704 if ARCH_MX6 && MX6_OCRAM_256KB
|
default 0x31000 if ARCH_MX6 && MX6_OCRAM_256KB
|
||||||
default 0
|
default 0x0
|
||||||
help
|
help
|
||||||
Specifies the maximum length of the U-Boot SPL image.
|
Specifies the maximum length of the U-Boot SPL image.
|
||||||
If this value is zero, it is ignored.
|
If this value is zero, it is ignored.
|
||||||
@ -1335,7 +1335,7 @@ if TPL
|
|||||||
config TPL_SIZE_LIMIT
|
config TPL_SIZE_LIMIT
|
||||||
hex "Maximum size of TPL image"
|
hex "Maximum size of TPL image"
|
||||||
depends on TPL
|
depends on TPL
|
||||||
default 0
|
default 0x0
|
||||||
help
|
help
|
||||||
Specifies the maximum length of the U-Boot TPL image.
|
Specifies the maximum length of the U-Boot TPL image.
|
||||||
If this value is zero, it is ignored.
|
If this value is zero, it is ignored.
|
||||||
|
@ -32,7 +32,7 @@ struct ymodem_fit_info {
|
|||||||
|
|
||||||
static int getcymodem(void) {
|
static int getcymodem(void) {
|
||||||
if (tstc())
|
if (tstc())
|
||||||
return (getc());
|
return (getchar());
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -72,7 +72,7 @@ CYGACC_COMM_IF_GETC_TIMEOUT (char chan, char *c)
|
|||||||
}
|
}
|
||||||
if (tstc ())
|
if (tstc ())
|
||||||
{
|
{
|
||||||
*c = getc ();
|
*c = getchar();
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
return 0;
|
return 0;
|
||||||
|
@ -66,6 +66,7 @@ CONFIG_SPI_FLASH_ATMEL=y
|
|||||||
CONFIG_SPI_FLASH_DATAFLASH=y
|
CONFIG_SPI_FLASH_DATAFLASH=y
|
||||||
CONFIG_PINCTRL=y
|
CONFIG_PINCTRL=y
|
||||||
CONFIG_PINCTRL_AT91=y
|
CONFIG_PINCTRL_AT91=y
|
||||||
|
CONFIG_RTC_PCF8563=y
|
||||||
CONFIG_DM_SERIAL=y
|
CONFIG_DM_SERIAL=y
|
||||||
CONFIG_ATMEL_USART=y
|
CONFIG_ATMEL_USART=y
|
||||||
CONFIG_SPI=y
|
CONFIG_SPI=y
|
||||||
|
@ -6,7 +6,7 @@ CONFIG_ENV_OFFSET=0x3F8000
|
|||||||
CONFIG_ROCKCHIP_RK3288=y
|
CONFIG_ROCKCHIP_RK3288=y
|
||||||
CONFIG_TARGET_FIREFLY_RK3288=y
|
CONFIG_TARGET_FIREFLY_RK3288=y
|
||||||
CONFIG_SPL_STACK_R_ADDR=0x80000
|
CONFIG_SPL_STACK_R_ADDR=0x80000
|
||||||
CONFIG_SPL_SIZE_LIMIT=262144
|
CONFIG_SPL_SIZE_LIMIT=0x40000
|
||||||
CONFIG_DEBUG_UART_BASE=0xff690000
|
CONFIG_DEBUG_UART_BASE=0xff690000
|
||||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||||
CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly"
|
CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly"
|
||||||
|
@ -175,5 +175,6 @@ CONFIG_PHY_VITESSE=y
|
|||||||
CONFIG_MII=y
|
CONFIG_MII=y
|
||||||
CONFIG_TSEC_ENET=y
|
CONFIG_TSEC_ENET=y
|
||||||
# CONFIG_PCI is not set
|
# CONFIG_PCI is not set
|
||||||
|
CONFIG_RTC_PCF8563=y
|
||||||
CONFIG_SYS_NS16550=y
|
CONFIG_SYS_NS16550=y
|
||||||
CONFIG_OF_LIBFDT=y
|
CONFIG_OF_LIBFDT=y
|
||||||
|
@ -12,7 +12,7 @@ CONFIG_SPL_TEXT_BASE=0x20209000
|
|||||||
CONFIG_TARGET_IMXRT1020_EVK=y
|
CONFIG_TARGET_IMXRT1020_EVK=y
|
||||||
CONFIG_SPL_MMC_SUPPORT=y
|
CONFIG_SPL_MMC_SUPPORT=y
|
||||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||||
CONFIG_SPL_SIZE_LIMIT=131072
|
CONFIG_SPL_SIZE_LIMIT=0x20000
|
||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
|
||||||
CONFIG_DEFAULT_DEVICE_TREE="imxrt1020-evk"
|
CONFIG_DEFAULT_DEVICE_TREE="imxrt1020-evk"
|
||||||
CONFIG_DISTRO_DEFAULTS=y
|
CONFIG_DISTRO_DEFAULTS=y
|
||||||
|
@ -14,7 +14,7 @@ CONFIG_SPL_TEXT_BASE=0x20209000
|
|||||||
CONFIG_TARGET_IMXRT1050_EVK=y
|
CONFIG_TARGET_IMXRT1050_EVK=y
|
||||||
CONFIG_SPL_MMC_SUPPORT=y
|
CONFIG_SPL_MMC_SUPPORT=y
|
||||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||||
CONFIG_SPL_SIZE_LIMIT=131072
|
CONFIG_SPL_SIZE_LIMIT=0x20000
|
||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
|
||||||
CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk"
|
CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk"
|
||||||
CONFIG_DISTRO_DEFAULTS=y
|
CONFIG_DISTRO_DEFAULTS=y
|
||||||
|
@ -72,6 +72,7 @@ CONFIG_DM_PCI=y
|
|||||||
CONFIG_DM_PCI_COMPAT=y
|
CONFIG_DM_PCI_COMPAT=y
|
||||||
CONFIG_PCIE_LAYERSCAPE_RC=y
|
CONFIG_PCIE_LAYERSCAPE_RC=y
|
||||||
CONFIG_DM_RTC=y
|
CONFIG_DM_RTC=y
|
||||||
|
CONFIG_RTC_PCF8563=y
|
||||||
CONFIG_SCSI=y
|
CONFIG_SCSI=y
|
||||||
CONFIG_DM_SCSI=y
|
CONFIG_DM_SCSI=y
|
||||||
CONFIG_SYS_NS16550=y
|
CONFIG_SYS_NS16550=y
|
||||||
|
@ -61,6 +61,7 @@ CONFIG_DM_PCI=y
|
|||||||
CONFIG_DM_PCI_COMPAT=y
|
CONFIG_DM_PCI_COMPAT=y
|
||||||
CONFIG_PCIE_LAYERSCAPE_RC=y
|
CONFIG_PCIE_LAYERSCAPE_RC=y
|
||||||
CONFIG_DM_RTC=y
|
CONFIG_DM_RTC=y
|
||||||
|
CONFIG_RTC_PCF8563=y
|
||||||
CONFIG_SCSI=y
|
CONFIG_SCSI=y
|
||||||
CONFIG_DM_SCSI=y
|
CONFIG_DM_SCSI=y
|
||||||
CONFIG_SYS_NS16550=y
|
CONFIG_SYS_NS16550=y
|
||||||
|
@ -72,6 +72,7 @@ CONFIG_DM_PCI=y
|
|||||||
CONFIG_DM_PCI_COMPAT=y
|
CONFIG_DM_PCI_COMPAT=y
|
||||||
CONFIG_PCIE_LAYERSCAPE_RC=y
|
CONFIG_PCIE_LAYERSCAPE_RC=y
|
||||||
CONFIG_DM_RTC=y
|
CONFIG_DM_RTC=y
|
||||||
|
CONFIG_RTC_PCF8563=y
|
||||||
CONFIG_SCSI=y
|
CONFIG_SCSI=y
|
||||||
CONFIG_DM_SCSI=y
|
CONFIG_DM_SCSI=y
|
||||||
CONFIG_SYS_NS16550=y
|
CONFIG_SYS_NS16550=y
|
||||||
|
@ -51,6 +51,7 @@ CONFIG_PCI=y
|
|||||||
CONFIG_DM_PCI=y
|
CONFIG_DM_PCI=y
|
||||||
CONFIG_DM_PCI_COMPAT=y
|
CONFIG_DM_PCI_COMPAT=y
|
||||||
CONFIG_PCIE_LAYERSCAPE_RC=y
|
CONFIG_PCIE_LAYERSCAPE_RC=y
|
||||||
|
CONFIG_RTC_PCF8563=y
|
||||||
CONFIG_SCSI=y
|
CONFIG_SCSI=y
|
||||||
CONFIG_DM_SCSI=y
|
CONFIG_DM_SCSI=y
|
||||||
CONFIG_CONS_INDEX=2
|
CONFIG_CONS_INDEX=2
|
||||||
|
@ -7,7 +7,7 @@ CONFIG_NR_DRAM_BANKS=1
|
|||||||
CONFIG_ROCKCHIP_RK3288=y
|
CONFIG_ROCKCHIP_RK3288=y
|
||||||
CONFIG_TARGET_TINKER_RK3288=y
|
CONFIG_TARGET_TINKER_RK3288=y
|
||||||
CONFIG_SPL_STACK_R_ADDR=0x800000
|
CONFIG_SPL_STACK_R_ADDR=0x800000
|
||||||
CONFIG_SPL_SIZE_LIMIT=307200
|
CONFIG_SPL_SIZE_LIMIT=0x4B000
|
||||||
CONFIG_DEBUG_UART_BASE=0xff690000
|
CONFIG_DEBUG_UART_BASE=0xff690000
|
||||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||||
CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker-s"
|
CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker-s"
|
||||||
|
@ -121,7 +121,7 @@ Commands:
|
|||||||
"sf" (serial flash : NOR)
|
"sf" (serial flash : NOR)
|
||||||
cmd: dfu 0 sf <dev>
|
cmd: dfu 0 sf <dev>
|
||||||
each element in "dfu_alt_info" =
|
each element in "dfu_alt_info" =
|
||||||
<name> ram <offset> <size> raw access to sf device
|
<name> raw <offset> <size> raw access to sf device
|
||||||
<name> part <dev> <part_id> raw acces to partition
|
<name> part <dev> <part_id> raw acces to partition
|
||||||
<name> partubi <dev> <part_id> raw acces to ubi partition
|
<name> partubi <dev> <part_id> raw acces to ubi partition
|
||||||
|
|
||||||
|
@ -12,4 +12,5 @@ U-Boot API documentation
|
|||||||
pinctrl
|
pinctrl
|
||||||
rng
|
rng
|
||||||
serial
|
serial
|
||||||
|
timer
|
||||||
unicode
|
unicode
|
||||||
|
8
doc/api/timer.rst
Normal file
8
doc/api/timer.rst
Normal file
@ -0,0 +1,8 @@
|
|||||||
|
.. SPDX-License-Identifier: GPL-2.0+
|
||||||
|
.. Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
|
||||||
|
|
||||||
|
Timer Subsystem
|
||||||
|
===============
|
||||||
|
|
||||||
|
.. kernel-doc:: include/timer.h
|
||||||
|
:internal:
|
@ -83,11 +83,8 @@ Sometimes it is useful to turn on logging just in one file. You can use this
|
|||||||
#define LOG_DEBUG
|
#define LOG_DEBUG
|
||||||
|
|
||||||
to enable building in of all logging statements in a single file. Put it at
|
to enable building in of all logging statements in a single file. Put it at
|
||||||
the top of the file, before any #includes.
|
the top of the file, before any #includes. This overrides any log-level setting
|
||||||
|
in U-Boot, including CONFIG_LOG_DEFAULT_LEVEL, but just for that file.
|
||||||
To actually get U-Boot to output this you need to also set the default logging
|
|
||||||
level - e.g. set CONFIG_LOG_DEFAULT_LEVEL to 7 (LOGL_DEBUG) or more. Otherwise
|
|
||||||
debug output is suppressed and will not be generated.
|
|
||||||
|
|
||||||
|
|
||||||
Convenience functions
|
Convenience functions
|
||||||
@ -111,6 +108,12 @@ LOG_CATEGORY, which you can only define once per file, above all #includes, e.g.
|
|||||||
|
|
||||||
#define LOG_CATEGORY LOGC_ALLOC
|
#define LOG_CATEGORY LOGC_ALLOC
|
||||||
|
|
||||||
|
or
|
||||||
|
|
||||||
|
.. code-block:: c
|
||||||
|
|
||||||
|
#define LOG_CATEGORY UCLASS_SPI
|
||||||
|
|
||||||
Remember that all uclasses IDs are log categories too.
|
Remember that all uclasses IDs are log categories too.
|
||||||
|
|
||||||
|
|
||||||
|
33
doc/device-tree-bindings/spi/spi-qup.txt
Normal file
33
doc/device-tree-bindings/spi/spi-qup.txt
Normal file
@ -0,0 +1,33 @@
|
|||||||
|
Qualcomm QUP SPI controller Device Tree Bindings
|
||||||
|
-------------------------------------------
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible : Should be "qcom,spi-qup-v1.1.1", "qcom,spi-qup-v2.1.1"
|
||||||
|
or "qcom,spi-qup-v2.2.1"
|
||||||
|
- reg : Physical base address and size of SPI registers map.
|
||||||
|
- clock : Clock phandle (see clock bindings for details).
|
||||||
|
- #address-cells : Number of cells required to define a chip select
|
||||||
|
address on the SPI bus. Should be set to 1.
|
||||||
|
- #size-cells : Should be zero.
|
||||||
|
- pinctrl-names : Must be "default"
|
||||||
|
- pinctrl-n : At least one pinctrl phandle
|
||||||
|
- cs-gpios : Should specify GPIOs used for chipselects.
|
||||||
|
The gpios will be referred to as reg = <index> in the
|
||||||
|
SPI child nodes.
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
- num-cs : total number of chipselects
|
||||||
|
|
||||||
|
Example:
|
||||||
|
|
||||||
|
blsp1_spi1: spi@78b5000 {
|
||||||
|
compatible = "qcom,spi-qup-v2.2.1";
|
||||||
|
reg = <0x78b5000 0x600>;
|
||||||
|
clock = <&gcc 23>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
pinctrl-names = "spi";
|
||||||
|
pinctrl-0 = <&blsp_spi0>;
|
||||||
|
num-cs = <2>;
|
||||||
|
cs-gpios = <&soc_gpios 54 GPIO_ACTIVE_HIGH>, <&soc_gpios 4 GPIO_ACTIVE_HIGH>;
|
||||||
|
};
|
@ -150,32 +150,8 @@ static int clk_mux_set_parent(struct clk *clk, struct clk *parent)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static ulong clk_mux_get_rate(struct clk *clk)
|
|
||||||
{
|
|
||||||
struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
|
|
||||||
dev_get_clk_ptr(clk->dev) : clk);
|
|
||||||
struct udevice *parent;
|
|
||||||
struct clk *pclk;
|
|
||||||
int err, index;
|
|
||||||
|
|
||||||
index = clk_mux_get_parent(clk);
|
|
||||||
if (index >= mux->num_parents)
|
|
||||||
return -EFAULT;
|
|
||||||
|
|
||||||
err = uclass_get_device_by_name(UCLASS_CLK, mux->parent_names[index],
|
|
||||||
&parent);
|
|
||||||
if (err)
|
|
||||||
return err;
|
|
||||||
|
|
||||||
pclk = dev_get_clk_ptr(parent);
|
|
||||||
if (!pclk)
|
|
||||||
return -ENODEV;
|
|
||||||
|
|
||||||
return clk_get_rate(pclk);
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct clk_ops clk_mux_ops = {
|
const struct clk_ops clk_mux_ops = {
|
||||||
.get_rate = clk_mux_get_rate,
|
.get_rate = clk_generic_get_rate,
|
||||||
.set_parent = clk_mux_set_parent,
|
.set_parent = clk_mux_set_parent,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -142,7 +142,7 @@ int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp)
|
|||||||
|
|
||||||
ret = uclass_first_device_drvdata(UCLASS_SYSCON, driver_data, devp);
|
ret = uclass_first_device_drvdata(UCLASS_SYSCON, driver_data, devp);
|
||||||
if (ret)
|
if (ret)
|
||||||
return log_msg_ret("find", ret);
|
return ret;
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -705,7 +705,7 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
|
|||||||
|
|
||||||
/* Compute it once normally. */
|
/* Compute it once normally. */
|
||||||
#ifdef CONFIG_FSL_DDR_INTERACTIVE
|
#ifdef CONFIG_FSL_DDR_INTERACTIVE
|
||||||
if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */
|
if (tstc() && (getchar() == 'd')) { /* we got a key press of 'd' */
|
||||||
total_memory = fsl_ddr_interactive(pinfo, 0);
|
total_memory = fsl_ddr_interactive(pinfo, 0);
|
||||||
} else if (fsl_ddr_interactive_env_var_exists()) {
|
} else if (fsl_ddr_interactive_env_var_exists()) {
|
||||||
total_memory = fsl_ddr_interactive(pinfo, 1);
|
total_memory = fsl_ddr_interactive(pinfo, 1);
|
||||||
|
@ -107,7 +107,7 @@
|
|||||||
#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
|
#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
|
||||||
#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
|
#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
|
||||||
#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
|
#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
|
||||||
#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */
|
#define MV_INIT_ERROR (0x16) /* Error occurred while INIT process */
|
||||||
#define MV_HW_ERROR (0x17) /* Hardware error */
|
#define MV_HW_ERROR (0x17) /* Hardware error */
|
||||||
#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
|
#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
|
||||||
#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
|
#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
|
||||||
|
@ -807,7 +807,7 @@ int designware_i2c_probe(struct udevice *bus)
|
|||||||
return -ENXIO;
|
return -ENXIO;
|
||||||
}
|
}
|
||||||
|
|
||||||
log_info("I2C bus %s version %#x\n", bus->name,
|
log_debug("I2C bus %s version %#x\n", bus->name,
|
||||||
readl(&priv->regs->comp_version));
|
readl(&priv->regs->comp_version));
|
||||||
|
|
||||||
return __dw_i2c_init(priv->regs, 0, 0);
|
return __dw_i2c_init(priv->regs, 0, 0);
|
||||||
|
@ -2192,7 +2192,7 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
|
|||||||
return 0;
|
return 0;
|
||||||
error:
|
error:
|
||||||
mmc_set_signal_voltage(mmc, old_voltage);
|
mmc_set_signal_voltage(mmc, old_voltage);
|
||||||
/* if an error occured, revert to a safer bus mode */
|
/* if an error occurred, revert to a safer bus mode */
|
||||||
mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
|
mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
|
||||||
EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
|
EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
|
||||||
mmc_select_mode(mmc, MMC_LEGACY);
|
mmc_select_mode(mmc, MMC_LEGACY);
|
||||||
|
@ -1171,7 +1171,7 @@ skip_fall:
|
|||||||
internal_delay |= (1 << i);
|
internal_delay |= (1 << i);
|
||||||
}
|
}
|
||||||
|
|
||||||
dev_err(dev, "Final internal delay: 0x%x\n", internal_delay);
|
dev_dbg(dev, "Final internal delay: 0x%x\n", internal_delay);
|
||||||
|
|
||||||
internal_delay_phase = get_best_delay(dev, host, internal_delay);
|
internal_delay_phase = get_best_delay(dev, host, internal_delay);
|
||||||
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
|
clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
|
||||||
@ -1179,7 +1179,7 @@ skip_fall:
|
|||||||
MSDC_PAD_TUNE_CMDRRDLY_S);
|
MSDC_PAD_TUNE_CMDRRDLY_S);
|
||||||
|
|
||||||
skip_internal:
|
skip_internal:
|
||||||
dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
|
dev_dbg(dev, "Final cmd pad delay: %x\n", final_delay);
|
||||||
return final_delay == 0xff ? -EIO : 0;
|
return final_delay == 0xff ? -EIO : 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1265,7 +1265,7 @@ skip_fall:
|
|||||||
host->hs200_write_int_delay <<
|
host->hs200_write_int_delay <<
|
||||||
MSDC_PAD_TUNE_DATWRDLY_S);
|
MSDC_PAD_TUNE_DATWRDLY_S);
|
||||||
|
|
||||||
dev_err(dev, "Final data pad delay: %x\n", final_delay);
|
dev_dbg(dev, "Final data pad delay: %x\n", final_delay);
|
||||||
|
|
||||||
return final_delay == 0xff ? -EIO : 0;
|
return final_delay == 0xff ? -EIO : 0;
|
||||||
}
|
}
|
||||||
|
@ -732,6 +732,13 @@ config MDIO_MUX_I2CREG
|
|||||||
an I2C chip. The board it was developed for uses a mux controlled by
|
an I2C chip. The board it was developed for uses a mux controlled by
|
||||||
on-board FPGA which in turn is accessed as a chip over I2C.
|
on-board FPGA which in turn is accessed as a chip over I2C.
|
||||||
|
|
||||||
|
config MDIO_IPQ4019
|
||||||
|
bool "Qualcomm IPQ4019 MDIO interface support"
|
||||||
|
depends on DM_MDIO
|
||||||
|
help
|
||||||
|
This driver supports the MDIO interface found in Qualcomm
|
||||||
|
IPQ40xx series Soc-s.
|
||||||
|
|
||||||
config MVMDIO
|
config MVMDIO
|
||||||
bool "Marvell MDIO interface support"
|
bool "Marvell MDIO interface support"
|
||||||
depends on DM_MDIO
|
depends on DM_MDIO
|
||||||
|
@ -40,6 +40,7 @@ obj-$(CONFIG_LAN91C96) += lan91c96.o
|
|||||||
obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
|
obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
|
||||||
obj-$(CONFIG_MACB) += macb.o
|
obj-$(CONFIG_MACB) += macb.o
|
||||||
obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
|
obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
|
||||||
|
obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o
|
||||||
obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o
|
obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o
|
||||||
obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o
|
obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o
|
||||||
obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o
|
obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o
|
||||||
|
146
drivers/net/mdio-ipq4019.c
Normal file
146
drivers/net/mdio-ipq4019.c
Normal file
@ -0,0 +1,146 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* Qualcomm IPQ4019 MDIO driver
|
||||||
|
*
|
||||||
|
* Copyright (c) 2020 Sartura Ltd.
|
||||||
|
*
|
||||||
|
* Author: Luka Kovacic <luka.kovacic@sartura.hr>
|
||||||
|
* Author: Robert Marko <robert.marko@sartura.hr>
|
||||||
|
*
|
||||||
|
* Based on Linux driver
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <common.h>
|
||||||
|
#include <dm.h>
|
||||||
|
#include <errno.h>
|
||||||
|
#include <linux/bitops.h>
|
||||||
|
#include <linux/iopoll.h>
|
||||||
|
#include <miiphy.h>
|
||||||
|
#include <phy.h>
|
||||||
|
|
||||||
|
#define MDIO_MODE_REG 0x40
|
||||||
|
#define MDIO_ADDR_REG 0x44
|
||||||
|
#define MDIO_DATA_WRITE_REG 0x48
|
||||||
|
#define MDIO_DATA_READ_REG 0x4c
|
||||||
|
#define MDIO_CMD_REG 0x50
|
||||||
|
#define MDIO_CMD_ACCESS_BUSY BIT(16)
|
||||||
|
#define MDIO_CMD_ACCESS_START BIT(8)
|
||||||
|
#define MDIO_CMD_ACCESS_CODE_READ 0
|
||||||
|
#define MDIO_CMD_ACCESS_CODE_WRITE 1
|
||||||
|
|
||||||
|
/* 0 = Clause 22, 1 = Clause 45 */
|
||||||
|
#define MDIO_MODE_BIT BIT(8)
|
||||||
|
|
||||||
|
#define IPQ4019_MDIO_TIMEOUT 10000
|
||||||
|
#define IPQ4019_MDIO_SLEEP 10
|
||||||
|
|
||||||
|
struct ipq4019_mdio_priv {
|
||||||
|
phys_addr_t mdio_base;
|
||||||
|
};
|
||||||
|
|
||||||
|
static int ipq4019_mdio_wait_busy(struct ipq4019_mdio_priv *priv)
|
||||||
|
{
|
||||||
|
unsigned int busy;
|
||||||
|
|
||||||
|
return readl_poll_sleep_timeout(priv->mdio_base + MDIO_CMD_REG, busy,
|
||||||
|
(busy & MDIO_CMD_ACCESS_BUSY) == 0, IPQ4019_MDIO_SLEEP,
|
||||||
|
IPQ4019_MDIO_TIMEOUT);
|
||||||
|
}
|
||||||
|
|
||||||
|
int ipq4019_mdio_read(struct udevice *dev, int addr, int devad, int reg)
|
||||||
|
{
|
||||||
|
struct ipq4019_mdio_priv *priv = dev_get_priv(dev);
|
||||||
|
unsigned int cmd;
|
||||||
|
|
||||||
|
if (ipq4019_mdio_wait_busy(priv))
|
||||||
|
return -ETIMEDOUT;
|
||||||
|
|
||||||
|
/* Issue the phy address and reg */
|
||||||
|
writel((addr << 8) | reg, priv->mdio_base + MDIO_ADDR_REG);
|
||||||
|
|
||||||
|
cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_READ;
|
||||||
|
|
||||||
|
/* Issue read command */
|
||||||
|
writel(cmd, priv->mdio_base + MDIO_CMD_REG);
|
||||||
|
|
||||||
|
/* Wait read complete */
|
||||||
|
if (ipq4019_mdio_wait_busy(priv))
|
||||||
|
return -ETIMEDOUT;
|
||||||
|
|
||||||
|
/* Read and return data */
|
||||||
|
return readl(priv->mdio_base + MDIO_DATA_READ_REG);
|
||||||
|
}
|
||||||
|
|
||||||
|
int ipq4019_mdio_write(struct udevice *dev, int addr, int devad,
|
||||||
|
int reg, u16 val)
|
||||||
|
{
|
||||||
|
struct ipq4019_mdio_priv *priv = dev_get_priv(dev);
|
||||||
|
unsigned int cmd;
|
||||||
|
|
||||||
|
if (ipq4019_mdio_wait_busy(priv))
|
||||||
|
return -ETIMEDOUT;
|
||||||
|
|
||||||
|
/* Issue the phy addreass and reg */
|
||||||
|
writel((addr << 8) | reg, priv->mdio_base + MDIO_ADDR_REG);
|
||||||
|
|
||||||
|
/* Issue write data */
|
||||||
|
writel(val, priv->mdio_base + MDIO_DATA_WRITE_REG);
|
||||||
|
|
||||||
|
cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_WRITE;
|
||||||
|
|
||||||
|
/* Issue write command */
|
||||||
|
writel(cmd, priv->mdio_base + MDIO_CMD_REG);
|
||||||
|
|
||||||
|
/* Wait for write complete */
|
||||||
|
|
||||||
|
if (ipq4019_mdio_wait_busy(priv))
|
||||||
|
return -ETIMEDOUT;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct mdio_ops ipq4019_mdio_ops = {
|
||||||
|
.read = ipq4019_mdio_read,
|
||||||
|
.write = ipq4019_mdio_write,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int ipq4019_mdio_bind(struct udevice *dev)
|
||||||
|
{
|
||||||
|
if (ofnode_valid(dev->node))
|
||||||
|
device_set_name(dev, ofnode_get_name(dev->node));
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int ipq4019_mdio_probe(struct udevice *dev)
|
||||||
|
{
|
||||||
|
struct ipq4019_mdio_priv *priv = dev_get_priv(dev);
|
||||||
|
unsigned int data;
|
||||||
|
|
||||||
|
priv->mdio_base = dev_read_addr(dev);
|
||||||
|
if (priv->mdio_base == FDT_ADDR_T_NONE)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
/* Enter Clause 22 mode */
|
||||||
|
data = readl(priv->mdio_base + MDIO_MODE_REG);
|
||||||
|
data &= ~MDIO_MODE_BIT;
|
||||||
|
writel(data, priv->mdio_base + MDIO_MODE_REG);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct udevice_id ipq4019_mdio_ids[] = {
|
||||||
|
{ .compatible = "qcom,ipq4019-mdio", },
|
||||||
|
{ }
|
||||||
|
};
|
||||||
|
|
||||||
|
U_BOOT_DRIVER(ipq4019_mdio) = {
|
||||||
|
.name = "ipq4019_mdio",
|
||||||
|
.id = UCLASS_MDIO,
|
||||||
|
.of_match = ipq4019_mdio_ids,
|
||||||
|
.bind = ipq4019_mdio_bind,
|
||||||
|
.probe = ipq4019_mdio_probe,
|
||||||
|
.ops = &ipq4019_mdio_ops,
|
||||||
|
.priv_auto_alloc_size = sizeof(struct ipq4019_mdio_priv),
|
||||||
|
};
|
@ -394,7 +394,7 @@ bool stm32mp1_ddr_interactive(void *priv,
|
|||||||
unsigned long start = get_timer(0);
|
unsigned long start = get_timer(0);
|
||||||
|
|
||||||
while (1) {
|
while (1) {
|
||||||
if (tstc() && (getc() == 'd')) {
|
if (tstc() && (getchar() == 'd')) {
|
||||||
next_step = STEP_DDR_RESET;
|
next_step = STEP_DDR_RESET;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -72,15 +72,14 @@ config RESET_UNIPHIER
|
|||||||
Say Y if you want to control reset signals provided by System Control
|
Say Y if you want to control reset signals provided by System Control
|
||||||
block, Media I/O block, Peripheral Block.
|
block, Media I/O block, Peripheral Block.
|
||||||
|
|
||||||
config AST2500_RESET
|
config RESET_AST2500
|
||||||
bool "Reset controller driver for AST2500 SoCs"
|
bool "Reset controller driver for AST2500 SoCs"
|
||||||
depends on DM_RESET && WDT_ASPEED
|
depends on DM_RESET
|
||||||
default y if ASPEED_AST2500
|
default y if ASPEED_AST2500
|
||||||
help
|
help
|
||||||
Support for reset controller on AST2500 SoC. This controller uses
|
Support for reset controller on AST2500 SoC.
|
||||||
watchdog to reset different peripherals and thus only supports
|
Say Y if you want to control reset signals of different peripherals
|
||||||
resets that are supported by watchdog. The main limitation though
|
through System Control Unit (SCU).
|
||||||
is that some reset signals, like I2C or MISC reset multiple devices.
|
|
||||||
|
|
||||||
config RESET_ROCKCHIP
|
config RESET_ROCKCHIP
|
||||||
bool "Reset controller driver for Rockchip SoCs"
|
bool "Reset controller driver for Rockchip SoCs"
|
||||||
|
@ -14,7 +14,7 @@ obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
|
|||||||
obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
|
obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
|
||||||
obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
|
obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
|
||||||
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
|
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
|
||||||
obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
|
obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
|
||||||
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
|
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
|
||||||
obj-$(CONFIG_RESET_MESON) += reset-meson.o
|
obj-$(CONFIG_RESET_MESON) += reset-meson.o
|
||||||
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
|
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
|
||||||
|
@ -1,104 +0,0 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0
|
|
||||||
/*
|
|
||||||
* Copyright 2017 Google, Inc
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <dm.h>
|
|
||||||
#include <log.h>
|
|
||||||
#include <misc.h>
|
|
||||||
#include <reset.h>
|
|
||||||
#include <reset-uclass.h>
|
|
||||||
#include <wdt.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <asm/arch/scu_ast2500.h>
|
|
||||||
#include <asm/arch/wdt.h>
|
|
||||||
|
|
||||||
struct ast2500_reset_priv {
|
|
||||||
/* WDT used to perform resets. */
|
|
||||||
struct udevice *wdt;
|
|
||||||
struct ast2500_scu *scu;
|
|
||||||
};
|
|
||||||
|
|
||||||
static int ast2500_ofdata_to_platdata(struct udevice *dev)
|
|
||||||
{
|
|
||||||
struct ast2500_reset_priv *priv = dev_get_priv(dev);
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
ret = uclass_get_device_by_phandle(UCLASS_WDT, dev, "aspeed,wdt",
|
|
||||||
&priv->wdt);
|
|
||||||
if (ret) {
|
|
||||||
debug("%s: can't find WDT for reset controller", __func__);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int ast2500_reset_assert(struct reset_ctl *reset_ctl)
|
|
||||||
{
|
|
||||||
struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
|
|
||||||
u32 reset_mode, reset_mask;
|
|
||||||
bool reset_sdram;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* To reset SDRAM, a specifal flag in SYSRESET register
|
|
||||||
* needs to be enabled first
|
|
||||||
*/
|
|
||||||
reset_mode = ast_reset_mode_from_flags(reset_ctl->id);
|
|
||||||
reset_mask = ast_reset_mask_from_flags(reset_ctl->id);
|
|
||||||
reset_sdram = reset_mode == WDT_CTRL_RESET_SOC &&
|
|
||||||
(reset_mask & WDT_RESET_SDRAM);
|
|
||||||
|
|
||||||
if (reset_sdram) {
|
|
||||||
ast_scu_unlock(priv->scu);
|
|
||||||
setbits_le32(&priv->scu->sysreset_ctrl1,
|
|
||||||
SCU_SYSRESET_SDRAM_WDT);
|
|
||||||
ret = wdt_expire_now(priv->wdt, reset_ctl->id);
|
|
||||||
clrbits_le32(&priv->scu->sysreset_ctrl1,
|
|
||||||
SCU_SYSRESET_SDRAM_WDT);
|
|
||||||
ast_scu_lock(priv->scu);
|
|
||||||
} else {
|
|
||||||
ret = wdt_expire_now(priv->wdt, reset_ctl->id);
|
|
||||||
}
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int ast2500_reset_request(struct reset_ctl *reset_ctl)
|
|
||||||
{
|
|
||||||
debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
|
|
||||||
reset_ctl->dev, reset_ctl->id);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int ast2500_reset_probe(struct udevice *dev)
|
|
||||||
{
|
|
||||||
struct ast2500_reset_priv *priv = dev_get_priv(dev);
|
|
||||||
|
|
||||||
priv->scu = ast_get_scu();
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct udevice_id ast2500_reset_ids[] = {
|
|
||||||
{ .compatible = "aspeed,ast2500-reset" },
|
|
||||||
{ }
|
|
||||||
};
|
|
||||||
|
|
||||||
struct reset_ops ast2500_reset_ops = {
|
|
||||||
.rst_assert = ast2500_reset_assert,
|
|
||||||
.request = ast2500_reset_request,
|
|
||||||
};
|
|
||||||
|
|
||||||
U_BOOT_DRIVER(ast2500_reset) = {
|
|
||||||
.name = "ast2500_reset",
|
|
||||||
.id = UCLASS_RESET,
|
|
||||||
.of_match = ast2500_reset_ids,
|
|
||||||
.probe = ast2500_reset_probe,
|
|
||||||
.ops = &ast2500_reset_ops,
|
|
||||||
.ofdata_to_platdata = ast2500_ofdata_to_platdata,
|
|
||||||
.priv_auto_alloc_size = sizeof(struct ast2500_reset_priv),
|
|
||||||
};
|
|
109
drivers/reset/reset-ast2500.c
Normal file
109
drivers/reset/reset-ast2500.c
Normal file
@ -0,0 +1,109 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0
|
||||||
|
/*
|
||||||
|
* Copyright 2017 Google, Inc
|
||||||
|
* Copyright 2020 ASPEED Technology Inc.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <dm.h>
|
||||||
|
#include <log.h>
|
||||||
|
#include <misc.h>
|
||||||
|
#include <reset.h>
|
||||||
|
#include <reset-uclass.h>
|
||||||
|
#include <linux/err.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <asm/arch/scu_ast2500.h>
|
||||||
|
|
||||||
|
struct ast2500_reset_priv {
|
||||||
|
struct ast2500_scu *scu;
|
||||||
|
};
|
||||||
|
|
||||||
|
static int ast2500_reset_request(struct reset_ctl *reset_ctl)
|
||||||
|
{
|
||||||
|
debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
|
||||||
|
reset_ctl->dev, reset_ctl->id);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int ast2500_reset_free(struct reset_ctl *reset_ctl)
|
||||||
|
{
|
||||||
|
debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
|
||||||
|
reset_ctl->dev, reset_ctl->id);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int ast2500_reset_assert(struct reset_ctl *reset_ctl)
|
||||||
|
{
|
||||||
|
struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
|
||||||
|
struct ast2500_scu *scu = priv->scu;
|
||||||
|
|
||||||
|
debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
|
||||||
|
|
||||||
|
if (reset_ctl->id < 32)
|
||||||
|
setbits_le32(&scu->sysreset_ctrl1, BIT(reset_ctl->id));
|
||||||
|
else
|
||||||
|
setbits_le32(&scu->sysreset_ctrl2, BIT(reset_ctl->id - 32));
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int ast2500_reset_deassert(struct reset_ctl *reset_ctl)
|
||||||
|
{
|
||||||
|
struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
|
||||||
|
struct ast2500_scu *scu = priv->scu;
|
||||||
|
|
||||||
|
debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
|
||||||
|
|
||||||
|
if (reset_ctl->id < 32)
|
||||||
|
clrbits_le32(&scu->sysreset_ctrl1, BIT(reset_ctl->id));
|
||||||
|
else
|
||||||
|
clrbits_le32(&scu->sysreset_ctrl2, BIT(reset_ctl->id - 32));
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int ast2500_reset_probe(struct udevice *dev)
|
||||||
|
{
|
||||||
|
int rc;
|
||||||
|
struct ast2500_reset_priv *priv = dev_get_priv(dev);
|
||||||
|
struct udevice *scu_dev;
|
||||||
|
|
||||||
|
/* get SCU base from clock device */
|
||||||
|
rc = uclass_get_device_by_driver(UCLASS_CLK,
|
||||||
|
DM_GET_DRIVER(aspeed_ast2500_scu), &scu_dev);
|
||||||
|
if (rc) {
|
||||||
|
debug("%s: clock device not found, rc=%d\n", __func__, rc);
|
||||||
|
return rc;
|
||||||
|
}
|
||||||
|
|
||||||
|
priv->scu = devfdt_get_addr_ptr(scu_dev);
|
||||||
|
if (IS_ERR_OR_NULL(priv->scu)) {
|
||||||
|
debug("%s: invalid SCU base pointer\n", __func__);
|
||||||
|
return PTR_ERR(priv->scu);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct udevice_id ast2500_reset_ids[] = {
|
||||||
|
{ .compatible = "aspeed,ast2500-reset" },
|
||||||
|
{ }
|
||||||
|
};
|
||||||
|
|
||||||
|
struct reset_ops ast2500_reset_ops = {
|
||||||
|
.request = ast2500_reset_request,
|
||||||
|
.rfree = ast2500_reset_free,
|
||||||
|
.rst_assert = ast2500_reset_assert,
|
||||||
|
.rst_deassert = ast2500_reset_deassert,
|
||||||
|
};
|
||||||
|
|
||||||
|
U_BOOT_DRIVER(ast2500_reset) = {
|
||||||
|
.name = "ast2500_reset",
|
||||||
|
.id = UCLASS_RESET,
|
||||||
|
.of_match = ast2500_reset_ids,
|
||||||
|
.probe = ast2500_reset_probe,
|
||||||
|
.ops = &ast2500_reset_ops,
|
||||||
|
.priv_auto_alloc_size = sizeof(struct ast2500_reset_priv),
|
||||||
|
};
|
@ -24,6 +24,13 @@ config RNG_SANDBOX
|
|||||||
Enable random number generator for sandbox. This is an
|
Enable random number generator for sandbox. This is an
|
||||||
emulation of a rng device.
|
emulation of a rng device.
|
||||||
|
|
||||||
|
config RNG_MSM
|
||||||
|
bool "Qualcomm SoCs Random Number Generator support"
|
||||||
|
depends on DM_RNG
|
||||||
|
help
|
||||||
|
This driver provides support for the Random Number
|
||||||
|
Generator hardware found on Qualcomm SoCs.
|
||||||
|
|
||||||
config RNG_STM32MP1
|
config RNG_STM32MP1
|
||||||
bool "Enable random number generator for STM32MP1"
|
bool "Enable random number generator for STM32MP1"
|
||||||
depends on ARCH_STM32MP
|
depends on ARCH_STM32MP
|
||||||
|
@ -6,5 +6,6 @@
|
|||||||
obj-$(CONFIG_DM_RNG) += rng-uclass.o
|
obj-$(CONFIG_DM_RNG) += rng-uclass.o
|
||||||
obj-$(CONFIG_RNG_MESON) += meson-rng.o
|
obj-$(CONFIG_RNG_MESON) += meson-rng.o
|
||||||
obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o
|
obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o
|
||||||
|
obj-$(CONFIG_RNG_MSM) += msm_rng.o
|
||||||
obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
|
obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
|
||||||
obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o
|
obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o
|
||||||
|
143
drivers/rng/msm_rng.c
Normal file
143
drivers/rng/msm_rng.c
Normal file
@ -0,0 +1,143 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* PRNG driver for Qualcomm IPQ40xx
|
||||||
|
*
|
||||||
|
* Copyright (c) 2020 Sartura Ltd.
|
||||||
|
*
|
||||||
|
* Author: Robert Marko <robert.marko@sartura.hr>
|
||||||
|
*
|
||||||
|
* Based on Linux driver
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <clk.h>
|
||||||
|
#include <common.h>
|
||||||
|
#include <dm.h>
|
||||||
|
#include <linux/bitops.h>
|
||||||
|
#include <rng.h>
|
||||||
|
|
||||||
|
/* Device specific register offsets */
|
||||||
|
#define PRNG_DATA_OUT 0x0000
|
||||||
|
#define PRNG_STATUS 0x0004
|
||||||
|
#define PRNG_LFSR_CFG 0x0100
|
||||||
|
#define PRNG_CONFIG 0x0104
|
||||||
|
|
||||||
|
/* Device specific register masks and config values */
|
||||||
|
#define PRNG_LFSR_CFG_MASK 0x0000ffff
|
||||||
|
#define PRNG_LFSR_CFG_CLOCKS 0x0000dddd
|
||||||
|
#define PRNG_CONFIG_HW_ENABLE BIT(1)
|
||||||
|
#define PRNG_STATUS_DATA_AVAIL BIT(0)
|
||||||
|
|
||||||
|
#define MAX_HW_FIFO_DEPTH 16
|
||||||
|
#define MAX_HW_FIFO_SIZE (MAX_HW_FIFO_DEPTH * 4)
|
||||||
|
#define WORD_SZ 4
|
||||||
|
|
||||||
|
struct msm_rng_priv {
|
||||||
|
phys_addr_t base;
|
||||||
|
struct clk clk;
|
||||||
|
};
|
||||||
|
|
||||||
|
static int msm_rng_read(struct udevice *dev, void *data, size_t len)
|
||||||
|
{
|
||||||
|
struct msm_rng_priv *priv = dev_get_priv(dev);
|
||||||
|
size_t currsize = 0;
|
||||||
|
u32 *retdata = data;
|
||||||
|
size_t maxsize;
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
/* calculate max size bytes to transfer back to caller */
|
||||||
|
maxsize = min_t(size_t, MAX_HW_FIFO_SIZE, len);
|
||||||
|
|
||||||
|
/* read random data from hardware */
|
||||||
|
do {
|
||||||
|
val = readl_relaxed(priv->base + PRNG_STATUS);
|
||||||
|
if (!(val & PRNG_STATUS_DATA_AVAIL))
|
||||||
|
break;
|
||||||
|
|
||||||
|
val = readl_relaxed(priv->base + PRNG_DATA_OUT);
|
||||||
|
if (!val)
|
||||||
|
break;
|
||||||
|
|
||||||
|
*retdata++ = val;
|
||||||
|
currsize += WORD_SZ;
|
||||||
|
|
||||||
|
/* make sure we stay on 32bit boundary */
|
||||||
|
if ((maxsize - currsize) < WORD_SZ)
|
||||||
|
break;
|
||||||
|
} while (currsize < maxsize);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int msm_rng_enable(struct msm_rng_priv *priv, int enable)
|
||||||
|
{
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
if (enable) {
|
||||||
|
/* Enable PRNG only if it is not already enabled */
|
||||||
|
val = readl_relaxed(priv->base + PRNG_CONFIG);
|
||||||
|
if (val & PRNG_CONFIG_HW_ENABLE) {
|
||||||
|
val = readl_relaxed(priv->base + PRNG_LFSR_CFG);
|
||||||
|
val &= ~PRNG_LFSR_CFG_MASK;
|
||||||
|
val |= PRNG_LFSR_CFG_CLOCKS;
|
||||||
|
writel(val, priv->base + PRNG_LFSR_CFG);
|
||||||
|
|
||||||
|
val = readl_relaxed(priv->base + PRNG_CONFIG);
|
||||||
|
val |= PRNG_CONFIG_HW_ENABLE;
|
||||||
|
writel(val, priv->base + PRNG_CONFIG);
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
val = readl_relaxed(priv->base + PRNG_CONFIG);
|
||||||
|
val &= ~PRNG_CONFIG_HW_ENABLE;
|
||||||
|
writel(val, priv->base + PRNG_CONFIG);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int msm_rng_probe(struct udevice *dev)
|
||||||
|
{
|
||||||
|
struct msm_rng_priv *priv = dev_get_priv(dev);
|
||||||
|
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
priv->base = dev_read_addr(dev);
|
||||||
|
if (priv->base == FDT_ADDR_T_NONE)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
ret = clk_get_by_index(dev, 0, &priv->clk);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
ret = clk_enable(&priv->clk);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
return msm_rng_enable(priv, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int msm_rng_remove(struct udevice *dev)
|
||||||
|
{
|
||||||
|
struct msm_rng_priv *priv = dev_get_priv(dev);
|
||||||
|
|
||||||
|
return msm_rng_enable(priv, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct dm_rng_ops msm_rng_ops = {
|
||||||
|
.read = msm_rng_read,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct udevice_id msm_rng_match[] = {
|
||||||
|
{ .compatible = "qcom,prng", },
|
||||||
|
{},
|
||||||
|
};
|
||||||
|
|
||||||
|
U_BOOT_DRIVER(msm_rng) = {
|
||||||
|
.name = "msm-rng",
|
||||||
|
.id = UCLASS_RNG,
|
||||||
|
.of_match = msm_rng_match,
|
||||||
|
.ops = &msm_rng_ops,
|
||||||
|
.probe = msm_rng_probe,
|
||||||
|
.remove = msm_rng_remove,
|
||||||
|
.priv_auto_alloc_size = sizeof(struct msm_rng_priv),
|
||||||
|
};
|
@ -75,6 +75,12 @@ config RTC_ISL1208
|
|||||||
This driver supports reading and writing the RTC/calendar and detects
|
This driver supports reading and writing the RTC/calendar and detects
|
||||||
total power failures.
|
total power failures.
|
||||||
|
|
||||||
|
config RTC_PCF8563
|
||||||
|
tristate "Philips PCF8563"
|
||||||
|
help
|
||||||
|
If you say yes here you get support for the Philips PCF8563 RTC
|
||||||
|
and compatible chips.
|
||||||
|
|
||||||
config RTC_RV3029
|
config RTC_RV3029
|
||||||
bool "Enable RV3029 driver"
|
bool "Enable RV3029 driver"
|
||||||
depends on DM_RTC
|
depends on DM_RTC
|
||||||
|
@ -401,11 +401,19 @@ config DEBUG_UART_MTK
|
|||||||
driver will be available until the real driver model serial is
|
driver will be available until the real driver model serial is
|
||||||
running.
|
running.
|
||||||
|
|
||||||
|
config DEBUG_UART_XEN
|
||||||
|
bool "XEN Hypervisor Console"
|
||||||
|
depends on XEN_SERIAL
|
||||||
|
help
|
||||||
|
Select this to enable a debug UART using the serial_xen driver. You
|
||||||
|
will not have to provide any parameters to make this work. The driver
|
||||||
|
will be available until the real driver-model serial is running.
|
||||||
|
|
||||||
endchoice
|
endchoice
|
||||||
|
|
||||||
config DEBUG_UART_BASE
|
config DEBUG_UART_BASE
|
||||||
hex "Base address of UART"
|
hex "Base address of UART"
|
||||||
depends on DEBUG_UART
|
depends on DEBUG_UART && !DEBUG_UART_XEN
|
||||||
default 0 if DEBUG_UART_SANDBOX
|
default 0 if DEBUG_UART_SANDBOX
|
||||||
help
|
help
|
||||||
This is the base address of your UART for memory-mapped UARTs.
|
This is the base address of your UART for memory-mapped UARTs.
|
||||||
@ -415,7 +423,7 @@ config DEBUG_UART_BASE
|
|||||||
|
|
||||||
config DEBUG_UART_CLOCK
|
config DEBUG_UART_CLOCK
|
||||||
int "UART input clock"
|
int "UART input clock"
|
||||||
depends on DEBUG_UART
|
depends on DEBUG_UART && !DEBUG_UART_XEN
|
||||||
default 0 if DEBUG_UART_SANDBOX
|
default 0 if DEBUG_UART_SANDBOX
|
||||||
help
|
help
|
||||||
The UART input clock determines the speed of the internal UART
|
The UART input clock determines the speed of the internal UART
|
||||||
@ -427,7 +435,7 @@ config DEBUG_UART_CLOCK
|
|||||||
|
|
||||||
config DEBUG_UART_SHIFT
|
config DEBUG_UART_SHIFT
|
||||||
int "UART register shift"
|
int "UART register shift"
|
||||||
depends on DEBUG_UART
|
depends on DEBUG_UART && !DEBUG_UART_XEN
|
||||||
default 0 if DEBUG_UART
|
default 0 if DEBUG_UART
|
||||||
help
|
help
|
||||||
Some UARTs (notably ns16550) support different register layouts
|
Some UARTs (notably ns16550) support different register layouts
|
||||||
|
@ -413,7 +413,7 @@ static int on_baudrate(const char *name, const char *value, enum env_op op,
|
|||||||
|
|
||||||
if ((flags & H_INTERACTIVE) != 0)
|
if ((flags & H_INTERACTIVE) != 0)
|
||||||
while (1) {
|
while (1) {
|
||||||
if (getc() == '\r')
|
if (getchar() == '\r')
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -90,7 +90,7 @@ static int on_baudrate(const char *name, const char *value, enum env_op op,
|
|||||||
|
|
||||||
if ((flags & H_INTERACTIVE) != 0)
|
if ((flags & H_INTERACTIVE) != 0)
|
||||||
while (1) {
|
while (1) {
|
||||||
if (getc() == '\r')
|
if (getchar() == '\r')
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -5,6 +5,7 @@
|
|||||||
*/
|
*/
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <cpu_func.h>
|
#include <cpu_func.h>
|
||||||
|
#include <debug_uart.h>
|
||||||
#include <dm.h>
|
#include <dm.h>
|
||||||
#include <serial.h>
|
#include <serial.h>
|
||||||
#include <watchdog.h>
|
#include <watchdog.h>
|
||||||
@ -15,11 +16,14 @@
|
|||||||
#include <xen/events.h>
|
#include <xen/events.h>
|
||||||
|
|
||||||
#include <xen/interface/sched.h>
|
#include <xen/interface/sched.h>
|
||||||
|
#include <xen/interface/xen.h>
|
||||||
#include <xen/interface/hvm/hvm_op.h>
|
#include <xen/interface/hvm/hvm_op.h>
|
||||||
#include <xen/interface/hvm/params.h>
|
#include <xen/interface/hvm/params.h>
|
||||||
#include <xen/interface/io/console.h>
|
#include <xen/interface/io/console.h>
|
||||||
#include <xen/interface/io/ring.h>
|
#include <xen/interface/io/ring.h>
|
||||||
|
|
||||||
|
#include <asm/xen/hypercall.h>
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
u32 console_evtchn;
|
u32 console_evtchn;
|
||||||
@ -175,8 +179,22 @@ U_BOOT_DRIVER(serial_xen) = {
|
|||||||
.priv_auto_alloc_size = sizeof(struct xen_uart_priv),
|
.priv_auto_alloc_size = sizeof(struct xen_uart_priv),
|
||||||
.probe = xen_serial_probe,
|
.probe = xen_serial_probe,
|
||||||
.ops = &xen_serial_ops,
|
.ops = &xen_serial_ops,
|
||||||
#if !CONFIG_IS_ENABLED(OF_CONTROL)
|
|
||||||
.flags = DM_FLAG_PRE_RELOC,
|
.flags = DM_FLAG_PRE_RELOC,
|
||||||
#endif
|
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#if defined(CONFIG_DEBUG_UART_XEN)
|
||||||
|
static inline void _debug_uart_init(void) {}
|
||||||
|
|
||||||
|
static inline void _debug_uart_putc(int c)
|
||||||
|
{
|
||||||
|
#if CONFIG_IS_ENABLED(ARM)
|
||||||
|
xen_debug_putc(c);
|
||||||
|
#else
|
||||||
|
/* the type cast should work on LE only */
|
||||||
|
HYPERVISOR_console_io(CONSOLEIO_write, 1, (char *)&ch);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
DEBUG_UART_FUNCS
|
||||||
|
|
||||||
|
#endif
|
||||||
|
@ -271,6 +271,16 @@ config PL022_SPI
|
|||||||
controller. If you have an embedded system with an AMBA(R)
|
controller. If you have an embedded system with an AMBA(R)
|
||||||
bus and a PL022 controller, say Y or M here.
|
bus and a PL022 controller, say Y or M here.
|
||||||
|
|
||||||
|
config SPI_QUP
|
||||||
|
bool "Qualcomm SPI controller with QUP interface"
|
||||||
|
depends on ARCH_IPQ40XX
|
||||||
|
help
|
||||||
|
Qualcomm Universal Peripheral (QUP) core is an AHB slave that
|
||||||
|
provides a common data path (an output FIFO and an input FIFO)
|
||||||
|
for serial peripheral interface (SPI) mini-core. SPI in master
|
||||||
|
mode supports up to 50MHz, up to four chip selects, programmable
|
||||||
|
data path from 4 bits to 32 bits and numerous protocol variants.
|
||||||
|
|
||||||
config RENESAS_RPC_SPI
|
config RENESAS_RPC_SPI
|
||||||
bool "Renesas RPC SPI driver"
|
bool "Renesas RPC SPI driver"
|
||||||
depends on RCAR_GEN3 || RZA1
|
depends on RCAR_GEN3 || RZA1
|
||||||
|
@ -47,6 +47,7 @@ obj-$(CONFIG_OCTEON_SPI) += octeon_spi.o
|
|||||||
obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
|
obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
|
||||||
obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
|
obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
|
||||||
obj-$(CONFIG_PL022_SPI) += pl022_spi.o
|
obj-$(CONFIG_PL022_SPI) += pl022_spi.o
|
||||||
|
obj-$(CONFIG_SPI_QUP) += spi-qup.o
|
||||||
obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
|
obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
|
||||||
obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
|
obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
|
||||||
obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
|
obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
|
||||||
|
803
drivers/spi/spi-qup.c
Normal file
803
drivers/spi/spi-qup.c
Normal file
@ -0,0 +1,803 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* Driver for Qualcomm QUP SPI controller
|
||||||
|
* FIFO and Block modes supported, no DMA
|
||||||
|
* mode support
|
||||||
|
*
|
||||||
|
* Copyright (c) 2020 Sartura Ltd.
|
||||||
|
*
|
||||||
|
* Author: Robert Marko <robert.marko@sartura.hr>
|
||||||
|
* Author: Luka Kovacic <luka.kovacic@sartura.hr>
|
||||||
|
*
|
||||||
|
* Based on stock U-boot and Linux drivers
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <asm/gpio.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <clk.h>
|
||||||
|
#include <common.h>
|
||||||
|
#include <dm.h>
|
||||||
|
#include <errno.h>
|
||||||
|
#include <linux/delay.h>
|
||||||
|
#include <spi.h>
|
||||||
|
|
||||||
|
#define QUP_CONFIG 0x0000
|
||||||
|
#define QUP_STATE 0x0004
|
||||||
|
#define QUP_IO_M_MODES 0x0008
|
||||||
|
#define QUP_SW_RESET 0x000c
|
||||||
|
#define QUP_OPERATIONAL 0x0018
|
||||||
|
#define QUP_ERROR_FLAGS 0x001c
|
||||||
|
#define QUP_ERROR_FLAGS_EN 0x0020
|
||||||
|
#define QUP_OPERATIONAL_MASK 0x0028
|
||||||
|
#define QUP_HW_VERSION 0x0030
|
||||||
|
#define QUP_MX_OUTPUT_CNT 0x0100
|
||||||
|
#define QUP_OUTPUT_FIFO 0x0110
|
||||||
|
#define QUP_MX_WRITE_CNT 0x0150
|
||||||
|
#define QUP_MX_INPUT_CNT 0x0200
|
||||||
|
#define QUP_MX_READ_CNT 0x0208
|
||||||
|
#define QUP_INPUT_FIFO 0x0218
|
||||||
|
|
||||||
|
#define SPI_CONFIG 0x0300
|
||||||
|
#define SPI_IO_CONTROL 0x0304
|
||||||
|
#define SPI_ERROR_FLAGS 0x0308
|
||||||
|
#define SPI_ERROR_FLAGS_EN 0x030c
|
||||||
|
|
||||||
|
/* QUP_CONFIG fields */
|
||||||
|
#define QUP_CONFIG_SPI_MODE BIT(8)
|
||||||
|
#define QUP_CONFIG_CLOCK_AUTO_GATE BIT(13)
|
||||||
|
#define QUP_CONFIG_NO_INPUT BIT(7)
|
||||||
|
#define QUP_CONFIG_NO_OUTPUT BIT(6)
|
||||||
|
#define QUP_CONFIG_N 0x001f
|
||||||
|
|
||||||
|
/* QUP_STATE fields */
|
||||||
|
#define QUP_STATE_VALID BIT(2)
|
||||||
|
#define QUP_STATE_RESET 0
|
||||||
|
#define QUP_STATE_RUN 1
|
||||||
|
#define QUP_STATE_PAUSE 3
|
||||||
|
#define QUP_STATE_MASK 3
|
||||||
|
#define QUP_STATE_CLEAR 2
|
||||||
|
|
||||||
|
/* QUP_IO_M_MODES fields */
|
||||||
|
#define QUP_IO_M_PACK_EN BIT(15)
|
||||||
|
#define QUP_IO_M_UNPACK_EN BIT(14)
|
||||||
|
#define QUP_IO_M_INPUT_MODE_MASK_SHIFT 12
|
||||||
|
#define QUP_IO_M_OUTPUT_MODE_MASK_SHIFT 10
|
||||||
|
#define QUP_IO_M_INPUT_MODE_MASK (3 << QUP_IO_M_INPUT_MODE_MASK_SHIFT)
|
||||||
|
#define QUP_IO_M_OUTPUT_MODE_MASK (3 << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT)
|
||||||
|
|
||||||
|
#define QUP_IO_M_OUTPUT_BLOCK_SIZE(x) (((x) & (0x03 << 0)) >> 0)
|
||||||
|
#define QUP_IO_M_OUTPUT_FIFO_SIZE(x) (((x) & (0x07 << 2)) >> 2)
|
||||||
|
#define QUP_IO_M_INPUT_BLOCK_SIZE(x) (((x) & (0x03 << 5)) >> 5)
|
||||||
|
#define QUP_IO_M_INPUT_FIFO_SIZE(x) (((x) & (0x07 << 7)) >> 7)
|
||||||
|
|
||||||
|
#define QUP_IO_M_MODE_FIFO 0
|
||||||
|
#define QUP_IO_M_MODE_BLOCK 1
|
||||||
|
#define QUP_IO_M_MODE_DMOV 2
|
||||||
|
#define QUP_IO_M_MODE_BAM 3
|
||||||
|
|
||||||
|
/* QUP_OPERATIONAL fields */
|
||||||
|
#define QUP_OP_IN_BLOCK_READ_REQ BIT(13)
|
||||||
|
#define QUP_OP_OUT_BLOCK_WRITE_REQ BIT(12)
|
||||||
|
#define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11)
|
||||||
|
#define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10)
|
||||||
|
#define QUP_OP_IN_SERVICE_FLAG BIT(9)
|
||||||
|
#define QUP_OP_OUT_SERVICE_FLAG BIT(8)
|
||||||
|
#define QUP_OP_IN_FIFO_FULL BIT(7)
|
||||||
|
#define QUP_OP_OUT_FIFO_FULL BIT(6)
|
||||||
|
#define QUP_OP_IN_FIFO_NOT_EMPTY BIT(5)
|
||||||
|
#define QUP_OP_OUT_FIFO_NOT_EMPTY BIT(4)
|
||||||
|
|
||||||
|
/* QUP_ERROR_FLAGS and QUP_ERROR_FLAGS_EN fields */
|
||||||
|
#define QUP_ERROR_OUTPUT_OVER_RUN BIT(5)
|
||||||
|
#define QUP_ERROR_INPUT_UNDER_RUN BIT(4)
|
||||||
|
#define QUP_ERROR_OUTPUT_UNDER_RUN BIT(3)
|
||||||
|
#define QUP_ERROR_INPUT_OVER_RUN BIT(2)
|
||||||
|
|
||||||
|
/* SPI_CONFIG fields */
|
||||||
|
#define SPI_CONFIG_HS_MODE BIT(10)
|
||||||
|
#define SPI_CONFIG_INPUT_FIRST BIT(9)
|
||||||
|
#define SPI_CONFIG_LOOPBACK BIT(8)
|
||||||
|
|
||||||
|
/* SPI_IO_CONTROL fields */
|
||||||
|
#define SPI_IO_C_FORCE_CS BIT(11)
|
||||||
|
#define SPI_IO_C_CLK_IDLE_HIGH BIT(10)
|
||||||
|
#define SPI_IO_C_MX_CS_MODE BIT(8)
|
||||||
|
#define SPI_IO_C_CS_N_POLARITY_0 BIT(4)
|
||||||
|
#define SPI_IO_C_CS_SELECT(x) (((x) & 3) << 2)
|
||||||
|
#define SPI_IO_C_CS_SELECT_MASK 0x000c
|
||||||
|
#define SPI_IO_C_TRISTATE_CS BIT(1)
|
||||||
|
#define SPI_IO_C_NO_TRI_STATE BIT(0)
|
||||||
|
|
||||||
|
/* SPI_ERROR_FLAGS and SPI_ERROR_FLAGS_EN fields */
|
||||||
|
#define SPI_ERROR_CLK_OVER_RUN BIT(1)
|
||||||
|
#define SPI_ERROR_CLK_UNDER_RUN BIT(0)
|
||||||
|
|
||||||
|
#define SPI_NUM_CHIPSELECTS 4
|
||||||
|
|
||||||
|
#define SPI_DELAY_THRESHOLD 1
|
||||||
|
#define SPI_DELAY_RETRY 10
|
||||||
|
|
||||||
|
#define SPI_RESET_STATE 0
|
||||||
|
#define SPI_RUN_STATE 1
|
||||||
|
#define SPI_CORE_RESET 0
|
||||||
|
#define SPI_CORE_RUNNING 1
|
||||||
|
|
||||||
|
#define DUMMY_DATA_VAL 0
|
||||||
|
#define TIMEOUT_CNT 100
|
||||||
|
|
||||||
|
#define QUP_STATE_VALID_BIT 2
|
||||||
|
#define QUP_CONFIG_MINI_CORE_MSK (0x0F << 8)
|
||||||
|
#define QUP_CONFIG_MINI_CORE_SPI BIT(8)
|
||||||
|
#define QUP_CONF_INPUT_MSK BIT(7)
|
||||||
|
#define QUP_CONF_INPUT_ENA (0 << 7)
|
||||||
|
#define QUP_CONF_NO_INPUT BIT(7)
|
||||||
|
#define QUP_CONF_OUTPUT_MSK BIT(6)
|
||||||
|
#define QUP_CONF_OUTPUT_ENA (0 << 6)
|
||||||
|
#define QUP_CONF_NO_OUTPUT BIT(6)
|
||||||
|
#define QUP_STATE_RUN_STATE 0x1
|
||||||
|
#define QUP_STATE_RESET_STATE 0x0
|
||||||
|
#define QUP_STATE_PAUSE_STATE 0x3
|
||||||
|
#define SPI_BIT_WORD_MSK 0x1F
|
||||||
|
#define SPI_8_BIT_WORD 0x07
|
||||||
|
#define LOOP_BACK_MSK BIT(8)
|
||||||
|
#define NO_LOOP_BACK (0 << 8)
|
||||||
|
#define SLAVE_OPERATION_MSK BIT(5)
|
||||||
|
#define SLAVE_OPERATION (0 << 5)
|
||||||
|
#define CLK_ALWAYS_ON (0 << 9)
|
||||||
|
#define MX_CS_MODE BIT(8)
|
||||||
|
#define CS_POLARITY_MASK BIT(4)
|
||||||
|
#define NO_TRI_STATE BIT(0)
|
||||||
|
#define FORCE_CS_MSK BIT(11)
|
||||||
|
#define FORCE_CS_EN BIT(11)
|
||||||
|
#define FORCE_CS_DIS (0 << 11)
|
||||||
|
#define OUTPUT_BIT_SHIFT_MSK BIT(16)
|
||||||
|
#define OUTPUT_BIT_SHIFT_EN BIT(16)
|
||||||
|
#define INPUT_BLOCK_MODE_MSK (0x03 << 12)
|
||||||
|
#define INPUT_BLOCK_MODE (0x01 << 12)
|
||||||
|
#define OUTPUT_BLOCK_MODE_MSK (0x03 << 10)
|
||||||
|
#define OUTPUT_BLOCK_MODE (0x01 << 10)
|
||||||
|
#define INPUT_BAM_MODE (0x3 << 12)
|
||||||
|
#define OUTPUT_BAM_MODE (0x3 << 10)
|
||||||
|
#define PACK_EN (0x1 << 15)
|
||||||
|
#define UNPACK_EN (0x1 << 14)
|
||||||
|
#define PACK_EN_MSK (0x1 << 15)
|
||||||
|
#define UNPACK_EN_MSK (0x1 << 14)
|
||||||
|
#define OUTPUT_SERVICE_MSK (0x1 << 8)
|
||||||
|
#define INPUT_SERVICE_MSK (0x1 << 9)
|
||||||
|
#define OUTPUT_SERVICE_DIS (0x1 << 8)
|
||||||
|
#define INPUT_SERVICE_DIS (0x1 << 9)
|
||||||
|
#define BLSP0_SPI_DEASSERT_WAIT_REG 0x0310
|
||||||
|
#define QUP_DATA_AVAILABLE_FOR_READ BIT(5)
|
||||||
|
#define SPI_INPUT_BLOCK_SIZE 4
|
||||||
|
#define SPI_OUTPUT_BLOCK_SIZE 4
|
||||||
|
#define SPI_BITLEN_MSK 0x07
|
||||||
|
#define MAX_COUNT_SIZE 0xffff
|
||||||
|
|
||||||
|
struct qup_spi_priv {
|
||||||
|
phys_addr_t base;
|
||||||
|
struct clk clk;
|
||||||
|
u32 num_cs;
|
||||||
|
struct gpio_desc cs_gpios[SPI_NUM_CHIPSELECTS];
|
||||||
|
bool cs_high;
|
||||||
|
u32 core_state;
|
||||||
|
};
|
||||||
|
|
||||||
|
static int qup_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
|
||||||
|
{
|
||||||
|
struct qup_spi_priv *priv = dev_get_priv(dev);
|
||||||
|
|
||||||
|
debug("%s: cs=%d enable=%d\n", __func__, cs, enable);
|
||||||
|
|
||||||
|
if (cs >= SPI_NUM_CHIPSELECTS)
|
||||||
|
return -ENODEV;
|
||||||
|
|
||||||
|
if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
if (priv->cs_high)
|
||||||
|
enable = !enable;
|
||||||
|
|
||||||
|
return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Function to write data to OUTPUT FIFO
|
||||||
|
*/
|
||||||
|
static void qup_spi_write_byte(struct udevice *dev, unsigned char data)
|
||||||
|
{
|
||||||
|
struct udevice *bus = dev_get_parent(dev);
|
||||||
|
struct qup_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
/* Wait for space in the FIFO */
|
||||||
|
while ((readl(priv->base + QUP_OPERATIONAL) & QUP_OP_OUT_FIFO_FULL))
|
||||||
|
udelay(1);
|
||||||
|
|
||||||
|
/* Write the byte of data */
|
||||||
|
writel(data, priv->base + QUP_OUTPUT_FIFO);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Function to read data from Input FIFO
|
||||||
|
*/
|
||||||
|
static unsigned char qup_spi_read_byte(struct udevice *dev)
|
||||||
|
{
|
||||||
|
struct udevice *bus = dev_get_parent(dev);
|
||||||
|
struct qup_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
/* Wait for Data in FIFO */
|
||||||
|
while (!(readl(priv->base + QUP_OPERATIONAL) & QUP_DATA_AVAILABLE_FOR_READ)) {
|
||||||
|
printf("Stuck at FIFO data wait\n");
|
||||||
|
udelay(1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Read a byte of data */
|
||||||
|
return readl(priv->base + QUP_INPUT_FIFO) & 0xff;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Function to check wheather Input or Output FIFO
|
||||||
|
* has data to be serviced
|
||||||
|
*/
|
||||||
|
static int qup_spi_check_fifo_status(struct udevice *dev, u32 reg_addr)
|
||||||
|
{
|
||||||
|
struct udevice *bus = dev_get_parent(dev);
|
||||||
|
struct qup_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
unsigned int count = TIMEOUT_CNT;
|
||||||
|
unsigned int status_flag;
|
||||||
|
unsigned int val;
|
||||||
|
|
||||||
|
do {
|
||||||
|
val = readl(priv->base + reg_addr);
|
||||||
|
count--;
|
||||||
|
if (count == 0)
|
||||||
|
return -ETIMEDOUT;
|
||||||
|
|
||||||
|
status_flag = ((val & QUP_OP_OUT_SERVICE_FLAG) | (val & QUP_OP_IN_SERVICE_FLAG));
|
||||||
|
} while (!status_flag);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Function to configure Input and Output enable/disable
|
||||||
|
*/
|
||||||
|
static void qup_spi_enable_io_config(struct udevice *dev, u32 write_cnt, u32 read_cnt)
|
||||||
|
{
|
||||||
|
struct udevice *bus = dev_get_parent(dev);
|
||||||
|
struct qup_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
|
||||||
|
if (write_cnt) {
|
||||||
|
clrsetbits_le32(priv->base + QUP_CONFIG,
|
||||||
|
QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA);
|
||||||
|
} else {
|
||||||
|
clrsetbits_le32(priv->base + QUP_CONFIG,
|
||||||
|
QUP_CONF_OUTPUT_MSK, QUP_CONF_NO_OUTPUT);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (read_cnt) {
|
||||||
|
clrsetbits_le32(priv->base + QUP_CONFIG,
|
||||||
|
QUP_CONF_INPUT_MSK, QUP_CONF_INPUT_ENA);
|
||||||
|
} else {
|
||||||
|
clrsetbits_le32(priv->base + QUP_CONFIG,
|
||||||
|
QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static int check_bit_state(struct udevice *dev, u32 reg_addr, int bit_num, int val,
|
||||||
|
int us_delay)
|
||||||
|
{
|
||||||
|
struct udevice *bus = dev_get_parent(dev);
|
||||||
|
struct qup_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
unsigned int count = TIMEOUT_CNT;
|
||||||
|
unsigned int bit_val = ((readl(priv->base + reg_addr) >> bit_num) & 0x01);
|
||||||
|
|
||||||
|
while (bit_val != val) {
|
||||||
|
count--;
|
||||||
|
if (count == 0)
|
||||||
|
return -ETIMEDOUT;
|
||||||
|
udelay(us_delay);
|
||||||
|
bit_val = ((readl(priv->base + reg_addr) >> bit_num) & 0x01);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Check whether QUPn State is valid
|
||||||
|
*/
|
||||||
|
static int check_qup_state_valid(struct udevice *dev)
|
||||||
|
{
|
||||||
|
return check_bit_state(dev, QUP_STATE, QUP_STATE_VALID, 1, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configure QUPn Core state
|
||||||
|
*/
|
||||||
|
static int qup_spi_config_spi_state(struct udevice *dev, unsigned int state)
|
||||||
|
{
|
||||||
|
struct udevice *bus = dev_get_parent(dev);
|
||||||
|
struct qup_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
u32 val;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = check_qup_state_valid(dev);
|
||||||
|
if (ret != 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
switch (state) {
|
||||||
|
case SPI_RUN_STATE:
|
||||||
|
/* Set the state to RUN */
|
||||||
|
val = ((readl(priv->base + QUP_STATE) & ~QUP_STATE_MASK)
|
||||||
|
| QUP_STATE_RUN);
|
||||||
|
writel(val, priv->base + QUP_STATE);
|
||||||
|
ret = check_qup_state_valid(dev);
|
||||||
|
if (ret != 0)
|
||||||
|
return ret;
|
||||||
|
priv->core_state = SPI_CORE_RUNNING;
|
||||||
|
break;
|
||||||
|
case SPI_RESET_STATE:
|
||||||
|
/* Set the state to RESET */
|
||||||
|
val = ((readl(priv->base + QUP_STATE) & ~QUP_STATE_MASK)
|
||||||
|
| QUP_STATE_RESET);
|
||||||
|
writel(val, priv->base + QUP_STATE);
|
||||||
|
ret = check_qup_state_valid(dev);
|
||||||
|
if (ret != 0)
|
||||||
|
return ret;
|
||||||
|
priv->core_state = SPI_CORE_RESET;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
printf("Unsupported QUP SPI state: %d\n", state);
|
||||||
|
ret = -EINVAL;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Function to read bytes number of data from the Input FIFO
|
||||||
|
*/
|
||||||
|
static int __qup_spi_blsp_spi_read(struct udevice *dev, u8 *data_buffer, unsigned int bytes)
|
||||||
|
{
|
||||||
|
struct udevice *bus = dev_get_parent(dev);
|
||||||
|
struct qup_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
u32 val;
|
||||||
|
unsigned int i;
|
||||||
|
unsigned int read_bytes = bytes;
|
||||||
|
unsigned int fifo_count;
|
||||||
|
int ret = 0;
|
||||||
|
int state_config;
|
||||||
|
|
||||||
|
/* Configure no of bytes to read */
|
||||||
|
state_config = qup_spi_config_spi_state(dev, SPI_RESET_STATE);
|
||||||
|
if (state_config)
|
||||||
|
return state_config;
|
||||||
|
|
||||||
|
/* Configure input and output enable */
|
||||||
|
qup_spi_enable_io_config(dev, 0, read_bytes);
|
||||||
|
|
||||||
|
writel(bytes, priv->base + QUP_MX_INPUT_CNT);
|
||||||
|
|
||||||
|
state_config = qup_spi_config_spi_state(dev, SPI_RUN_STATE);
|
||||||
|
if (state_config)
|
||||||
|
return state_config;
|
||||||
|
|
||||||
|
while (read_bytes) {
|
||||||
|
ret = qup_spi_check_fifo_status(dev, QUP_OPERATIONAL);
|
||||||
|
if (ret != 0)
|
||||||
|
goto out;
|
||||||
|
|
||||||
|
val = readl(priv->base + QUP_OPERATIONAL);
|
||||||
|
if (val & QUP_OP_IN_SERVICE_FLAG) {
|
||||||
|
/*
|
||||||
|
* acknowledge to hw that software will
|
||||||
|
* read input data
|
||||||
|
*/
|
||||||
|
val &= QUP_OP_IN_SERVICE_FLAG;
|
||||||
|
writel(val, priv->base + QUP_OPERATIONAL);
|
||||||
|
|
||||||
|
fifo_count = ((read_bytes > SPI_INPUT_BLOCK_SIZE) ?
|
||||||
|
SPI_INPUT_BLOCK_SIZE : read_bytes);
|
||||||
|
|
||||||
|
for (i = 0; i < fifo_count; i++) {
|
||||||
|
*data_buffer = qup_spi_read_byte(dev);
|
||||||
|
data_buffer++;
|
||||||
|
read_bytes--;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
out:
|
||||||
|
/*
|
||||||
|
* Put the SPI Core back in the Reset State
|
||||||
|
* to end the transfer
|
||||||
|
*/
|
||||||
|
(void)qup_spi_config_spi_state(dev, SPI_RESET_STATE);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qup_spi_blsp_spi_read(struct udevice *dev, u8 *data_buffer, unsigned int bytes)
|
||||||
|
{
|
||||||
|
int length, ret;
|
||||||
|
|
||||||
|
while (bytes) {
|
||||||
|
length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE;
|
||||||
|
|
||||||
|
ret = __qup_spi_blsp_spi_read(dev, data_buffer, length);
|
||||||
|
if (ret != 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
data_buffer += length;
|
||||||
|
bytes -= length;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Function to write data to the Output FIFO
|
||||||
|
*/
|
||||||
|
static int __qup_blsp_spi_write(struct udevice *dev, const u8 *cmd_buffer, unsigned int bytes)
|
||||||
|
{
|
||||||
|
struct udevice *bus = dev_get_parent(dev);
|
||||||
|
struct qup_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
u32 val;
|
||||||
|
unsigned int i;
|
||||||
|
unsigned int write_len = bytes;
|
||||||
|
unsigned int read_len = bytes;
|
||||||
|
unsigned int fifo_count;
|
||||||
|
int ret = 0;
|
||||||
|
int state_config;
|
||||||
|
|
||||||
|
state_config = qup_spi_config_spi_state(dev, SPI_RESET_STATE);
|
||||||
|
if (state_config)
|
||||||
|
return state_config;
|
||||||
|
|
||||||
|
writel(bytes, priv->base + QUP_MX_OUTPUT_CNT);
|
||||||
|
writel(bytes, priv->base + QUP_MX_INPUT_CNT);
|
||||||
|
state_config = qup_spi_config_spi_state(dev, SPI_RUN_STATE);
|
||||||
|
if (state_config)
|
||||||
|
return state_config;
|
||||||
|
|
||||||
|
/* Configure input and output enable */
|
||||||
|
qup_spi_enable_io_config(dev, write_len, read_len);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* read_len considered to ensure that we read the dummy data for the
|
||||||
|
* write we performed. This is needed to ensure with WR-RD transaction
|
||||||
|
* to get the actual data on the subsequent read cycle that happens
|
||||||
|
*/
|
||||||
|
while (write_len || read_len) {
|
||||||
|
ret = qup_spi_check_fifo_status(dev, QUP_OPERATIONAL);
|
||||||
|
if (ret != 0)
|
||||||
|
goto out;
|
||||||
|
|
||||||
|
val = readl(priv->base + QUP_OPERATIONAL);
|
||||||
|
if (val & QUP_OP_OUT_SERVICE_FLAG) {
|
||||||
|
/*
|
||||||
|
* acknowledge to hw that software will write
|
||||||
|
* expected output data
|
||||||
|
*/
|
||||||
|
val &= QUP_OP_OUT_SERVICE_FLAG;
|
||||||
|
writel(val, priv->base + QUP_OPERATIONAL);
|
||||||
|
|
||||||
|
if (write_len > SPI_OUTPUT_BLOCK_SIZE)
|
||||||
|
fifo_count = SPI_OUTPUT_BLOCK_SIZE;
|
||||||
|
else
|
||||||
|
fifo_count = write_len;
|
||||||
|
|
||||||
|
for (i = 0; i < fifo_count; i++) {
|
||||||
|
/* Write actual data to output FIFO */
|
||||||
|
qup_spi_write_byte(dev, *cmd_buffer);
|
||||||
|
cmd_buffer++;
|
||||||
|
write_len--;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (val & QUP_OP_IN_SERVICE_FLAG) {
|
||||||
|
/*
|
||||||
|
* acknowledge to hw that software
|
||||||
|
* will read input data
|
||||||
|
*/
|
||||||
|
val &= QUP_OP_IN_SERVICE_FLAG;
|
||||||
|
writel(val, priv->base + QUP_OPERATIONAL);
|
||||||
|
|
||||||
|
if (read_len > SPI_INPUT_BLOCK_SIZE)
|
||||||
|
fifo_count = SPI_INPUT_BLOCK_SIZE;
|
||||||
|
else
|
||||||
|
fifo_count = read_len;
|
||||||
|
|
||||||
|
for (i = 0; i < fifo_count; i++) {
|
||||||
|
/* Read dummy data for the data written */
|
||||||
|
(void)qup_spi_read_byte(dev);
|
||||||
|
|
||||||
|
/* Decrement the write count after reading the
|
||||||
|
* dummy data from the device. This is to make
|
||||||
|
* sure we read dummy data before we write the
|
||||||
|
* data to fifo
|
||||||
|
*/
|
||||||
|
read_len--;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
out:
|
||||||
|
/*
|
||||||
|
* Put the SPI Core back in the Reset State
|
||||||
|
* to end the transfer
|
||||||
|
*/
|
||||||
|
(void)qup_spi_config_spi_state(dev, SPI_RESET_STATE);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qup_spi_blsp_spi_write(struct udevice *dev, const u8 *cmd_buffer, unsigned int bytes)
|
||||||
|
{
|
||||||
|
int length, ret;
|
||||||
|
|
||||||
|
while (bytes) {
|
||||||
|
length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE;
|
||||||
|
|
||||||
|
ret = __qup_blsp_spi_write(dev, cmd_buffer, length);
|
||||||
|
if (ret != 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
cmd_buffer += length;
|
||||||
|
bytes -= length;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qup_spi_set_speed(struct udevice *dev, uint speed)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qup_spi_set_mode(struct udevice *dev, uint mode)
|
||||||
|
{
|
||||||
|
struct qup_spi_priv *priv = dev_get_priv(dev);
|
||||||
|
unsigned int clk_idle_state;
|
||||||
|
unsigned int input_first_mode;
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
switch (mode) {
|
||||||
|
case SPI_MODE_0:
|
||||||
|
clk_idle_state = 0;
|
||||||
|
input_first_mode = SPI_CONFIG_INPUT_FIRST;
|
||||||
|
break;
|
||||||
|
case SPI_MODE_1:
|
||||||
|
clk_idle_state = 0;
|
||||||
|
input_first_mode = 0;
|
||||||
|
break;
|
||||||
|
case SPI_MODE_2:
|
||||||
|
clk_idle_state = 1;
|
||||||
|
input_first_mode = SPI_CONFIG_INPUT_FIRST;
|
||||||
|
break;
|
||||||
|
case SPI_MODE_3:
|
||||||
|
clk_idle_state = 1;
|
||||||
|
input_first_mode = 0;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
printf("Unsupported spi mode: %d\n", mode);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (mode & SPI_CS_HIGH)
|
||||||
|
priv->cs_high = true;
|
||||||
|
else
|
||||||
|
priv->cs_high = false;
|
||||||
|
|
||||||
|
val = readl(priv->base + SPI_CONFIG);
|
||||||
|
val |= input_first_mode;
|
||||||
|
writel(val, priv->base + SPI_CONFIG);
|
||||||
|
|
||||||
|
val = readl(priv->base + SPI_IO_CONTROL);
|
||||||
|
if (clk_idle_state)
|
||||||
|
val |= SPI_IO_C_CLK_IDLE_HIGH;
|
||||||
|
else
|
||||||
|
val &= ~SPI_IO_C_CLK_IDLE_HIGH;
|
||||||
|
|
||||||
|
writel(val, priv->base + SPI_IO_CONTROL);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void qup_spi_reset(struct udevice *dev)
|
||||||
|
{
|
||||||
|
struct udevice *bus = dev_get_parent(dev);
|
||||||
|
struct qup_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
|
||||||
|
/* Driver may not be probed yet */
|
||||||
|
if (!priv)
|
||||||
|
return;
|
||||||
|
|
||||||
|
writel(0x1, priv->base + QUP_SW_RESET);
|
||||||
|
udelay(5);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qup_spi_hw_init(struct udevice *dev)
|
||||||
|
{
|
||||||
|
struct udevice *bus = dev_get_parent(dev);
|
||||||
|
struct qup_spi_priv *priv = dev_get_priv(bus);
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
/* QUPn module configuration */
|
||||||
|
qup_spi_reset(dev);
|
||||||
|
|
||||||
|
/* Set the QUPn state */
|
||||||
|
ret = qup_spi_config_spi_state(dev, SPI_RESET_STATE);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configure Mini core to SPI core with Input Output enabled,
|
||||||
|
* SPI master, N = 8 bits
|
||||||
|
*/
|
||||||
|
clrsetbits_le32(priv->base + QUP_CONFIG, (QUP_CONFIG_MINI_CORE_MSK |
|
||||||
|
QUP_CONF_INPUT_MSK |
|
||||||
|
QUP_CONF_OUTPUT_MSK |
|
||||||
|
SPI_BIT_WORD_MSK),
|
||||||
|
(QUP_CONFIG_MINI_CORE_SPI |
|
||||||
|
QUP_CONF_INPUT_ENA |
|
||||||
|
QUP_CONF_OUTPUT_ENA |
|
||||||
|
SPI_8_BIT_WORD));
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configure Input first SPI protocol,
|
||||||
|
* SPI master mode and no loopback
|
||||||
|
*/
|
||||||
|
clrsetbits_le32(priv->base + SPI_CONFIG, (LOOP_BACK_MSK |
|
||||||
|
SLAVE_OPERATION_MSK),
|
||||||
|
(NO_LOOP_BACK |
|
||||||
|
SLAVE_OPERATION));
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configure SPI IO Control Register
|
||||||
|
* CLK_ALWAYS_ON = 0
|
||||||
|
* MX_CS_MODE = 0
|
||||||
|
* NO_TRI_STATE = 1
|
||||||
|
*/
|
||||||
|
writel((CLK_ALWAYS_ON | NO_TRI_STATE), priv->base + SPI_IO_CONTROL);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configure SPI IO Modes.
|
||||||
|
* OUTPUT_BIT_SHIFT_EN = 1
|
||||||
|
* INPUT_MODE = Block Mode
|
||||||
|
* OUTPUT MODE = Block Mode
|
||||||
|
*/
|
||||||
|
|
||||||
|
clrsetbits_le32(priv->base + QUP_IO_M_MODES, (OUTPUT_BIT_SHIFT_MSK |
|
||||||
|
INPUT_BLOCK_MODE_MSK |
|
||||||
|
OUTPUT_BLOCK_MODE_MSK),
|
||||||
|
(OUTPUT_BIT_SHIFT_EN |
|
||||||
|
INPUT_BLOCK_MODE |
|
||||||
|
OUTPUT_BLOCK_MODE));
|
||||||
|
|
||||||
|
/* Disable Error mask */
|
||||||
|
writel(0, priv->base + SPI_ERROR_FLAGS_EN);
|
||||||
|
writel(0, priv->base + QUP_ERROR_FLAGS_EN);
|
||||||
|
writel(0, priv->base + BLSP0_SPI_DEASSERT_WAIT_REG);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qup_spi_claim_bus(struct udevice *dev)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = qup_spi_hw_init(dev);
|
||||||
|
if (ret)
|
||||||
|
return -EIO;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qup_spi_release_bus(struct udevice *dev)
|
||||||
|
{
|
||||||
|
/* Reset the SPI hardware */
|
||||||
|
qup_spi_reset(dev);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qup_spi_xfer(struct udevice *dev, unsigned int bitlen,
|
||||||
|
const void *dout, void *din, unsigned long flags)
|
||||||
|
{
|
||||||
|
struct udevice *bus = dev_get_parent(dev);
|
||||||
|
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
|
||||||
|
unsigned int len;
|
||||||
|
const u8 *txp = dout;
|
||||||
|
u8 *rxp = din;
|
||||||
|
int ret = 0;
|
||||||
|
|
||||||
|
if (bitlen & SPI_BITLEN_MSK) {
|
||||||
|
printf("Invalid bit length\n");
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
len = bitlen >> 3;
|
||||||
|
|
||||||
|
if (flags & SPI_XFER_BEGIN) {
|
||||||
|
ret = qup_spi_hw_init(dev);
|
||||||
|
if (ret != 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
ret = qup_spi_set_cs(bus, slave_plat->cs, false);
|
||||||
|
if (ret != 0)
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (dout != NULL) {
|
||||||
|
ret = qup_spi_blsp_spi_write(dev, txp, len);
|
||||||
|
if (ret != 0)
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (din != NULL) {
|
||||||
|
ret = qup_spi_blsp_spi_read(dev, rxp, len);
|
||||||
|
if (ret != 0)
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (flags & SPI_XFER_END) {
|
||||||
|
ret = qup_spi_set_cs(bus, slave_plat->cs, true);
|
||||||
|
if (ret != 0)
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qup_spi_probe(struct udevice *dev)
|
||||||
|
{
|
||||||
|
struct qup_spi_priv *priv = dev_get_priv(dev);
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
priv->base = dev_read_addr(dev);
|
||||||
|
if (priv->base == FDT_ADDR_T_NONE)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
ret = clk_get_by_index(dev, 0, &priv->clk);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
ret = clk_enable(&priv->clk);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
priv->num_cs = dev_read_u32_default(dev, "num-cs", 1);
|
||||||
|
|
||||||
|
ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
|
||||||
|
priv->num_cs, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
|
||||||
|
if (ret < 0) {
|
||||||
|
printf("Can't get %s cs gpios: %d\n", dev->name, ret);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct dm_spi_ops qup_spi_ops = {
|
||||||
|
.claim_bus = qup_spi_claim_bus,
|
||||||
|
.release_bus = qup_spi_release_bus,
|
||||||
|
.xfer = qup_spi_xfer,
|
||||||
|
.set_speed = qup_spi_set_speed,
|
||||||
|
.set_mode = qup_spi_set_mode,
|
||||||
|
/*
|
||||||
|
* cs_info is not needed, since we require all chip selects to be
|
||||||
|
* in the device tree explicitly
|
||||||
|
*/
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct udevice_id qup_spi_ids[] = {
|
||||||
|
{ .compatible = "qcom,spi-qup-v1.1.1", },
|
||||||
|
{ .compatible = "qcom,spi-qup-v2.1.1", },
|
||||||
|
{ .compatible = "qcom,spi-qup-v2.2.1", },
|
||||||
|
{ }
|
||||||
|
};
|
||||||
|
|
||||||
|
U_BOOT_DRIVER(spi_qup) = {
|
||||||
|
.name = "spi_qup",
|
||||||
|
.id = UCLASS_SPI,
|
||||||
|
.of_match = qup_spi_ids,
|
||||||
|
.ops = &qup_spi_ops,
|
||||||
|
.priv_auto_alloc_size = sizeof(struct qup_spi_priv),
|
||||||
|
.probe = qup_spi_probe,
|
||||||
|
};
|
@ -62,14 +62,13 @@ struct atftmr_timer_platdata {
|
|||||||
struct atftmr_timer_regs *regs;
|
struct atftmr_timer_regs *regs;
|
||||||
};
|
};
|
||||||
|
|
||||||
static int atftmr_timer_get_count(struct udevice *dev, u64 *count)
|
static u64 atftmr_timer_get_count(struct udevice *dev)
|
||||||
{
|
{
|
||||||
struct atftmr_timer_platdata *plat = dev->platdata;
|
struct atftmr_timer_platdata *plat = dev->platdata;
|
||||||
struct atftmr_timer_regs *const regs = plat->regs;
|
struct atftmr_timer_regs *const regs = plat->regs;
|
||||||
u32 val;
|
u32 val;
|
||||||
val = readl(®s->t3_counter);
|
val = readl(®s->t3_counter);
|
||||||
*count = timer_conv_64(val);
|
return timer_conv_64(val);
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int atftmr_timer_probe(struct udevice *dev)
|
static int atftmr_timer_probe(struct udevice *dev)
|
||||||
|
@ -32,7 +32,7 @@ struct altera_timer_platdata {
|
|||||||
struct altera_timer_regs *regs;
|
struct altera_timer_regs *regs;
|
||||||
};
|
};
|
||||||
|
|
||||||
static int altera_timer_get_count(struct udevice *dev, u64 *count)
|
static u64 altera_timer_get_count(struct udevice *dev)
|
||||||
{
|
{
|
||||||
struct altera_timer_platdata *plat = dev->platdata;
|
struct altera_timer_platdata *plat = dev->platdata;
|
||||||
struct altera_timer_regs *const regs = plat->regs;
|
struct altera_timer_regs *const regs = plat->regs;
|
||||||
@ -44,9 +44,7 @@ static int altera_timer_get_count(struct udevice *dev, u64 *count)
|
|||||||
/* Read timer value */
|
/* Read timer value */
|
||||||
val = readl(®s->snapl) & 0xffff;
|
val = readl(®s->snapl) & 0xffff;
|
||||||
val |= (readl(®s->snaph) & 0xffff) << 16;
|
val |= (readl(®s->snaph) & 0xffff) << 16;
|
||||||
*count = timer_conv_64(~val);
|
return timer_conv_64(~val);
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int altera_timer_probe(struct udevice *dev)
|
static int altera_timer_probe(struct udevice *dev)
|
||||||
|
@ -26,7 +26,7 @@ struct arc_timer_priv {
|
|||||||
uint timer_id;
|
uint timer_id;
|
||||||
};
|
};
|
||||||
|
|
||||||
static int arc_timer_get_count(struct udevice *dev, u64 *count)
|
static u64 arc_timer_get_count(struct udevice *dev)
|
||||||
{
|
{
|
||||||
u32 val = 0;
|
u32 val = 0;
|
||||||
struct arc_timer_priv *priv = dev_get_priv(dev);
|
struct arc_timer_priv *priv = dev_get_priv(dev);
|
||||||
@ -39,9 +39,7 @@ static int arc_timer_get_count(struct udevice *dev, u64 *count)
|
|||||||
val = read_aux_reg(ARC_AUX_TIMER1_CNT);
|
val = read_aux_reg(ARC_AUX_TIMER1_CNT);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
*count = timer_conv_64(val);
|
return timer_conv_64(val);
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int arc_timer_probe(struct udevice *dev)
|
static int arc_timer_probe(struct udevice *dev)
|
||||||
|
@ -51,13 +51,11 @@ static int ast_timer_probe(struct udevice *dev)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int ast_timer_get_count(struct udevice *dev, u64 *count)
|
static u64 ast_timer_get_count(struct udevice *dev)
|
||||||
{
|
{
|
||||||
struct ast_timer_priv *priv = dev_get_priv(dev);
|
struct ast_timer_priv *priv = dev_get_priv(dev);
|
||||||
|
|
||||||
*count = AST_TMC_RELOAD_VAL - readl(&priv->tmc->status);
|
return AST_TMC_RELOAD_VAL - readl(&priv->tmc->status);
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int ast_timer_ofdata_to_platdata(struct udevice *dev)
|
static int ast_timer_ofdata_to_platdata(struct udevice *dev)
|
||||||
|
@ -68,13 +68,12 @@ struct atcpit_timer_platdata {
|
|||||||
u32 *regs;
|
u32 *regs;
|
||||||
};
|
};
|
||||||
|
|
||||||
static int atcpit_timer_get_count(struct udevice *dev, u64 *count)
|
static u64 atcpit_timer_get_count(struct udevice *dev)
|
||||||
{
|
{
|
||||||
struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
|
struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
|
||||||
u32 val;
|
u32 val;
|
||||||
val = ~(REG32_TMR(CH_CNT(1))+0xffffffff);
|
val = ~(REG32_TMR(CH_CNT(1))+0xffffffff);
|
||||||
*count = timer_conv_64(val);
|
return timer_conv_64(val);
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int atcpit_timer_probe(struct udevice *dev)
|
static int atcpit_timer_probe(struct udevice *dev)
|
||||||
|
@ -25,15 +25,13 @@ struct atmel_pit_platdata {
|
|||||||
struct atmel_pit_regs *regs;
|
struct atmel_pit_regs *regs;
|
||||||
};
|
};
|
||||||
|
|
||||||
static int atmel_pit_get_count(struct udevice *dev, u64 *count)
|
static u64 atmel_pit_get_count(struct udevice *dev)
|
||||||
{
|
{
|
||||||
struct atmel_pit_platdata *plat = dev_get_platdata(dev);
|
struct atmel_pit_platdata *plat = dev_get_platdata(dev);
|
||||||
struct atmel_pit_regs *const regs = plat->regs;
|
struct atmel_pit_regs *const regs = plat->regs;
|
||||||
u32 val = readl(®s->value_image);
|
u32 val = readl(®s->value_image);
|
||||||
|
|
||||||
*count = timer_conv_64(val);
|
return timer_conv_64(val);
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int atmel_pit_probe(struct udevice *dev)
|
static int atmel_pit_probe(struct udevice *dev)
|
||||||
|
@ -57,13 +57,11 @@ ulong timer_get_boot_us(void)
|
|||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
static int cadence_ttc_get_count(struct udevice *dev, u64 *count)
|
static u64 cadence_ttc_get_count(struct udevice *dev)
|
||||||
{
|
{
|
||||||
struct cadence_ttc_priv *priv = dev_get_priv(dev);
|
struct cadence_ttc_priv *priv = dev_get_priv(dev);
|
||||||
|
|
||||||
*count = readl(&priv->regs->counter_val1);
|
return readl(&priv->regs->counter_val1);
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int cadence_ttc_probe(struct udevice *dev)
|
static int cadence_ttc_probe(struct udevice *dev)
|
||||||
|
@ -25,7 +25,7 @@ struct dw_apb_timer_priv {
|
|||||||
struct reset_ctl_bulk resets;
|
struct reset_ctl_bulk resets;
|
||||||
};
|
};
|
||||||
|
|
||||||
static int dw_apb_timer_get_count(struct udevice *dev, u64 *count)
|
static u64 dw_apb_timer_get_count(struct udevice *dev)
|
||||||
{
|
{
|
||||||
struct dw_apb_timer_priv *priv = dev_get_priv(dev);
|
struct dw_apb_timer_priv *priv = dev_get_priv(dev);
|
||||||
|
|
||||||
@ -34,9 +34,7 @@ static int dw_apb_timer_get_count(struct udevice *dev, u64 *count)
|
|||||||
* requires the count to be incrementing. Invert the
|
* requires the count to be incrementing. Invert the
|
||||||
* result.
|
* result.
|
||||||
*/
|
*/
|
||||||
*count = timer_conv_64(~readl(priv->regs + DW_APB_CURR_VAL));
|
return timer_conv_64(~readl(priv->regs + DW_APB_CURR_VAL));
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int dw_apb_timer_probe(struct udevice *dev)
|
static int dw_apb_timer_probe(struct udevice *dev)
|
||||||
|
@ -27,16 +27,14 @@ struct mchp_pit64b_priv {
|
|||||||
void __iomem *base;
|
void __iomem *base;
|
||||||
};
|
};
|
||||||
|
|
||||||
static int mchp_pit64b_get_count(struct udevice *dev, u64 *count)
|
static u64 mchp_pit64b_get_count(struct udevice *dev)
|
||||||
{
|
{
|
||||||
struct mchp_pit64b_priv *priv = dev_get_priv(dev);
|
struct mchp_pit64b_priv *priv = dev_get_priv(dev);
|
||||||
|
|
||||||
u32 lsb = readl(priv->base + MCHP_PIT64B_TLSBR);
|
u32 lsb = readl(priv->base + MCHP_PIT64B_TLSBR);
|
||||||
u32 msb = readl(priv->base + MCHP_PIT64B_TMSBR);
|
u32 msb = readl(priv->base + MCHP_PIT64B_TMSBR);
|
||||||
|
|
||||||
*count = ((u64)msb << 32) | lsb;
|
return ((u64)msb << 32) | lsb;
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int mchp_pit64b_probe(struct udevice *dev)
|
static int mchp_pit64b_probe(struct udevice *dev)
|
||||||
|
@ -187,7 +187,7 @@ void wait_ticks(ulong ticks)
|
|||||||
WATCHDOG_RESET();
|
WATCHDOG_RESET();
|
||||||
}
|
}
|
||||||
|
|
||||||
static int mpc83xx_timer_get_count(struct udevice *dev, u64 *count)
|
static u64 mpc83xx_timer_get_count(struct udevice *dev)
|
||||||
{
|
{
|
||||||
u32 tbu, tbl;
|
u32 tbu, tbl;
|
||||||
|
|
||||||
@ -201,9 +201,7 @@ static int mpc83xx_timer_get_count(struct udevice *dev, u64 *count)
|
|||||||
tbl = mftb();
|
tbl = mftb();
|
||||||
} while (tbu != mftbu());
|
} while (tbu != mftbu());
|
||||||
|
|
||||||
*count = (tbu * 0x10000ULL) + tbl;
|
return (tbu * 0x10000ULL) + tbl;
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int mpc83xx_timer_probe(struct udevice *dev)
|
static int mpc83xx_timer_probe(struct udevice *dev)
|
||||||
|
@ -27,14 +27,12 @@ struct mtk_timer_priv {
|
|||||||
void __iomem *base;
|
void __iomem *base;
|
||||||
};
|
};
|
||||||
|
|
||||||
static int mtk_timer_get_count(struct udevice *dev, u64 *count)
|
static u64 mtk_timer_get_count(struct udevice *dev)
|
||||||
{
|
{
|
||||||
struct mtk_timer_priv *priv = dev_get_priv(dev);
|
struct mtk_timer_priv *priv = dev_get_priv(dev);
|
||||||
u32 val = readl(priv->base + MTK_GPT4_CNT);
|
u32 val = readl(priv->base + MTK_GPT4_CNT);
|
||||||
|
|
||||||
*count = timer_conv_64(val);
|
return timer_conv_64(val);
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int mtk_timer_probe(struct udevice *dev)
|
static int mtk_timer_probe(struct udevice *dev)
|
||||||
|
@ -54,14 +54,12 @@ struct nomadik_mtu_priv {
|
|||||||
struct nomadik_mtu_timer_regs *timer;
|
struct nomadik_mtu_timer_regs *timer;
|
||||||
};
|
};
|
||||||
|
|
||||||
static int nomadik_mtu_get_count(struct udevice *dev, u64 *count)
|
static u64 nomadik_mtu_get_count(struct udevice *dev)
|
||||||
{
|
{
|
||||||
struct nomadik_mtu_priv *priv = dev_get_priv(dev);
|
struct nomadik_mtu_priv *priv = dev_get_priv(dev);
|
||||||
|
|
||||||
/* Decrementing counter: invert the value */
|
/* Decrementing counter: invert the value */
|
||||||
*count = timer_conv_64(~readl(&priv->timer->cv));
|
return timer_conv_64(~readl(&priv->timer->cv));
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int nomadik_mtu_probe(struct udevice *dev)
|
static int nomadik_mtu_probe(struct udevice *dev)
|
||||||
|
@ -48,13 +48,11 @@ struct omap_timer_priv {
|
|||||||
struct omap_gptimer_regs *regs;
|
struct omap_gptimer_regs *regs;
|
||||||
};
|
};
|
||||||
|
|
||||||
static int omap_timer_get_count(struct udevice *dev, u64 *count)
|
static u64 omap_timer_get_count(struct udevice *dev)
|
||||||
{
|
{
|
||||||
struct omap_timer_priv *priv = dev_get_priv(dev);
|
struct omap_timer_priv *priv = dev_get_priv(dev);
|
||||||
|
|
||||||
*count = timer_conv_64(readl(&priv->regs->tcrr));
|
return timer_conv_64(readl(&priv->regs->tcrr));
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int omap_timer_probe(struct udevice *dev)
|
static int omap_timer_probe(struct udevice *dev)
|
||||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user