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https://github.com/brain-hackers/u-boot-brain
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fix: phy: marvell: cp110: pcie: update analog parameters according to latest ETP
Add PCIE analog parameters initialization values according to latest ETP. Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
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528213d3fd
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ae07a70ac2
@ -232,6 +232,8 @@ static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src,
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mask |= HPIPE_MISC_REFCLK_SEL_MASK;
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data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET;
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}
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mask |= HPIPE_MISC_ICP_FORCE_MASK;
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data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET;
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reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
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if (pcie_clk) { /* output */
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/* Set reference frequcency select - 0x2 for 25MHz*/
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@ -267,6 +269,9 @@ static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src,
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/* Set Maximal PHY Generation Setting(8Gbps) */
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mask = HPIPE_INTERFACE_GEN_MAX_MASK;
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data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET;
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/* Bypass frame detection and sync detection for RX DATA */
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mask = HPIPE_INTERFACE_DET_BYPASS_MASK;
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data = 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET;
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/* Set Link Train Mode (Tx training control pins are used) */
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mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK;
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data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET;
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@ -351,9 +356,9 @@ static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src,
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data = 0x3 << HPIPE_G3_DFE_RES_OFFSET;
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reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
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/* Force DFE resolution (use GEN table value) */
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/* Use TX/RX training result for DFE */
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mask = HPIPE_DFE_RES_FORCE_MASK;
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data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
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data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET;
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reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
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/* Configure initial and final coefficient value for receiver */
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@ -379,9 +384,64 @@ static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src,
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data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET;
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mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK;
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data |= 0x1 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
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data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
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reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
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/* Pattern lock lost timeout disable */
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mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK;
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data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET;
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reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask);
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/* Configure DFE adaptations */
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mask = HPIPE_CDR_MAX_DFE_ADAPT_1_MASK;
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data = 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET;
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mask |= HPIPE_CDR_MAX_DFE_ADAPT_0_MASK;
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data |= 0x0 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET;
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mask |= HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK;
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data |= 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET;
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reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask);
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mask = HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK;
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data = 0x0 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET;
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reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask);
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/* Genration 2 setting 1*/
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mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
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data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
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mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK;
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data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET;
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mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
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data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
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reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
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/* DFE enable */
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mask = HPIPE_G2_DFE_RES_MASK;
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data = 0x3 << HPIPE_G2_DFE_RES_OFFSET;
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reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask);
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/* Configure DFE Resolution */
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mask = HPIPE_LANE_CFG4_DFE_EN_SEL_MASK;
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data = 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET;
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reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
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/* VDD calibration control */
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mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
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data = 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
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reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
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/* Set PLL Charge-pump Current Control */
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mask = HPIPE_G3_SETTING_5_G3_ICP_MASK;
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data = 0x4 << HPIPE_G3_SETTING_5_G3_ICP_OFFSET;
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reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask);
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/* Set lane rqualization remote setting */
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mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK;
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data = 0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET;
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mask |= HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK;
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data |= 0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET;
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mask |= HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK;
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data |= 0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET;
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reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask);
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if (!is_end_point) {
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/* Set phy in root complex mode */
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mask = HPIPE_CFG_PHY_RC_EP_MASK;
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@ -227,6 +227,9 @@
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#define HPIPE_INTERFACE_GEN_MAX_OFFSET 10
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#define HPIPE_INTERFACE_GEN_MAX_MASK \
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(0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
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#define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12
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#define HPIPE_INTERFACE_DET_BYPASS_MASK \
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(0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET)
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#define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14
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#define HPIPE_INTERFACE_LINK_TRAIN_MASK \
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(0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
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@ -444,6 +447,17 @@
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#define HPIPE_TX_TRAIN_PAT_SEL_MASK \
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(0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET)
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#define HPIPE_CDR_CONTROL_REG 0x418
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#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12
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#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \
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(0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)
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#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9
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#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \
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(0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET)
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#define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6
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#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \
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(0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET)
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#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438
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#define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6
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#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \
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@ -481,7 +495,11 @@
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(0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET)
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#define HPIPE_G2_SETTINGS_3_REG 0x448
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#define HPIPE_G2_SETTINGS_4_REG 0x44C
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#define HPIPE_G2_SETTINGS_4_REG 0x44c
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#define HPIPE_G2_DFE_RES_OFFSET 8
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#define HPIPE_G2_DFE_RES_MASK \
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(0x3 << HPIPE_G2_DFE_RES_OFFSET)
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#define HPIPE_G3_SETTING_3_REG 0x450
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#define HPIPE_G3_FFE_CAP_SEL_OFFSET 0
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@ -510,6 +528,11 @@
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#define HPIPE_TX_PRESET_INDEX_MASK \
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(0xf << HPIPE_TX_PRESET_INDEX_OFFSET)
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#define HPIPE_DFE_CONTROL_REG 0x470
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#define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14
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#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK \
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(0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET)
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#define HPIPE_DFE_CTRL_28_REG 0x49C
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#define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7
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#define HPIPE_DFE_CTRL_28_PIPE4_MASK \
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@ -520,6 +543,11 @@
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#define HPIPE_G1_SETTING_5_G1_ICP_MASK \
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(0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)
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#define HPIPE_G3_SETTING_5_REG 0x548
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#define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0
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#define HPIPE_G3_SETTING_5_G3_ICP_MASK \
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(0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET)
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#define HPIPE_LANE_CONFIG0_REG 0x600
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#define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0
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#define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \
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@ -542,6 +570,9 @@
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#define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0
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#define HPIPE_LANE_CFG4_DFE_CTRL_MASK \
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(0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
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#define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3
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#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK \
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(0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET)
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#define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6
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#define HPIPE_LANE_CFG4_DFE_OVER_MASK \
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(0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
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@ -559,6 +590,17 @@
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#define HPIPE_CFG_UPDATE_POLARITY_MASK \
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(0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
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#define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8
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#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0
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#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK \
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(0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET)
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#define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1
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#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK \
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(0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET)
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#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2
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#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK \
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(0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
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#define HPIPE_RST_CLK_CTRL_REG 0x704
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#define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
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#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \
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