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fix: phy: marvell: cp110: pcie: update analog parameters according to latest ETP

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Add PCIE analog parameters initialization values according to
latest ETP.

Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Igal Liberman 2017-04-24 18:45:33 +03:00 committed by Stefan Roese
parent 528213d3fd
commit ae07a70ac2
2 changed files with 106 additions and 4 deletions
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66
drivers/phy/marvell/comphy_cp110.c
View File

@ -232,6 +232,8 @@ static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src,
mask |= HPIPE_MISC_REFCLK_SEL_MASK;
data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET;
}
mask |= HPIPE_MISC_ICP_FORCE_MASK;
data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET;
reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
if (pcie_clk) { /* output */
/* Set reference frequcency select - 0x2 for 25MHz*/
@ -267,6 +269,9 @@ static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src,
/* Set Maximal PHY Generation Setting(8Gbps) */
mask = HPIPE_INTERFACE_GEN_MAX_MASK;
data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET;
/* Bypass frame detection and sync detection for RX DATA */
mask = HPIPE_INTERFACE_DET_BYPASS_MASK;
data = 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET;
/* Set Link Train Mode (Tx training control pins are used) */
mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK;
data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET;
@ -351,9 +356,9 @@ static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src,
data = 0x3 << HPIPE_G3_DFE_RES_OFFSET;
reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
/* Force DFE resolution (use GEN table value) */
/* Use TX/RX training result for DFE */
mask = HPIPE_DFE_RES_FORCE_MASK;
data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET;
reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
/* Configure initial and final coefficient value for receiver */
@ -379,9 +384,64 @@ static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src,
data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET;
mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK;
data |= 0x1 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
/* Pattern lock lost timeout disable */
mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK;
data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET;
reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask);
/* Configure DFE adaptations */
mask = HPIPE_CDR_MAX_DFE_ADAPT_1_MASK;
data = 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET;
mask |= HPIPE_CDR_MAX_DFE_ADAPT_0_MASK;
data |= 0x0 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET;
mask |= HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK;
data |= 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET;
reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask);
mask = HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK;
data = 0x0 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET;
reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask);
/* Genration 2 setting 1*/
mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK;
data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET;
mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
/* DFE enable */
mask = HPIPE_G2_DFE_RES_MASK;
data = 0x3 << HPIPE_G2_DFE_RES_OFFSET;
reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask);
/* Configure DFE Resolution */
mask = HPIPE_LANE_CFG4_DFE_EN_SEL_MASK;
data = 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET;
reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
/* VDD calibration control */
mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
data = 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
/* Set PLL Charge-pump Current Control */
mask = HPIPE_G3_SETTING_5_G3_ICP_MASK;
data = 0x4 << HPIPE_G3_SETTING_5_G3_ICP_OFFSET;
reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask);
/* Set lane rqualization remote setting */
mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK;
data = 0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET;
mask |= HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK;
data |= 0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET;
mask |= HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK;
data |= 0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET;
reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask);
if (!is_end_point) {
/* Set phy in root complex mode */
mask = HPIPE_CFG_PHY_RC_EP_MASK;

44
drivers/phy/marvell/comphy_hpipe.h
View File

@ -227,6 +227,9 @@
#define HPIPE_INTERFACE_GEN_MAX_OFFSET 10
#define HPIPE_INTERFACE_GEN_MAX_MASK \
(0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
#define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12
#define HPIPE_INTERFACE_DET_BYPASS_MASK \
(0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET)
#define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14
#define HPIPE_INTERFACE_LINK_TRAIN_MASK \
(0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
@ -444,6 +447,17 @@
#define HPIPE_TX_TRAIN_PAT_SEL_MASK \
(0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET)
#define HPIPE_CDR_CONTROL_REG 0x418
#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12
#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \
(0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)
#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9
#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \
(0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET)
#define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6
#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \
(0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET)
#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438
#define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6
#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \
@ -481,7 +495,11 @@
(0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET)
#define HPIPE_G2_SETTINGS_3_REG 0x448
#define HPIPE_G2_SETTINGS_4_REG 0x44C
#define HPIPE_G2_SETTINGS_4_REG 0x44c
#define HPIPE_G2_DFE_RES_OFFSET 8
#define HPIPE_G2_DFE_RES_MASK \
(0x3 << HPIPE_G2_DFE_RES_OFFSET)
#define HPIPE_G3_SETTING_3_REG 0x450
#define HPIPE_G3_FFE_CAP_SEL_OFFSET 0
@ -510,6 +528,11 @@
#define HPIPE_TX_PRESET_INDEX_MASK \
(0xf << HPIPE_TX_PRESET_INDEX_OFFSET)
#define HPIPE_DFE_CONTROL_REG 0x470
#define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14
#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK \
(0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET)
#define HPIPE_DFE_CTRL_28_REG 0x49C
#define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7
#define HPIPE_DFE_CTRL_28_PIPE4_MASK \
@ -520,6 +543,11 @@
#define HPIPE_G1_SETTING_5_G1_ICP_MASK \
(0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)
#define HPIPE_G3_SETTING_5_REG 0x548
#define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0
#define HPIPE_G3_SETTING_5_G3_ICP_MASK \
(0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET)
#define HPIPE_LANE_CONFIG0_REG 0x600
#define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0
#define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \
@ -542,6 +570,9 @@
#define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0
#define HPIPE_LANE_CFG4_DFE_CTRL_MASK \
(0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
#define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3
#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK \
(0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET)
#define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6
#define HPIPE_LANE_CFG4_DFE_OVER_MASK \
(0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
@ -559,6 +590,17 @@
#define HPIPE_CFG_UPDATE_POLARITY_MASK \
(0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
#define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8
#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0
#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK \
(0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET)
#define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1
#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK \
(0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET)
#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2
#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK \
(0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
#define HPIPE_RST_CLK_CTRL_REG 0x704
#define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \