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riscv: cpu: check and append L1 cache to cpu features

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All cpu cores within FU540-C000 having split I/D caches.
Set the L1 cache feature bit using the i-cache-size or d-cache-size
as one of the property from device tree indicating that L1 cache is
present on the cpu core.

=> cpu detail
  1: cpu@1      rv64imafdc
        ID = 1, freq = 999.100 MHz: L1 cache, MMU
  2: cpu@2      rv64imafdc
        ID = 2, freq = 999.100 MHz: L1 cache, MMU
  3: cpu@3      rv64imafdc
        ID = 3, freq = 999.100 MHz: L1 cache, MMU
  4: cpu@4      rv64imafdc
        ID = 4, freq = 999.100 MHz: L1 cache, MMU

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
This commit is contained in:
Sagar Shrikant Kadam 2020-06-28 07:45:03 -07:00 committed by Andes
parent b6b233ddb7
commit add0dc1f7d
1 changed files with 12 additions and 0 deletions
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12
drivers/cpu/riscv_cpu.c
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@ -35,6 +35,8 @@ static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info)
int ret;
struct clk clk;
const char *mmu;
u32 i_cache_size;
u32 d_cache_size;
/* First try getting the frequency from the assigned clock */
ret = clk_get_by_index(dev, 0, &clk);
@ -52,6 +54,16 @@ static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info)
if (mmu)
info->features |= BIT(CPU_FEAT_MMU);
/* check if I cache is present */
ret = dev_read_u32(dev, "i-cache-size", &i_cache_size);
if (ret)
/* if not found check if d-cache is present */
ret = dev_read_u32(dev, "d-cache-size", &d_cache_size);
/* if either I or D cache is present set L1 cache feature */
if (!ret)
info->features |= BIT(CPU_FEAT_L1_CACHE);
return 0;
}